JPS6384071A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent leakage to a substrate of electrons stored in a floating gate by removing an silicon-substrate impurity diffusion region in a fixed quantity so that a tunnel oxide-film forming prearranged region is all brought to an azimuth of plane (100). CONSTITUTION:A first oxide film 22 and a nitride film 23 are formed to the surface of an silicon single crystal substrate 21 having a p-type plane (100) azimuth and patterned, and a field region 24 is shaped through selective oxidation, using the nitride film 23 as a mask. The nitride film 23 is removed, the oxide film 22 and the field region 24 are etched, employing a resist 25 as a mask, and As<+> is implanted to form an n<+> region 26. The resist 25 is removed, the oxide film is etched, and a first gate oxide film 27 is shaped. The first gate oxide film 27 is removed by a resist 28, and surfaces except the azimuth of plane (100) are gotten rid of through etching. First gate polysilicon 30, an intermediate insulating film 31 and second gate polysilicon 32 are formed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides an electrically writable ROM (
The present invention relates to a method of manufacturing a semiconductor device having a cell (hereinafter referred to as E2FROM).

(Prior art) E2FROMs having various structures are known, one of which is to form an ultra-thin oxide film region of about 100 layers on a part of the gate oxide film, and to tunnel from this part. There is a type that injects and extracts electrons into and out of the floating gate.

The cell structure of a conventional E2FROM and its manufacturing method will be explained based on FIGS. 2 and 3.

FIG. 2 is a plan view showing an example of a conventional E2PROM cell, and FIG. 3 is a cross-sectional view showing the cross-sectional structure of the portion indicated by AA' in FIG. 2, step by step. First, as shown in FIG. 3(a), a first oxide film 2 and a nitride film 3 are sequentially deposited on the surface of a semiconductor substrate 1 whose main surface orientation is the (100) plane, and patterned using a resist. A structure is obtained in which the oxide film 2 and the nitride film 3 remain in predetermined regions.

Subsequently, after peeling off the resist used for patterning, selective oxidation is performed using this nitride film 3 as a mask to form a field oxide film 4.

Next, as shown in FIG. 3(b), after the nitride film 3 is peeled off, a resist 5 is formed which has been patterned in a predetermined manner in order to provide an n+ region immediately below the region where the tunnel oxide film is to be formed, and this resist 5 is used as a mask. As a step, the first oxide film 2 and the oxide film on the surface of the field region 4 are etched.

Next, by ion-implanting arsenic (As''), an n+ region 6 is formed directly under the region where the tunnel oxide film is to be formed.

In this step, when etching the oxide film, the boundary between the strand region and the field region 4 (indicated as E in the figure, and referred to as the LOCOS edge in the following explanation) is placed on the side of the field oxide film 4. retreat to.

Next, as shown in FIG. 3C, after the resist 5 is removed, the oxide film remaining in the device regions other than the n+ region 6 is removed by etching. At this time, Logos Edge retreats as before. Next, a first gate oxide film 7 is formed on the surface of the n-region 6.

Thereafter, a resist 8 is patterned for etching the first gate oxide film 7 in the area where the tunnel oxide film is to be formed.

Next, as shown in FIG. 3(d), the first gate oxide film 7 is etched using the patterned resist 8 as a mask, and after the resist 8 is peeled off, a tunnel oxide film 9 is formed. A first gate polysilicon 10 is then deposited over the entire surface of the substrate.

Thereafter, the first gate polysilicon 10 is patterned using a well-known technique, an interlayer insulating film 11 is formed on the surface of the first gate polysilicon 10, and a second gate polysilicon 12 is deposited on the surface. This second
By patterning the gate polysilicon 12, a structure as shown in FIG. 3(e) is obtained.

As described above, in the E2FROM according to the prior art described in FIGS. 2 and 3, the tunnel oxide film region spans the logos edge. However, in such a structure, Figure 3 (
As shown in e), due to the retreat of the logos edge in the four directions of the field region, a plane orientation different from the (100) plane orientation appears in the region where the tunnel oxide film is to be formed. (100)
Since there are many unbonded silicon molecules in plane orientations other than the plane direction, there are many levels in the oxide film formed on the silicon surface, and the electrons accumulated in the i-deflection gate are transferred to the substrate side through these levels. It will leak. Therefore, there is a problem that the data retention characteristics of the memory cell are poor.

To solve this problem, as shown in FIG. 4, a structure is adopted in which the tunnel oxide film region 9 does not overlap the logos edge, thereby improving data retention characteristics.

However, if such a structure is adopted, the cell size will become large.

(Problem to be Solved by the Invention) In order to form a tunnel oxide film region without increasing the cell size, it is necessary to adopt a structure in which the tunnel oxide film region overlaps the logo edge. According to this technique, deterioration of data retention characteristics due to regression of the logo edge has become a problem. Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause deterioration of data retention characteristics due to regression of the logo edge even when a cell structure in which the tunnel oxide film region extends over the logo edge is adopted. shall be.

[Structure of the invention]

(Means for Solving the Problems) According to the present invention, a tunnel oxide film region is formed on a semiconductor substrate having a (100) plane as a principal plane orientation so as to be in contact with a field oxide film formed by a selective oxidation method. Ta. E2F
'In a method for manufacturing a semiconductor device having a ROM cell,
After selectively removing the oxide film in region 1- where the tunnel oxide film is to be formed, and further removing the underlying semiconductor substrate by isomeric etching until all exposed surfaces have one principal plane orientation (100), tunnel oxide is applied to the exposed surfaces. It is characterized by forming a film.

(Function) In the manufacturing method according to the present invention, after etching the first gate oxide film, a predetermined amount of the underlying semiconductor substrate is removed by anisotropic etching, so that a logo edge is created around the area where the tunnel oxide film is to be formed. (100
) Even if plane orientations other than the (100) plane appear, they are all removed by anisotropic etching and only the (100) plane remains, so there are few levels existing in the tunnel oxide film, and therefore Electrons accumulated in the floating gate no longer leak to the substrate side. (Example) Hereinafter, an example of the present invention will be described in detail based on the step-by-step sectional views of elements shown in FIG.

Note that each step shown in FIG. 1 substantially corresponds to each step shown in FIG. 3. First, as shown in Figure 1(a), P type (10
0) A first oxide film 22 is formed on the surface of a silicon single crystal substrate 21 having an ili orientation, and then a nitride film 23 is deposited on this surface. Then, by performing patterning using a resist, a pattern is obtained in which the nitride film 23 and the first oxide film 22 remain in predetermined regions.

Next, after peeling off the resist used for this patterning, selective oxidation is performed using the nitride film 23 as a mask to form a field region 24.

Next, as shown in FIG. 1(b), the nitride film 23 is peeled off,
Add more oxidation. Next, patterning is performed using a resist 25 to form an n+ region 26 directly in the area where the tunnel oxide film is to be formed, and the oxide film 22 and field region 24 are etched using the patterned resist 25 as a mask. Next, As is 100
A dose of 5×101372 is implanted at keV to form an N″ region 26.

Then, as shown in FIG. 1C, the resist 25 is peeled off, and the oxide film remaining on the device regions other than the n region is etched away by immersing it in N 2 H, a 2 F solution, or the like. Thereafter, a first gate oxide film 27 is formed to a thickness of approximately 400 nm. Next, patterning for etching of the first gate oxide film 27 on the area where the tunnel oxide film is to be formed is performed using a resist 28, and the first gate oxide film 27 is etched away by immersing it in an NH4F solution using the resist 28 as a mask. do.

Next, as shown in FIG. 1(d), reactive ion etching (RIE) or other anisotropic etching is performed to etch the exposed surface of the semiconductor substrate 21 by a desired amount, so that only the (100) plane orientation is etched. be exposed.

By etching away the portion indicated by the dotted line in the figure, all planes other than the (100) plane, which were formed by the retreat of the logos edge around the area where the tunnel oxide film is to be formed, are etched and disappear.

The resist 28 is then removed, and a tunnel oxide film 29 is formed on this exposed surface to a thickness of approximately 100 nm.

This thickness needs to be selected appropriately because the thinner it is, the easier it is for electrons to enter, but the retention properties are worse. The subsequent steps are shown in Figure 1 (
As shown in e), the formation of the first gate polysilicon 30, the diffusion and patterning of phosphorus into the first gate polysilicon 30, the formation of the intermediate insulating film 31, the formation of the second gate polysilicon 32, and the formation of phosphorus thereto. Diffusion and patterning follow.

Figure 5 shows E2 with a cell structure formed in this way.
FIG. 3 is a characteristic diagram showing a change in the threshold voltage of FROM over time in comparison with a case using a conventional cell structure. As is clear from the figure, E2PR with angular cell structure using the present invention
It can be seen that the data retention properties of the OM are improved compared to those manufactured using conventional methods.

〔Effect of the invention〕

As described above in detail based on the embodiments, according to the manufacturing method of the present invention, a predetermined amount of the silicon substrate impurity diffusion region is removed so that the entire region where the tunnel oxide film is to be formed has a (100) plane orientation. Therefore, if the E2P structure is such that the tunnel oxide film region overlaps the logo edge,
A memory device having a ROM cell can be manufactured without deteriorating data retention characteristics.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an element according to each step to explain the manufacturing process of the present invention, and FIGS. 2 and 4 are each a conventional E2FR
FIG. 3 is a plan view showing an example of an OM cell, FIG. 3 is a cross-sectional view of the element by process to explain the conventional manufacturing method, and FIG. 5 is a diagram showing the data retention characteristics of E2PROM manufactured by the present invention and the conventional manufacturing method. This is what is shown. 1.21... Semiconductor substrate, 4.24... Field region, 6, 26... N region, 7, 27... First gate oxide film, 9.29... Tunnel oxide film. Applicant's agent Sato-Yukon 2 and 4

Claims (1)

[Claims] 1. An electrically writable semiconductor substrate having a tunnel oxide film region in contact with a field oxide film formed by a selective oxidation method on a semiconductor substrate whose principal plane is oriented in the (100) plane. In a method for manufacturing a semiconductor device having a ROM cell,
After selectively removing the oxide film on the region where the tunnel oxide film is to be formed, and further removing the underlying semiconductor substrate by anisotropic etching until all exposed surfaces have one principal plane orientation (100), 1. A method of manufacturing a semiconductor device, comprising forming a tunnel oxide film on a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the anisotropic etching is reactive ion etching.