JPS63246875A - Semiconductor storage device and manufacture thereof - Google Patents
Semiconductor storage device and manufacture thereofInfo
- Publication number
- JPS63246875A JPS63246875A JP8161587A JP8161587A JPS63246875A JP S63246875 A JPS63246875 A JP S63246875A JP 8161587 A JP8161587 A JP 8161587A JP 8161587 A JP8161587 A JP 8161587A JP S63246875 A JPS63246875 A JP S63246875A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- silicon nitride
- nitride film
- tunnel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000003860 storage Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 17
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 235000014676 Phragmites communis Nutrition 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical class ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体記憶装置に関するもので、特に情報の
書込みおよび消去が電気的に可能な不揮発性メモリ、い
わゆるＥ Ｅ Ｆ ＲＯＭ （Ｅｌｅｃｔｒｉｃａｌｌ
ｙ Ｅｒａｓａｂｌｅ ａｎｄ Ｐｒｏｇｒａｍｍａｂ
ｌｅ Ｒｅａｄ ０ｎｌｙ Ｍｅｍ。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a nonvolatile memory in which information can be written and erased electrically, so-called EEF ROM (Electrical Memory).
y Erasable and Programmable
le Read 0nly Mem.
ｒｙ）の構造とその製造方法に関するものである。ry) and its manufacturing method.
［従来の技術］
第２図は従来のＥＥＦＲＯＭセルの断面構造を模式的に
示した図である。第２図から見られるように、ＥＥＰＲ
ＯＭセルは、メモリトランジスタ部とセレクトトランジ
スタ部をそれぞれ形成する２つのＭＯＳ型トランジスタ
から構成される。メモリトランジスタは、半導体基板１
の活性領域に形成されるソース１６およびドレイン１７
と、半導体基板１上の電荷蓄積用のフローティングゲー
ト１２およびフローティングゲートの電荷蓄積動作を制
御するためのコントロールゲート１１とから構成される
。またフローティングゲート１２とドレイン領域１７と
の間には電荷の通路となるトンネル領域１４が設けられ
ている。このトンネル領域は厚さ１００λ程度の薄い絶
縁膜と、フローティングゲート１２とドレイン１７とで
構成される領域である。トンネル領域以外のフローティ
ングゲート１２と半導体基板１との間には、トンネル絶
縁膜より厚いゲート絶縁膜が形成される。[Prior Art] FIG. 2 is a diagram schematically showing the cross-sectional structure of a conventional EEFROM cell. As seen from Figure 2, EEPR
The OM cell is composed of two MOS transistors forming a memory transistor section and a select transistor section, respectively. The memory transistor is a semiconductor substrate 1
A source 16 and a drain 17 formed in the active region of
, a floating gate 12 for charge storage on the semiconductor substrate 1, and a control gate 11 for controlling the charge storage operation of the floating gate. Further, a tunnel region 14 is provided between the floating gate 12 and the drain region 17, which serves as a path for charges. This tunnel region is a region composed of a thin insulating film with a thickness of about 100λ, a floating gate 12, and a drain 17. A gate insulating film thicker than the tunnel insulating film is formed between the floating gate 12 and the semiconductor substrate 1 in areas other than the tunnel region.
セレクトトランジスタは、半導体基板１の活性領域に形
成されるソース（メモリトランジスタのドレインと共用
）１７およびビットライン１５と、半導体基板１上のワ
ードライン１３とから構成される。フローティングゲー
トへの電荷の注入およびフローティングゲートからの電
荷の放出は電極１８．１９．２０．２１へ適当な電位の
電圧を印加することにより行なわれる。The select transistor is composed of a source (shared with the drain of the memory transistor) 17 and a bit line 15 formed in the active region of the semiconductor substrate 1, and a word line 13 on the semiconductor substrate 1. Injection of charge into the floating gate and discharge of charge from the floating gate are performed by applying a voltage of an appropriate potential to the electrodes 18, 19, 20, 21.
第３図は従来のＥＥＰＲＯＭのトンネル領域形成工程を
示す断面図であり、図において１は半導体基板、２は基
板１と逆の導電型を示す不純物拡散層、３は５ｉ０２．
５はフォトレジスト、６は多結晶シリコン、７はトンネ
ル絶縁膜である。従来の方法では、まず素子分離領域を
形成した後、基板１の所望の場所に不純物拡散層２を形
成し、その表面をＳｉＯ□で覆う。この段階が３−１図
である。次にフォトレジスト５を塗布し、フォトリソグ
ラフィ技術で、フォトレジストに開孔部を設け、しかる
後、フッ酸系溶液により、フォトレジスト５の開孔部に
より、下地５ｉ０２３をエツチングする。この状態が３
−２図である。次に３−３図に示すようにフォトレジス
ト５を除去し、適当な表面清浄を行なう。さらに３−４
図に示すように、トンネル絶縁膜７を形成した後、多結
晶シリコン６をＬＰＣＶＤ法などで被着させる。このよ
うにしてトンネル領域を形成するのであるが、通常フォ
トレジスト５の膜厚は、１μｍ前後である。このため、
たとえば直径０．５μｍの開孔部をフォトレジストで形
成しても、そのアスペクト比は２となる。したがって直
径０．５μｍの穴の内部にフッ酸系溶液が浸透するのは
表面張力の影響によって極めて困難となる。一方、５ｉ
０２３のエツチングにプラズマエツチング技術を応用す
ることも考えられるが、この場合は、半導体基板１およ
び不純物拡散層２の表面にプラズマによる損傷を与えて
しまうためにその後に形成されるトンネル絶縁膜の絶縁
耐圧の劣化や信頼性の低下を招く。FIG. 3 is a cross-sectional view showing the process of forming a tunnel region of a conventional EEPROM. In the figure, 1 is a semiconductor substrate, 2 is an impurity diffusion layer having a conductivity type opposite to that of the substrate 1, and 3 is a 5i02.
5 is a photoresist, 6 is polycrystalline silicon, and 7 is a tunnel insulating film. In the conventional method, an element isolation region is first formed, then an impurity diffusion layer 2 is formed at a desired location on the substrate 1, and its surface is covered with SiO□. This stage is shown in Figure 3-1. Next, a photoresist 5 is applied, and openings are formed in the photoresist using photolithography, and then the base 5i023 is etched using the openings of the photoresist 5 using a hydrofluoric acid solution. This state is 3
-Figure 2. Next, as shown in Figure 3-3, the photoresist 5 is removed and appropriate surface cleaning is performed. 3-4 more
As shown in the figure, after forming the tunnel insulating film 7, polycrystalline silicon 6 is deposited by LPCVD or the like. The tunnel region is formed in this way, and the film thickness of the photoresist 5 is usually around 1 μm. For this reason,
For example, even if an opening with a diameter of 0.5 μm is formed using photoresist, its aspect ratio will be 2. Therefore, it is extremely difficult for a hydrofluoric acid solution to penetrate into a hole having a diameter of 0.5 μm due to the influence of surface tension. On the other hand, 5i
It is also possible to apply plasma etching technology to the etching of 023, but in this case, the insulation of the tunnel insulating film formed afterwards would be damaged due to plasma damage to the surfaces of the semiconductor substrate 1 and the impurity diffusion layer 2. This leads to deterioration of withstand voltage and reliability.
［発明が解決しようとする問題点］
従来のＥＥＦＲＯＭは以上のように構成されているので
、トンネル領域を開孔するのにフッ酸溶液を用いる湿式
プロセスで行なわなければならず、直径１μｍ以下の領
域を開孔することが極めて困難となり、サブミクロンの
開孔ができなくなるなどの問題点があった。またサブミ
クロンのトンネル領域が開孔できないため、メモリセル
を比例縮小することができず、大容量のＥＥＦＲＯＭが
得られなかった。[Problems to be Solved by the Invention] Since the conventional EEFROM is configured as described above, the tunnel region must be opened by a wet process using a hydrofluoric acid solution, and the tunnel region must be opened using a wet process using a hydrofluoric acid solution. There were problems such as it became extremely difficult to open holes in the area, and submicron holes could not be opened. Further, since the submicron tunnel region cannot be opened, the memory cell cannot be proportionally reduced, and a large-capacity EEFROM cannot be obtained.
この発明は上記のような問題点を解消するためになされ
たもので、サブミクロンのトンネル領域を開孔できると
ともに、開孔プロセスで誘起される酸化膜欠陥の発生を
抑制でき、高密度のＥＥＦＲＯＭを得ることを目的とす
る。This invention was made to solve the above-mentioned problems, and it is possible to open a submicron tunnel region, suppress the occurrence of oxide film defects induced in the opening process, and improve the performance of high-density EEFROM. The purpose is to obtain.
［問題点を解決するための手段］
この発明に係るＥＥＰＲＯＭは、トンネル領域を開孔す
る前に、基板表面に５ｔ３Ｎ、／５ｉ０２の２層膜を形
成し、プラズマエツチング法によりＳｉ、Ｎ、膜に開孔
部を作り、このＳｔ、Ｎ４膜をマスクとして下地のＳｉ
Ｏ□をフッ酸系エツチング液で除去するようにしたもの
である。[Means for Solving the Problems] In the EEPROM according to the present invention, before opening the tunnel region, a two-layer film of 5t3N and /5i02 is formed on the substrate surface, and Si, N, and the film are removed by plasma etching. An opening is made in the Si substrate using the St, N4 film as a mask.
The O□ is removed using a hydrofluoric acid etching solution.
［作用コ
この発明における５ｉ０２膜エツチングのためのＳｉ、
Ｎ、膜は厚さ１００ＯＡ程度であるため、直径１．０μ
ｍ程度の孔でもアスペクト比は０゜１程度となり、微小
な孔を５ｉｎ２上にあけることができる。[Function] Si for etching the 5i02 film in this invention,
N, since the film is about 100OA thick, the diameter is 1.0μ.
Even if the hole is about m in size, the aspect ratio will be about 0°1, and a minute hole can be made on the order of 5 in2.
［発明の実施例］ 以下この発明の一実施例を図について説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.
第１図において１は半導体基板、２はこの半導体基板と
反対の導電型を有する不純物拡散層、３は５ｉ０２．４
はシリコン窒化膜（ｓｉ３Ｎ４）、５はフォトレジスト
、６は多結晶シリコン電極である。第１図は、この発明
によるＥＥＰＲＯＭのトンネル領域形成工程のみを抜粋
したものである。In FIG. 1, 1 is a semiconductor substrate, 2 is an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate, and 3 is 5i02.4.
5 is a silicon nitride film (si3N4), 5 is a photoresist, and 6 is a polycrystalline silicon electrode. FIG. 1 is an excerpt of only the process of forming a tunnel region of an EEPROM according to the present invention.
１−１図において、まず、半導体基板１の所望の場所に
不純物拡散層２を形成し、その表面をＳｉＯ□３で覆う
。不純物拡散層２を形成する前に、いわゆるフィールド
工程、たとえばＬＯＧＯＳ（Ｌｏｃａｌ ０ｘｉｄａｔ
ｉｏｎ ｏｆ’ ５ｉｌｉｃｏｎ）法などで、素子分離
領域を形成しておくのは言うまでもない。次に、従来の
方法では、この５ｉ０２３の上に直接にフォトレジスト
を塗布し、一般的な光りソグラフィ技術によって、フォ
トレジストに開孔パターンを形成していたが、本発明で
は、５ｉ０２３を形成した後、さらにＳＬ、Ｎ４４をた
とえばＬＰＣＶＤ法で被着させ、Ｓｉ３Ｎ４／５ｉ０２
の２層膜を形成する。この状態が１−２図である。次に
１−３図に示したように、フォトリソグラフィ技術でフ
ォトレジスト５に所望の開孔パターンを形成し、フォト
レジスト５をマスクとして下地のＳｔ、Ｎ、４をエツチ
ングする。この際たとえばＣＦ４＋Ｏ□プラズマなどを
用いたドライプロセスで５１３Ｎ４をエツチングする。1-1, first, an impurity diffusion layer 2 is formed at a desired location on a semiconductor substrate 1, and its surface is covered with SiO□3. Before forming the impurity diffusion layer 2, a so-called field process, for example, LOGOS (Local Oxidat
Needless to say, the element isolation region is formed using a method such as ion of 5 silicon. Next, in the conventional method, a photoresist was applied directly onto this 5i023, and an opening pattern was formed in the photoresist using a general photolithography technique, but in the present invention, a hole pattern was formed on the photoresist. After that, SL and N44 are further deposited by, for example, LPCVD method, and Si3N4/5i02
A two-layer film is formed. This state is shown in Figure 1-2. Next, as shown in FIG. 1-3, a desired opening pattern is formed in the photoresist 5 by photolithography, and the underlying St, N, and 4 layers are etched using the photoresist 5 as a mask. At this time, 513N4 is etched by a dry process using, for example, CF4+O□ plasma.
このため、フォトレジストの開孔径がサブミクロンであ
っても、下地５１３Ｎ４は十分にエツチング可能である
。Therefore, even if the opening diameter of the photoresist is submicron, the underlying layer 513N4 can be sufficiently etched.
また、プラズマエツチングの条件を適当に選ぶことによ
って、Ｓｉ、Ｎ、４の下部にあるＳｉｎ。In addition, by appropriately selecting the plasma etching conditions, Si, N, and Sin below 4 can be removed.
３をほとんどエツチングすることな（Ｓｉ３Ｎ４４だけ
を選択的に除去することが可能である。次に、フォトレ
ジスト５を除去した後、Ｓｔ、Ｎ。3 (it is possible to selectively remove only Si3N44). Next, after removing the photoresist 5, St, N.
４をマスクとしてフッ酸系溶液を用いてＳｉｎ。4 as a mask and using a hydrofluoric acid solution.
３をエツチングする。このＳｉ、Ｎ、４の膜厚は１００
０Å以下であるため、Ｓｉ、Ｎ４４の開孔部におけるア
スペクト比は０．１以下となり、フッ酸系溶液は表面張
力の影響を受けずに５ｉ０２３にサブミクロンの開孔部
を形成することができる。この状態が１−４図である。Etch 3. The film thickness of this Si, N, 4 is 100
Since it is 0 Å or less, the aspect ratio in the openings of Si and N44 is 0.1 or less, and the hydrofluoric acid solution can form submicron pores in 5i023 without being affected by surface tension. . This state is shown in Figure 1-4.
また、５ｉ０２３は湿式エツチングされるため、半導体
基板１および、不純物拡散層２の表面には何らの損傷も
与えることはない。しかる後、適当な表面クリーニング
を行なって、トンネル絶縁膜７たとえば５ｔＯ２や５ｉ
ＯｘＮｙ（オキシナイトライド）、ナイトロキサイド（
ｎｙｔｒｏｘｉｄｅ）などを形成した後、浮遊ゲートと
なる多結晶シリコン６をたとえばＬＰＣＶＤ法で被着せ
しめる。この段階が１−５図である。後は従来のＥＥＰ
ＲＯＭ製造法に従って所望の回路を構成すればよい。Furthermore, since 5i023 is wet-etched, the surfaces of semiconductor substrate 1 and impurity diffusion layer 2 are not damaged in any way. After that, appropriate surface cleaning is performed and the tunnel insulating film 7 is coated with a material such as 5tO2 or 5i.
OxNy (oxynitride), nitroxide (
After forming a polycrystalline silicon 6, which will become a floating gate, for example, is deposited by LPCVD. This stage is shown in Figures 1-5. The rest is conventional EEP
A desired circuit may be constructed according to the ROM manufacturing method.
［発明の効果コ
以上のように、この発明によれば、トンネル領域を形成
する前に半導体基板表面にＳｉ、Ｎ、／ＳｉＯ２の２層
膜を形成し、Ｓｔ、Ｎ４をプラズマエツチングでパター
ニングし、しかる後、Ｓｉ、Ｎ、をマスクとして５ｉ０
２をフッ酸系溶液を用いた湿式法でエツチングするため
に、サブミクロンのトンネル領域を基板表面に何らの損
傷をも与えずに開孔することが可能となる。また、サブ
ミクロンのトンネル領域が開孔できることにより、メモ
リセルを比例縮小することが可能となり、大容量で高信
頼性のあるＥＥＦＲＯＭを得られる効果がある。[Effects of the Invention] As described above, according to the present invention, before forming a tunnel region, a two-layer film of Si, N, /SiO2 is formed on the surface of a semiconductor substrate, and St and N4 are patterned by plasma etching. , then 5i0 with Si, N, as a mask.
Since 2 is etched by a wet method using a hydrofluoric acid solution, a submicron tunnel region can be formed without causing any damage to the substrate surface. Furthermore, since a submicron tunnel region can be opened, it becomes possible to proportionally reduce the size of the memory cell, which has the effect of providing a large-capacity, highly reliable EEFROM.
第１図はこの発明の一実施例によるＥＥＦＲＯＭのトン
ネル領域形成工程を示す断面図、第２図は従来のＥＥＦ
ＲＯＭセルの断面構造を模式的に示した図、第３図は従
来のＥＥＦＲＯＭのトンネル領域形成工程を示す断面図
である。
１は半導体基板、２は不純物拡散層、３はＳｉＯ□、４
は”ａＮ＊、５はフォトレジスト、６は多結晶シリコン
、７はトンネル絶縁膜、１１はコントロールゲート、１
２はフローティングゲート、１３はワードライン、１４
はトンネル領域、１５はビットライン、１６はメモリト
ランジスタのソース、１７はメモリトランジスタのドレ
イン、１８．１９．２０．２１は電極である。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a sectional view showing the process of forming a tunnel region of an EEFROM according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional EEFROM.
FIG. 3 is a diagram schematically showing a cross-sectional structure of a ROM cell, and FIG. 3 is a cross-sectional view showing a process of forming a tunnel region of a conventional EEFROM. 1 is a semiconductor substrate, 2 is an impurity diffusion layer, 3 is SiO□, 4
is "aN*," 5 is photoresist, 6 is polycrystalline silicon, 7 is tunnel insulating film, 11 is control gate, 1
2 is a floating gate, 13 is a word line, 14
15 is a tunnel region, 15 is a bit line, 16 is a source of a memory transistor, 17 is a drain of a memory transistor, and 18, 19, 20, and 21 are electrodes. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (5)
前記不純物拡散層上で、トンネル絶縁膜を除く部分に形
成されたシリコン酸化膜とシリコン窒化膜の２層膜とを
少なくとも一部に有することを特徴とする半導体記憶装
置。(1) a substrate, an impurity diffusion layer formed on the substrate,
A semiconductor memory device characterized in that at least a portion of the impurity diffusion layer has a two-layer film of a silicon oxide film and a silicon nitride film formed in a portion excluding a tunnel insulating film.
ることを特徴とする特許請求の範囲第１項記載の半導体
記憶装置。(2) The semiconductor memory device according to claim 1, wherein the silicon nitride film has a thickness of 1000 Å or less.
し、前記不純物拡散層上にシリコン酸化膜を形成し、前
記シリコン酸化膜上にシリコン窒化膜を形成し、前記シ
リコン窒化膜上に所望の開孔パターンを有するフォトレ
ジスト層を形成し、前記フォトレジストをマスクとして
下地のシリコン窒化膜をエッチングし、次に前記フォト
レジストを除去した後、前記所定の形状を有するシリコ
ン窒化膜をマスクとして前記シリコン酸化膜をエッチン
グしてトンネル領域を形成し、次に前記エッチングを行
なった箇所にトンネル絶縁膜を形成する工程を一部に含
むことを特徴とする半導体記憶装置の製造方法。(3) Prepare a substrate, form an impurity diffusion layer on the substrate, form a silicon oxide film on the impurity diffusion layer, form a silicon nitride film on the silicon oxide film, and form a silicon nitride film on the silicon nitride film. A photoresist layer having a desired opening pattern is formed, the underlying silicon nitride film is etched using the photoresist as a mask, and after the photoresist is removed, the silicon nitride film having the predetermined shape is etched. A method for manufacturing a semiconductor memory device, comprising a step of etching the silicon oxide film as a mask to form a tunnel region, and then forming a tunnel insulating film in the etched area.
プラズマエッチングすることを特徴とする特許請求の範
囲第３項記載の半導体記憶装置の製造方法。(4) The method for manufacturing a semiconductor memory device according to claim 3, wherein the silicon nitride film is plasma-etched in the opening of the tunnel region.
ることを特徴とする特許請求の範囲第３項または４項に
記載の半導体記憶装置の製造方法。(5) The method for manufacturing a semiconductor memory device according to claim 3 or 4, wherein the silicon nitride film has a thickness of 1000 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8161587A JPS63246875A (en) | 1987-04-01 | 1987-04-01 | Semiconductor storage device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8161587A JPS63246875A (en) | 1987-04-01 | 1987-04-01 | Semiconductor storage device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63246875A true JPS63246875A (en) | 1988-10-13 |
Family
ID=13751224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8161587A Pending JPS63246875A (en) | 1987-04-01 | 1987-04-01 | Semiconductor storage device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63246875A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0788144A1 (en) * | 1996-01-31 | 1997-08-06 | STMicroelectronics S.r.l. | Process for fabricating tunnel-oxide nonvolatile memory devices |
| JP2006024932A (en) * | 2004-07-06 | 2006-01-26 | Samsung Electronics Co Ltd | Method for forming tunneling insulating layer of nonvolatile memory device |
-
1987
- 1987-04-01 JP JP8161587A patent/JPS63246875A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0788144A1 (en) * | 1996-01-31 | 1997-08-06 | STMicroelectronics S.r.l. | Process for fabricating tunnel-oxide nonvolatile memory devices |
| JP2006024932A (en) * | 2004-07-06 | 2006-01-26 | Samsung Electronics Co Ltd | Method for forming tunneling insulating layer of nonvolatile memory device |
| US7429511B2 (en) | 2004-07-06 | 2008-09-30 | Samsung Electronics Co., Ltd. | Method of forming a tunneling insulating layer in nonvolatile memory device |
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