JPS6112302B2 - - Google Patents
Info
- Publication number
- JPS6112302B2 JPS6112302B2 JP952583A JP952583A JPS6112302B2 JP S6112302 B2 JPS6112302 B2 JP S6112302B2 JP 952583 A JP952583 A JP 952583A JP 952583 A JP952583 A JP 952583A JP S6112302 B2 JPS6112302 B2 JP S6112302B2
- Authority
- JP
- Japan
- Prior art keywords
- read
- address
- advance
- function
- access request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP952583A JPS59139431A (ja) | 1983-01-24 | 1983-01-24 | 先行読出し抑止方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP952583A JPS59139431A (ja) | 1983-01-24 | 1983-01-24 | 先行読出し抑止方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59139431A JPS59139431A (ja) | 1984-08-10 |
JPS6112302B2 true JPS6112302B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1986-04-07 |
Family
ID=11722681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP952583A Granted JPS59139431A (ja) | 1983-01-24 | 1983-01-24 | 先行読出し抑止方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59139431A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
-
1983
- 1983-01-24 JP JP952583A patent/JPS59139431A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59139431A (ja) | 1984-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5255374A (en) | Bus interface logic for computer system having dual bus architecture | |
EP0587865B1 (en) | Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types | |
US4792926A (en) | High speed memory system for use with a control bus bearing contiguous segmentially intermixed data read and data write request signals | |
JP2997521B2 (ja) | 半導体メモリ | |
US4320457A (en) | Communication bus acquisition circuit | |
EP0081961A2 (en) | Synchronous data bus system with automatically variable data rate | |
EP0186006A2 (en) | Multiprocessor system | |
US5263139A (en) | Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems | |
JPH01200459A (ja) | メモリ・インターフエース機構 | |
US4158883A (en) | Refresh control system | |
JPS6112302B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
US4695947A (en) | Virtual address system having fixed common bus cycles | |
JPS61165170A (ja) | バス制御方式 | |
EP0923031B1 (en) | Method for reading data from a shared memory in a multiprocessor computer system | |
US6499087B1 (en) | Synchronous memory sharing based on cycle stealing | |
JPS63180153A (ja) | キヤツシユ記憶のラインバツク制御方式 | |
JPH05108545A (ja) | Dmaコントローラ | |
JP2976417B2 (ja) | マルチプロセッサシステム | |
JPH05120206A (ja) | Dmaコントローラ | |
JPS63201810A (ja) | 情報処理システムの時刻方式 | |
JPH0351017B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
JPH08212170A (ja) | メモリ制御装置及びその方法 | |
JPS6029856A (ja) | マルチプロセツサ・システムにおけるロ−カルメモリのアクセス制御方式 | |
JPH0528090A (ja) | メモリ制御装置 | |
JPH04247391A (ja) | 時分割方式2ポートメモリ |