JPS61122752A - Microprogram control device - Google Patents

Abstract

PURPOSE:To attain multifunction and high speed performance without expanding the word length of a microinstruction by connecting control FF groups correspondingly to an address range and selecting an optional FF in accordance with the output of an address register. CONSTITUTION:A microinstruction is read out from a control storage 2 and stored in a reading register 3 to discriminate the type of the instruction. If the instruction is the one for sensing the control FF to be used in common in the whole address range, a signal outputted by the 1st decoding circuit 4 makes a sensing circuit 11 sense one FF in the control FF group 8. If the instruction is the one for sensing the control FFs effective only in the address range divided into n sections, one FF in the control FF group 6 is selected by a selector circuit 9 on the basis of the output of an address register 1 addressing the storage 2 at that point. Similarly, the FF group 7 is also selected by a selector circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device @EC used in a data processing device, and particularly to a definition area in a microinstruction for selecting a control flip-flop.

(Prior Art) Conventionally, in the microinstructions of this type of microprogram 1 control device, each definition area is limited due to the limitation of the size of the microinstructions, and the type of 71 microinstructions constituting the microinstructions and register selection are limited. The definition area for defining the control frit tube ψ tube and the branch 7 dress was determined to be optimal for the intended device.

(Problem to be solved by the invention) Therefore, in a system that requires multi-functionality, it is necessary to use a large number of control FOPs in the microprogram, and the number of control FOPs defined by the definition area is In addition to the flip-flop, it is necessary to provide a table managed by a microprogram inside the control memory and use it as a substitute for the control flip-flop, which hinders high-speed performance.

In addition, as memory elements become more highly integrated, there is a tendency to shorten the word length of microinstructions in order to improve the price/performance ratio, and there is a drawback that it is difficult to expand the definition area.

An object of the present invention is to eliminate the above-mentioned drawbacks and expand the definition area of microinstructions by using a part of the address register that addresses the control storage that stores the microprogram for selecting a group of control flip-flops. This makes multi-functionality easier, and
It is an object of the present invention to provide a microprogram control device that can shorten the microinstruction word length by mF1t. , a read register, Ill and a second decoding circuit, a plurality of control flip-flop groups, a plurality of selector circuits, and a sense circuit.

Control storage is for storing microprograms.

The address register is for addressing control storage.

The read register is for temporarily storing the microprogram read from the control storage.

The first decoding circuit is for decoding part of the output of the read register.

The second decoding circuit is for decoding part of the output of the 7 dress register.

The plurality of control flip-flop groups are for respectively storing states corresponding to the outputs of the Ill decoding circuit and the second decoding circuit at the time of data setting.

The plurality of selector circuits each select one of the outputs of the plurality of control flip-flop groups based on a portion of the output of the address register.

The sense circuit is for selecting one of the outputs of the plurality of selector circuits based on the output of the first decoding circuit.

(Implementation fl!) Next, the present invention will be explained in detail with reference to the drawings.

#L showing an embodiment of the present invention In the figure, 1 is an address register, 2 is a control storage, 3 is a read register, 4 is a first decoding circuit, 5 is a decoding circuit of Hayabusa 2, and 6 to 8 are respective control Flip-flop group for 9
, 10 are the first and second selector circuits, 11 respectively.
．． 12 are a first sense circuit and a second sense circuit, respectively.

In Figure 1, the output of address register 1 is (?(4
6101, the output of the control storage 2 is connected to the read register 6 via the signal line 102, and the output of the read register 6 is connected to the first decode circuit 4 via the signal @103. has been done. A part of the output of the address register 1 is connected to the decode circuit 5 of l1k2, the selector circuit 9 of Hayabusa 1, and the m-th selector circuit 10 via a signal 104. The output of the first decoding circuit 4 is the signal line 105
It is connected to control flip-flop groups 6 to B, a first sense circuit 11, and a second sense circuit 12 via. The output of the second decoding circuit 5 is connected to a group of 11 block flops 6 and 7 for control via a signal line 106,
The output of the control flip-flops 6 and 7 is the signal $107.
, 108 to the first selector circuit 9 and the m-th selector circuit 10, respectively, and the outputs of the ]-th selector circuit 9 and the m-th selector circuit 10 are connected to the signal line 1.
09 to the sense circuit 12 of I42. Roughly speaking, the set data signal line 111 is connected to the control flip-flop groups 6-8.

In this embodiment, the control flip-flop group is divided into two, a control flip-flop group 8 that can be used in common in the entire address range regardless of the contents of the address register, and a control flip-flop group 8 that can be used in common in the entire address range regardless of the contents of the address register. Control flip-flop group that can be accessed only within the divided address range 6.7
and. However, a configuration in which the control flip-flop 8, which can be used in common in all seven dress ranges, is not provided may be used.

Now, when a microinstruction is read from the control storage 2 and stored in one read register, the type of the microinstruction is determined. If this microinstruction is an instruction to sense a control flip-flop that can be commonly used in the entire ATOSYS range, the output signal decoded by the first decode circuit 4 is sent to the control flip-flop group 8 via the signal line 105. inside flip flop b1
~bp can be sensed by the first sense circuit 11. If the type of microinstruction is an instruction that senses a control flip-flop that is valid only within the address range divided into n addresses, at this point the output of address register 1 (signal Line 104) selects one of the flip-flops all to atn in the control flip-flop group 6 by the selector circuit 9 of @], and similarly selects the flip-flop "m1" in the control flip-flop group 7.
~'mn is selected by the selector circuit 10. Roughly speaking, one of the outputs of the selector circuits 9 and 100 (on the F1 line 109) is sent by the second sense circuit 12 according to the decoded output signal on the signal line 105 of the decode circuit 4 of 1FLL. can sense.

If the type of microinstruction is a data set instruction for a control flip-flop that can be used in common in the entire address range, the first decode circuit 4 selects the flip-flops b1 to bp in the control flip-flop group 8.
One of them is selected and data is set via the set data signal line 111. Similarly, if it is a data set command for a control flip-flop that is valid only within an address range divided into n addresses, the first decode circuit 4 sends a neutral signal to the staff member 1m105, and the address register 1 sends a signal @ The output on 104 is decoded and the code a1106 is
All
``aln to aln+ = amHt, and data is set via the set data signal line 111.

(Effects of the Invention) As explained above, the present invention has an advantage in that a control flip-flop group is provided corresponding to the address range and is configured to be selected by the output of the address register. This has the effect of making it possible to increase the number of functions and high-speed performance without increasing the length.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially illustrating one embodiment of a microprogram controlled instrument according to the present invention. 1. address register 2...Φ control storage 3... read register 4.5... decoding circuits 6-8@-e control flip-flop group 910... selector circuit It, 12... Sense circuit patent source NEC Corporation

Claims (1)

[Claims] a control storage for storing a microprogram, an address register for addressing the control storage, a read register for temporarily storing the microprogram read from the control storage, and an output of the read register. a first decoding circuit for decoding a part of the output of the address register; a second decoding circuit for decoding a part of the output of the address register; and the first decoding circuit and the second decoding circuit when setting data. a plurality of control flip-flop groups for respectively storing states corresponding to the outputs of the plurality of control flip-flops; multiple selector circuits for selection;
A microprogram control device comprising: a sense circuit for selecting one of the outputs of the plurality of selector circuits based on the output of the first decoding circuit.