JPS61125646A - Microprogram controller - Google Patents

Abstract

PURPOSE:To attain the multiple functions and the high-speed performance of a microprogram controller without increasing the word length of a microinstruction, by providing plural register groups in response to an address range, and selecting a specified register among those register groups with the output of an address register. CONSTITUTION:An output signal source 101 of an address register 1 is connected to a control storage 2, and an output signal source 102 of the storage 2 is connected to a reading register 3. An output signal source 103 of the register 3 is connected to the 1st decoding circuit 4, the 1st A type selector circuits 10-11, the 1st B type selector 13-14, a C type selector circuit 18 and a D type selector circuit 19 respectively. The output of the circuit 4 is supplied to the 1st-6th register groups 6-9, 16 and 17 through a signal line 105. The output of the register 1 is partly supplied to the 2nd decoder circuit 5 and the 2nd A and B type selector circuits 12 and 15, respectively. Then the output of the circuit 5 is supplied to the 1st-4th register groups 6-9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device in a data processing device, and particularly to a definition area for selecting a register in a microinstruction.

(Prior Art) Conventionally, in microinstructions of this type of microprogram control device, the type of microinstructions constituting the microinstructions, the definition of register selection, the definition of control flip 70 knobs, and the branch address are based on the microinstruction word length. Due to these limitations, each definition area has to be restricted, and the width of each definition area is determined to be optimal for the target device rjtK.

(Problem to be solved by the invention) Therefore, in devices that require multifunctionality, it is necessary to use multiple registers in the microprogram, and registers other than the number defined in the definition area are used for control. It was necessary to set up a table in memory that was managed by a microprogram and use this as a substitute, which prevented high-speed performance.

Furthermore, as memory elements become more highly integrated, there is a trend to reduce the length of microinstruction words in order to improve the price/performance ratio, making it difficult to expand the definition area.

An object of the present invention is to eliminate the above-mentioned drawbacks by using a part of the address register for addressing the control storage that stores the microprogram for register selection, and making it possible to expand the definition area in the microinstruction. Another object of the present invention is to provide a microprogram control device configured to be easily multifunctional and to reduce the length of microinstruction words.

(Means for Solving the Problems) A microprogram control device according to the present invention includes a control storage, an address register, a read register, a first Th and a second decoding circuit, a plurality of register groups, a first Th and a second The selector circuit group includes arithmetic logic means.

The control storage is for storing microprograms, the address register is for addressing the control storage, and the read register is for temporarily storing the microprogram read from the control storage. be.

The first decoder circuit is for decoding part of the output of the read register, and the second decoder circuit is for decoding part of the address register.

The plurality of register groups are for storing data output from the lal decoding circuit in a specific register having an address designated by the output of the second decoding circuit when setting data.

The first selector circuit group is for selecting four outputs of a specific register having a designated address from among the outputs of a plurality of register groups, which are spread over a portion of the outputs of the read registers.

The second selector circuit group is for selecting one of the outputs of the first selector circuit in accordance with a portion of the output of the address register.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram partially illustrating an embodiment of a microprogram control device according to the present invention. In FIG. 1, 1 is an address register, 2 is a control storage, 3 is a read register, 4.5 is a first and second decoding circuit, respectively, 6 to 9, 16.17 are a register and a meta group, respectively, and 10 to 12 is a doll selector circuit, 13 to 15 are B type selector circuits, 18 is a C type selector circuit, 19 is a D type selector circuit, and 20 is an arithmetic logic circuit.

In FIG. 1 K) showing an embodiment of the present invention, the output signal line 101 of the address register 1 is connected to the control storage 2, and the output signal @10 of the control storage 2 is connected to the output signal line 101 of the address register 1.
2 is connected to the read register 3. The output signal @ 103 of the read register 3 is sent to the first decoding circuit 4,
The first doll selector circuits 10 to 11, the 1X10B type selector circuits 13 to 14, the C type selector circuit 18, and the D
It is connected to the shape selector circuit 19. The output of the first decoding circuit 4 is connected to the first to sixth register groups 6 to 9, 16.17 through a signal line 105. A part of the output of the address register 1 is sent to the second decode circuit 5, the second doll selector circuit 12, and the second doll selector circuit 12 via the signal line 104.
The B-type selector circuit 15 is connected to the B-type selector circuit 15. The output of the second decoding circuit 5 is connected to the first to fourth registers n6-9 via a signal 41106.

The output of the first register #6 is transmitted to the first register #6 via the signal line 107.
is connected to the doll selector times @10, and the second selector n
The output of 7 is connected to the first doll selector circuit 11 via the signal line 108, the output of the third register group 8 is connected to the first B-type selector circuit 13 via the signal line 111, and the output of the 4th The output of the register #9 is connected to the first B type selector circuit 14 via the signal line 112, the output of the lX5 register group 16 is connected to the 0 type selector circuit 18 via the signal line 115, The output of register #17 is connected to D-type selector circuit 19 via signal $117. The outputs of the first doll selector circuits 10-11 are connected to the second doll selector circuit @12 via the signal line 109, and the outputs of the first B-type sector V sector circuits 13-14 are connected via the signal line 113. and is connected to the second B-type selector circuit 15.

The output of the second doll selector circuit 12 is connected to the A bus 201K via the signal line 110, and the 0 type selector circuit 18
The output is connected to the A bus 201 via the signal line 116 and input to the arithmetic logic unit 20. The output of the second B-type selector circuit 15 is connected to the B bus 202 via the signal line 114, and the output of the D-type selector circuit 19 is connected to the signal line 118.
is connected to the B bus 202 via the arithmetic logic unit 1t2.
It is input to 0. The output of the arithmetic logic unit 20 is connected to the D bus 2.
1st to 6th registers via 03! #6-9, 16
, 171c are connected.

In this embodiment, the register group is divided into four groups, which can be used in common in the entire address range regardless of the contents of the address register.The fifth register group 16 is for A bus input, and the sixth register group is for B bus input. Register group 17 and address range fm
A first or second register group 6, 7 for A bus input, which can be divided into individual groups and accessed only within each divided address range, and a third and fourth register group for B bus input. 8 and 9 were established. However, the fifth and sixth registers, which can be used in common across the entire address range,
Even if the configuration does not exist, tx.

Now, when a microinstruction is read from the control storage 2 and stored in the read register 3, the type of the microinstruction is determined.

If this microinstruction is a type of instruction that selects and operates on a register that can be commonly used in the entire address range, the data output from the read register 3 to the signal line 103 causes the register 01 in the fifth register #16 to be ~ One of the OPs is selected by the fO type selector circuit 18 and the human bus 20
1, and similarly, the signal fs103 is sent from the read register 3.
K output data causes one of the registers d+=dq in the sixth register group 17 to be selected by the D-type selector circuit 19.
A is selected and placed on the B bus 202, and the arithmetic logic unit 20
Execute the calculation by The output of the first decoding circuit 4 is transmitted to the fifth and sixth register groups 1 via a signal line 105.
6. Select one register f from 17, and set the contents of the D bus 203 as a result of the operation to the register.

On the other hand, if the type of microinstruction is an instruction that selects and operates on registers that are valid only within the address range divided into m addresses, the output from the read register 3 to the signal line 103 causes the first register group 6 to be read. All registers inside~
one of the registers aml to arn in the second register #7 is selected by the first doll selector circuit 10.
n is selected by the first doll selector circuit 11, and furthermore, by the output of the address register 1 on the signal 1i1104 which is currently addressing the control storage 2f, the A of @1 is sent to the signal l1109.
One of the outputs of the type selector circuits 10 to 11 is
The doll selector circuit 12 selects the person bus 201.
I'll put K on it. Similarly, one of the registers b1□ to b1n in the register group 8 of g3 is selected by the B-type selector circuit 13 by the output of the successive register 3 on the signal @103, and the output from the register #9 of @4 is selected by the B-type selector circuit 13. register bm
1 to bmn is selected by the first B-type selector circuit 14, and the first
A second B-type selector circuit 15 selects one of the outputs of the B-type selector circuits 13 to 14 and outputs the B bus 2.
Put it on 02. Therefore, the calculation is performed by the arithmetic logic unit 20.

One of the first to fourth registers #6 to #9 is selected by the output of the first decoding circuit 4 on the signal line 105 and the output of the second decoding circuit 5 on the signal line 106. , sets the contents of the D bus 203 carrying the calculation result to the register.

In addition to the types of microinstructions described above, registers that are common to the entire address range are specified on the human bus 201, and registers that are valid only within the address range divided into m pieces are specified on the B bus 202. or conversely, a type that specifies registers that are valid only within the address range divided into the A bus 201K and a register that is common to the entire address range for the B path 202. The type may be such that the selection of the register for the data set of the D path 203 can be specified as either a register that covers the entire address range Kll or a register that is valid only within the address range divided into m addresses.

(Effects of the Invention) As explained above, the present invention provides a plurality of register groups corresponding to address ranges, and expands the word length of a microinstruction by selecting a more specific register. This has the effect that it is possible to achieve multi-functionality and high-speed performance without requiring much effort.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram partially showing an embodiment of a microprogram control device according to the present invention. 1...Address register

Claims (1)

[Claims] a control storage for storing a microprogram, an address register for addressing the control storage, a read register for temporarily storing the microprogram read from the control storage, and an output of the read register. a first decoding circuit for decoding a part of the output of the address register; a second decoding circuit for decoding a part of the output of the address register; and an address specified by the output of the second decoding circuit when setting data. a plurality of register groups for storing data output from the first decoding circuit to a specific register having a plurality of registers; a first selector circuit group for selecting the output of a specific register having a designated address; and a group of first selector circuits for selecting one of the outputs of the first selector circuit depending on a portion of the output of the address register. A microprogram control device comprising: a second selector circuit group; and an arithmetic logic means.