JPS61120435A - Inspecting apparatus of semiconductor integrated circuit - Google Patents
Inspecting apparatus of semiconductor integrated circuitInfo
- Publication number
- JPS61120435A JPS61120435A JP24210384A JP24210384A JPS61120435A JP S61120435 A JPS61120435 A JP S61120435A JP 24210384 A JP24210384 A JP 24210384A JP 24210384 A JP24210384 A JP 24210384A JP S61120435 A JPS61120435 A JP S61120435A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- bbg
- substrate
- potential
- ics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路検査装置に係シ、特に、半導
体基板上に作製された、自己基板バイアス発生回路を有
する半導体集積回路装置に探針(以下グローブという)
を接触させ、該装置の電気的特性を測定する場合に用い
られる複数のプローブを持つ半導体集積回路検査装置(
以下プローブカードという)に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit testing device, and is particularly applicable to a semiconductor integrated circuit device fabricated on a semiconductor substrate and having a self-substrate bias generation circuit. Needle (hereinafter referred to as glove)
Semiconductor integrated circuit testing equipment (
(hereinafter referred to as a probe card).
従来、半導体基板4上に作製された集積回路装置(以下
、ICという)3の良・不良を判定するには、第2図(
a) # (b)に示すようにグローブカード2のグロ
ーブ1をIC3の電極(パッド)に接触させ、かつ、基
板半導体を吸着固定している金属チャック5を一定電位
に保って測定を行っていた。この基板半導体の電位は、
ICの特性に大きな影響を及ぼし、特にMOS ICの
場合には、ICを構成する各々のMOS )ランジスタ
のしきい値電圧が基板電位によって大きく変化する。又
、基板電位は従来のICの場合に外部から供給される場
合が多かった。Conventionally, in order to determine whether an integrated circuit device (hereinafter referred to as IC) 3 fabricated on a semiconductor substrate 4 is good or bad, the method shown in FIG.
a) # As shown in (b), the measurement is carried out by bringing the glove 1 of the glove card 2 into contact with the electrode (pad) of the IC 3, and by keeping the metal chuck 5, which holds the substrate semiconductor by suction, at a constant potential. Ta. The potential of this substrate semiconductor is
It has a great influence on the characteristics of an IC, and especially in the case of a MOS IC, the threshold voltage of each MOS transistor constituting the IC changes greatly depending on the substrate potential. Further, in the case of conventional ICs, the substrate potential is often supplied from outside.
しかしながら、近年、自己基板バイアス発生回路(以下
BBGとする。)を内蔵するICが増加するにつれ、従
来の測定方法では、ICの電気的特性の測定を正確に行
うことが困難になってきた。However, in recent years, as the number of ICs incorporating a self-substrate bias generation circuit (hereinafter referred to as BBG) has increased, it has become difficult to accurately measure the electrical characteristics of ICs using conventional measurement methods.
これは、BBGによって作られる基板バイアスは、デバ
イスの電源電圧を利用して発振回路を使って作られてい
る為基板電位は一定の電位とはなっておらず、又ICの
回路はBBGの特性に応じて設計されている為、ウェハ
ー状態で、吸着チャックから一定電位を与えると、IC
のBBGで発生される基板電位と干渉し、正確な特性測
定が困難になる。This is because the substrate bias created by the BBG is created using an oscillation circuit using the power supply voltage of the device, so the substrate potential is not a constant potential, and the IC circuit has characteristics of the BBG. Since it is designed according to
This interferes with the substrate potential generated by the BBG, making accurate characteristic measurements difficult.
この為、吸着チャックに電位を与えずに測定する方法も
あるが、本来BBGはrcチ、ゾ1個にバイアスを与え
る目的で設計されているが、ウェハー状態での測定では
、半導体基板ウェハー全体にバイアスを与えなければい
けない為、工Cチッ761個のBBGではその能力は不
足し、測定が不安定になってしまう。For this reason, there is a method of measuring without applying a potential to the suction chuck, but BBG was originally designed to apply a bias to one rc chip, but when measuring in the wafer state, it is difficult to measure the entire semiconductor substrate wafer. Since it is necessary to apply a bias to the BBG, a BBG of 761 pieces does not have sufficient capacity and the measurement becomes unstable.
本発明は、BBGを持つICのウェハー状態での特性測
定が正確に行なえる装置を提供するものである。The present invention provides an apparatus that can accurately measure the characteristics of an IC having a BBG in a wafer state.
本発明は半導体基板上に作製された自己基板パイ、アス
発生回路を有する複数の集積回路装置の一つに探針を接
触させて該装置の特性を測定する半導体集積回路検査装
置において、前記探針とは別に、前記被測定集積回路装
置に隣接する少なくとも2以上の他の集積回路装置の電
源電極に接触させる探針を備えたことを特徴とする半導
体集積回路検査装置である。The present invention relates to a semiconductor integrated circuit testing apparatus that measures the characteristics of a plurality of integrated circuit devices fabricated on a semiconductor substrate and having self-substrate pie and ass generating circuits by bringing a probe into contact with the device. The semiconductor integrated circuit testing apparatus is characterized in that, in addition to the needle, a probe is provided that contacts the power supply electrodes of at least two other integrated circuit devices adjacent to the integrated circuit device to be measured.
以下、図を用いて本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図(a) 、 (b)において、本発明に係るグロ
ーブオード2は、測定しようとするIC3に接触させる
プローブ1,1.・・・とは別に、該IC3と隣接する
2つ以上の他のIC7の電源d’ウッド接触させるプロ
ーブ6.6を備えたもので、グローブ1をIC3に、ま
たグローブ6をIC7の電極パッドに接触させ、3つ以
上のIC3,7のBBGを動作させ、かつチャ、り5を
電気的にオープンにしておくことによシ、ウニ” 4
全体の基板電位をIC3の電位に近い状態にすることに
よってIC3の電気的特性を正確に測定する。尚、この
時グローブ6によシ、隣接IC7のBBGを動作させな
ければ、IC3のBBGのみでは能力が不足し基板電位
が不安定になってしまう。又BBGは通常電源電圧を与
えるのみで動作するように設計されている為、プローブ
カード2にはプローブ6を2本追加するのみでよい。In FIGS. 1(a) and 1(b), the globe ode 2 according to the present invention has probes 1, 1 . . . . Separately, it is equipped with a probe 6.6 that contacts the power supply d'wood of two or more other ICs adjacent to the IC3, and connects the glove 1 to the IC3 and the glove 6 to the electrode pad of the IC7. By contacting the IC, operating the BBG of three or more ICs 3 and 7, and keeping the circuit 5 electrically open, the
By bringing the entire substrate potential close to the potential of IC3, the electrical characteristics of IC3 are accurately measured. Incidentally, if the globe 6 does not operate the BBG of the adjacent IC 7 at this time, the BBG of the IC 3 alone will not have sufficient capacity and the substrate potential will become unstable. Further, since the BBG is designed to operate by simply applying a power supply voltage, it is only necessary to add two probes 6 to the probe card 2.
本発明は以上説明したように、ウエノ・−上に作製され
たICの特性を測定する時に少なくも3つ以上のICの
BBGを動作させることによりてウェハーの基板電位を
1個のICのBBGの電位に極めて近い状態にすること
ができ、正確な特性測定を行なうことができる効果を有
するものである。As described above, the present invention operates the BBGs of at least three ICs when measuring the characteristics of an IC fabricated on a wafer, thereby adjusting the substrate potential of the wafer to the BBG of one IC. This has the effect of making it possible to bring the potential into a state extremely close to that of , allowing accurate characteristic measurements to be made.
第1図(a) 、 (b)は本発明の実施例を示すもの
であって、(、)は平面図、(b)は断面図、第2図(
a) t (b)は従来例を示すものであって、(a)
は平面図、軸)は断面図である。
l・・・測定しようとするICに接触されるプローブ、
2・・・グローブカード、3・・・測定されるIC,4
・・・半導体ウェハー、5・・・吸着チャック、6・・
・測定しようとするICに隣接するICの電源パッドに
接触されるグローブ、7・・・測定しようとするICに
隣接するC0
第1図
((Z)
第1図1(a) and 1(b) show an embodiment of the present invention, (,) is a plan view, (b) is a sectional view, and FIG.
a) t (b) shows a conventional example, (a)
is a plan view, and axis) is a cross-sectional view. l...Probe that comes into contact with the IC to be measured;
2... Globe card, 3... IC to be measured, 4
...Semiconductor wafer, 5...Adsorption chuck, 6...
・Glove that touches the power supply pad of the IC adjacent to the IC to be measured, 7... C0 adjacent to the IC to be measured ((Z) Figure 1
Claims (1)
回路を有する複数の集積回路装置の一つに探針を接触さ
せて該装置の特性を測定する半導体集積回路検査装置に
おいて、前記探針とは別に、前記被測定集積回路装置に
隣接する少なくとも2以上の他の集積回路装置の電源電
極に接触させる探針を備えたことを特徴とする半導体集
積回路検査装置。(1) In a semiconductor integrated circuit testing device that measures the characteristics of one of a plurality of integrated circuit devices having a self-substrate bias generation circuit fabricated on a semiconductor substrate by bringing a probe into contact with the device, the probe and Separately, a semiconductor integrated circuit testing device comprising a probe that is brought into contact with power supply electrodes of at least two other integrated circuit devices adjacent to the integrated circuit device to be measured.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24210384A JPS61120435A (en) | 1984-11-16 | 1984-11-16 | Inspecting apparatus of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24210384A JPS61120435A (en) | 1984-11-16 | 1984-11-16 | Inspecting apparatus of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61120435A true JPS61120435A (en) | 1986-06-07 |
Family
ID=17084342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24210384A Pending JPS61120435A (en) | 1984-11-16 | 1984-11-16 | Inspecting apparatus of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61120435A (en) |
-
1984
- 1984-11-16 JP JP24210384A patent/JPS61120435A/en active Pending
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