JPH0595045U - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] In a semiconductor device including a test element or a test element chip in the same wafer in which the semiconductor device is manufactured, the pseudo active patterns 108 and 124 and the pseudo polysilicon pattern 109 are formed near the test element. Place a pseudo pattern. [Effect] Since the pattern density of the circuit system section of the semiconductor device and the pattern density of the test element area section are equal, there is no difference in dimensional processing accuracy between the two, and the measurement result of the test element is reflected in the circuit system section to improve reliability. It is possible to provide a high-performance semiconductor device.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to the configuration of a semiconductor device including a test element.

[0002]

[Prior Art]

 In conventional semiconductor devices, in order to inspect manufacturing process abnormalities and circuit characteristics in the same semiconductor device chip, test elements for measuring device characteristics such as transistors and resistance elements, and polysilicon wiring width and A test element for dimensional measurement for locating aluminum wiring width and contact hole diameter is placed.

Alternatively, when the test elements cannot be arranged in the same chip of the semiconductor device, it is general to arrange the test elements as the test element chips in the same silicon wafer.

A conventional semiconductor device will be described below with reference to the drawings. FIG. 3 shows a state in which test elements are arranged in the same chip of a semiconductor device.

As shown in FIG. 3, the semiconductor device 301 includes a pad region 302 for supplying a power supply voltage and an input signal to the semiconductor device 301 and for extracting an electric signal to the outside of the semiconductor device, and a semiconductor device 301. It is composed of a circuit system area section 303 for processing a given signal and a test element area section 304 including test elements for element characteristic measurement and dimension measurement.

Further, FIG. 4 is an enlarged plan view showing the test element region portion 304 shown in FIG. Here, FIG. 4A shows a test element for measuring the characteristics of the MOS transistor.

As shown in FIG. 4A, the test element is composed of a gate electrode 401, a source electrode 402, and a drain electrode 403.

Further, the gate electrode 401 is a measurement pad 407 for applying a potential to the gate electrode 401, the source electrode 402 is a measurement pad 405 for supplying power, and the drain electrode 403 is an output. The measurement pads 406 are connected to each other via contact holes 409.

Furthermore, the measurement pad 408 is for supplying a bulk potential, and applies a potential to the bulk diffusion layer 404.

FIG. 4B is a plan view showing the arrangement of test elements for measuring the diffusion resistance.

The diffusion resistor 412 is connected to a measurement pad 410 for applying a potential to both ends of the diffusion resistor 412 formed in the active region via a contact hole 409.

Further, by applying a potential to both ends of the diffusion resistance 412, a voltage drop occurs due to a current flowing through the diffusion resistance 412, and a measurement pad 411 for measuring the voltage drop is connected through a contact hole 409.

As described above, the test element region is generally composed of the measurement pad and the test element.

However, in the test element region portion, the measurement pad has a size of 50 μm square to 100 μm square for contacting the probe for performing measurement. In addition, since the measurement pads must be brought into contact with a large number of probes in a narrow area, a large number of measurement pads must be arranged at a pitch of 100 μm to 200 μm.

Further, the occupied area of the test element 304 shown in FIG. 3 is about 100 μm ² to 2500 μm ² .

As a result, the area occupied by the test elements is small with respect to the arrangement pitch of the measurement pads, so that the test elements are isolated and exist in a considerably wide space between the measurement pads. That is, the test element area has a very coarse pattern density with respect to the pattern density of the circuit system area.

[0017]

[Problems to be solved by the device]

 In a semiconductor device manufacturing process, an active region for forming a transistor and a wiring portion are formed by an etching technique.

The pattern processing accuracy of this etching technique changes depending on the ease with which the etching solution and the etching gas flow into the processing pattern, and also changes depending on the amount of the substance in the portion removed by etching.

This indicates that the so-called loading effect, which depends on the pattern density of the material to be etched, has a very large effect.

Generally, if the pattern density is rough, the etching solution and the etching gas are likely to flow into the processing pattern, so that the etching rate is increased. On the other hand, if the amount of material removed by etching is large, the etching speed becomes slow.

Therefore, a difference in pattern density between the circuit system area 303 and the test element area 304 shown in FIG. 3 causes a difference in etching rate between the circuit system area 303 and the test element area 304. Occurs.

As a result, the device characteristic inspection result and the dimension inspection result by the test element may not match the actual device characteristic, the wiring width, and the contact hole diameter of the circuit system area 303.

Therefore, in the inspection of the test element, the semiconductor device is determined to be a non-defective product, but the actual device characteristics and pattern dimensions of the circuit system part are different from the measurement result of the test element, and the evaluation by the test element is performed. The problem arises that the reliability of itself becomes poor.

Therefore, an object of the present invention is to solve the above problems and to make the pattern machining accuracy of the test element area part and the circuit system area part the same, and measure the test element area part to measure the circuit system area part. It enables the accurate monitoring of the semiconductor device and provides a more reliable semiconductor device.

[0025]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the semiconductor device of the present invention is a pseudo pattern for making the pattern density of the circuit system area and the test element area the same, that is, pseudo active area, pseudo aluminum wiring, pseudo polysilicon. Place wiring etc. at least near the test element.

[0026]

【Example】

 Embodiments of the present invention will be described below with reference to the drawings. 1 (a) and 1 (b) are plan views showing a test element according to the present invention.

FIG. 1A shows a test element for examining the characteristics of a MOS transistor. The MOS transistor is composed of a gate electrode 101 made of polysilicon, a source electrode 102, and a drain electrode 103.

The gate electrode 101 is a measurement pad 104 for applying a potential to the gate electrode 101, the source electrode 102 is a measurement pad 105 for supplying power, the drain electrode 103 is an output measurement pad 106, Each of them is connected through a contact hole 110.

The measurement pad 107 is for supplying a bulk potential, and is connected to the bulk diffusion region 111 via a contact hole 110.

In the test element of the MOS transistor, the processing accuracy of the polysilicon of the gate electrode 101 and the processing accuracy of the active region greatly affect the characteristics. Therefore, in this MOS transistor test element, the pseudo active pattern 108 as a pseudo pattern and the polysilicon pattern density of the circuit system section are made equal in order to make the pattern density of the active area of the circuit system section equal. Therefore, the pseudo polysilicon pattern 109 as a pseudo pattern is arranged.

Further, FIG. 1B shows a test element for inspecting the diffusion resistance. The diffusion resistor 121 is formed in the active region, and the measurement pad 122 for applying a potential to both ends of the diffusion resistor 121 is connected through the contact hole 110.

Further, a voltage drops due to the current flowing through the diffusion resistance 121, but a measurement pad 123 for measuring the voltage drop is connected through the contact hole 110.

It is the processing accuracy of the active pattern that affects the resistance measurement in the test element of the diffusion resistance 121. Therefore, the pseudo-active pattern 124 is arranged near the diffused resistor 121 as a pseudo pattern for equalizing the pattern densities of the active regions of the circuit system section.

Further, the graph of FIG. 2 shows the polysilicon line width after etching with respect to the mask size.

As shown in the graph of FIG. 3, the polysilicon line width 202 of the conventional test element is thinner than the polysilicon line width 203 of the internal circuit by about 0.2 to 0.3 μm.

However, in the semiconductor device in which the pseudo pattern is arranged according to the present invention, the polysilicon line width 201 of the test element in which the polysilicon line having the line width of 2 μm is arranged at the pitch of 4 μm around the test element is equivalent to the internal circuit. There is no difference with respect to the polysilicon line width 203 of the internal circuit.

[0037]

[Effect of the device]

 As is clear from the above description, in the semiconductor device according to the present invention, the pattern density of the circuit system portion and the pattern density of the test element are equal due to the pseudo pattern, and the difference in dimensional processing accuracy between the two is eliminated. Therefore, dimensional measurement values measured by test elements, device characteristics such as transistor characteristic values, and resistance values accurately reflect the pattern processing accuracy and device characteristic variations in the manufacturing process. The inspection result of the element can be directly reflected in the circuit system section. As a result, a semiconductor device having high reliability can be realized in inspection management of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a plan view showing a test element of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing a pattern dependence of a polysilicon line width according to an embodiment of the present invention.

FIG. 3 is a plan view showing a test element in a conventional semiconductor device.

FIG. 4 is an enlarged plan view showing a test element in a conventional semiconductor device.

[Explanation of symbols]

 101 Gate Electrode 102 Source Electrode 103 Drain Electrodes 108, 124 Pseudo Active Pattern 109 Pseudo Polysilicon Pattern 110 Contact Hole 111 Bulk Diffusion Region 121 Diffusion Resistance

Claims (1)

[Scope of utility model registration request] 1. A semiconductor device including a test element or a test element chip in the same wafer in which the semiconductor device is manufactured, wherein a pseudo pattern is arranged at least in the vicinity of the test element.