TW414995B - Method of detecting semiconductor device - Google Patents

Abstract

A method of detecting a semiconductor device during its manufacturing process is provided for reducing the semiconductor device defect during the manufacturing process. Generally, Pviao (Polysilicon to Another polysilicon) is used to connect a landing-via and a polysilicon for being used as a line of a node. Another polysilicon connects to outside for being used as a bit-line contact end to measure a semiconductor cell device of a random access memory. The quality of the semiconductor cell device can thus be measured and checked to improve the yield of the semiconductor device.

Description

414995 V. Description of Invention (1) '' ~ 5 -1 Field of Invention:

The present invention discloses a method for reducing defects formed in a semiconductor body during a process of manufacturing a semiconductor element. V 5-2 Background of the Invention: In the past ten years or so, since the creation of computers, the demand for ram has been increasing rapidly due to the widespread use of random memory (ram) in various related areas. Especially the information industry applied to computer hardware. At the same time, it is not only used in the information industry. It is also generally used in large integrated circuit (LSI), very large integrated circuit (VLSI), and ultra large integrated circuit (ULSI). Undoubtedly, even in the next century, the process technology of random memory (RAM) still occupies a very important position in the information industry. In the encapsulation process Process of random slaves I, 丨, all processes must be completed ("FuUy", after the magic, as shown in the first Λ and the first B), the test must be performed in the first b Only after the formation of three layers of polycrystalline silicon 15 can semiconductor devices be measured

Device), and based on the measurement and verification of the finished product, further requirements for high yield. The above-mentioned method of the conventional random memory (RAM) semiconductor device has caused certain limitations in the process technology. Therefore, the finished product must be tested after the Fully Process is completed. then,'

414995 V. Description of the invention (2) Not only can't monitor the system's promotion and exchange # + +. .K, in real time; the errors generated during the process can't be eliminated in time to reduce the yield of the product. Even more because of this. In order to improve and improve the system of random memory ㈣),... ', Urgently needed—proposed a new process method and its structure, and improved component quality and manufacturing efficiency. 5-3 Purpose and summary of the invention: In the background of the invention of Γ2, the traditional packaging process of random memory can be disadvantageous. 'The present invention provides a non-destructive detection method, which effectively solves the problems generated in the packaging process in terms of quality. 0' The present invention The method provided is that during the process, that is, ^ P! Half and ° f, it is not necessary to destroy the random memory semiconductor element, that is, the semiconductor element detection is performed step by step, and no additional work is required. ^ According to the purpose of the above, the polycrystalline silicon contact end is used to face another polycrystal) Λ ^ (P0lySiliC0nt〇Anothei · Polysilicon, Pviao / channel core, and polycrystalline%-as a node (Node ) Terminal, and then another polycrystalline silicon (0, y = i, lcon) to connect, as a bit line contact (Bit_Uncontact), as a semiconductor memory device for measuring random memory. And want to keep Structure (Cel 1 Sturct ure) to approximate its true shape 414995 V. Description of the invention (3) (Real Case) 'You can use the / Polycrystalline silicon contact end to another polycrystalline silicon contact end / Polycrystalline silicon Contact / polycrystalline silicon contact to another polycrystalline silicon contact / another polycrystalline silicon contact (

Pivao / Polysilicon / Pviao / Another Polysilicon). The structure is extracted to maintain the cell arrangement (C e 11 A r r a y). In order to make the above description and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are described in detail below with reference to the accompanying drawings. Figure 5-4 is a simple illustration: Figure A is a top view of the random memory part of a completed process in the traditional process; " Figure B is a random memory of a completed process in the traditional process Partial sectional view; w The second A diagram is a top view of a random memory part of an unfinished process in the embodiment of the present invention; and The second B diagram is one of the unfinished process in the embodiment of the present invention A cross-sectional view of a random billion body part. ° Symbols of the main parts in the figure of the present invention: 11, 15, 16, 21, 24 Polycrystalline silicon 12 '22 Silicon nitride

Page 6 414995

13 '102 14 17' 25 23 M06 101 、 105 103 104 Landing channel node contact end bit line contact end polycrystalline silicon contact end to another polycrystalline silicon contact end polycrystalline sand bit line contact end active area 5-5 Detailed description of the invention : Bu The following is a description of the present invention. The description of the present invention will first be made with reference to an exemplary structure. These changes and the advantages of the present invention will be described later. The preferred method of manufacture will be discussed later. Furthermore, although the invention is described in terms of an embodiment, these descriptions do not limit the scope or the scope of the invention. Moreover, although this example; using the random dynamic memory 胄 of the semiconductor π device, it should be clear that the main part may be replaced by a coincidence part ... The description of the test method of the present invention is used. These elements include proof of the practicality and applicability of this example. Present preferred embodiments and present a preferred embodiment. Equivalent changes under this spirit are covered by the patent. And it should be described that even though the present invention is described by way of example, the present invention is not limited. Any other changes or modifications that do not depart from the disclosure of the present invention are included in the application of the present invention. Note (5) A broad definition to explain the scope of the present invention so as to include all these similar structures. 1. Usually, a silicon nitride (S1 N) layer is provided on a polycrystalline silicon layer of a random memory semiconductor device. The role of this silicon nitride layer is to provide the functions of a bit line contact (Bn Line Contact) terminal and a node (Node cntact) contact terminal and a self-aligned accurate contact (Self-Align cntact) terminal. In this example of actual yoke, the drawings of the present invention with reference to the second A 囷 and the second 8 are referred to. In the second figure B, the polysilicon contact terminal is used to connect another polycrystalline silicon contact terminal 2j (Polysilicon t0 Another pOlysiUcon, pvU〇) to the road channel (Landing-Via), as shown in FIG. 2 of the second A And polycrystalline silicon (PolysilicorO terminal, as shown in Fig. 10), as the node (Node) terminal, such as the wiring of 2 2 in the second B, and then another polycrystalline silicon (Polysillcon) connection, as Bit line contact (Bit_Une terminal, such as 25 in Figure 2B), used to measure the semiconductor device (Cell Device) of the random memory, and finally measured with a parameter measuring machine to obtain the allowable Measurement data within the range. In the present invention, if the cell structure (Ceil sturcture) is to be approximated to its real shape (Real Case), and the unfinished semi-finished product is not damaged, the node end can be used to / Polycrystalline silicon contact to another polycrystalline silicon contact / polycrystalline silicon contact / polycrystalline silicon contact to another polycrystalline silicon contact / another polycrystalline silicon contact (Pivao / p〇lysiHc〇n / p 二 ⑽ /

Another P〇lySilicon) to maintain the cell arrangement (

Ce 11 Array). In summary, the process of manufacturing a random-memory semiconductor device during the period of 414995 V. Description of Invention (6) The formation of the test method consists of testing the structure of the conductor element on the body of the conductor in an order less than a specific number. The decision on semiconductors is limited. Test semi-up ° test semi-semiconductor element S area and large structure are formed. In the next random step, a special test structure comparison step is performed and the number of measuring elements is measured. The conductor element and the conductor element structure are semi-main body in quantity and half in memory. First, a predetermined number of semiconductors and a small number of different test semiconductors are used. Defect defect is a method of analyzing the structure of all components and forming the structure of the conductor element. The method also includes the defects in the crystal conductor body. The semiconductor material is processed sequentially. Then on the semi-manufacturing material, at least-a sequential processing step is performed on the main body, and a smaller number of sequential processing steps are used to manufacture the semiconductor element element and test the semiconductor element structure to form a single step in the semiconductor material. The ontology is formed on the subject. Test flaws peep defects. The main body is a wafer with a larger wafer, and the steps of testing the semiconductor device in each part of the semiconductor device circle and testing the semiconductor device and testing the structure of the semiconductor device to determine the defect of the semiconductor device include at least: A polysilicon contact contacts a second polysilicon contact. Follow the wiring that connects the channel and polysilicon $ as the node end. The second polycrystalline silicon is used as a bit, and the `` 4 '' contact is used as a semiconductor device for measuring random memory. According to the above, it is only a preferred embodiment of the present invention. It is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit and scope of the present invention shall be included in the scope of patent application described below.

Claims (1)

414995 VI. Scope of Patent Application 1. A method for reducing defects formed in a semiconductor body during a process of manufacturing a semiconductor element, which includes at least the following steps: A body of a semiconductor material is subjected to a specific number of manufacturing steps to manufacture a A semiconductor device capable of being electrically tested; formed on a body of at least one semiconductor device test structure, wherein the semiconductor device test structure utilizes a limited number of steps for manufacturing a semiconductor device, and the limited number is less than the specific number, and the semiconductor device The test structure is made by a different limited number of steps; and testing the semiconductor element and testing the semiconductor element structure to determine the formation of the flaw on the body of the semiconductor body D 2. As in the method of the first scope of the patent application, the limited number of steps is one Group of sequential steps for manufacturing the complete semiconductor device. 3. The method according to item 1 of the patent application range, wherein the semiconductor device structures tested are all formed on a single body of the semiconductor material. 4. The method according to item 3 of the patent application, wherein the semiconductor device structures tested are formed next to each other on the main body. 5. The method of claim 1, wherein the semiconductor device structure is tested to analyze the formed defects. 6. The method of claim 1 in the scope of patent application, wherein the subject is a Page 10 414995-VI. Scope of patent application One area and multiple quantities of this semiconductor element Yuan: Junction: Poison is formed in the main body, and it also contains 70 steps of two conductors in each part of the crystal pattern.叩 而 富 千 7. — A Method for Manufacturing Random Memory Semiconductors: A Method for Defective Defects in the Memory Semiconductor Body ', ^ 至 ίΚΐ-特 = = At least Conductive Materials, Perform iC :: Piece Test Structure On the semi-conductor Zhao material, at least-perform a different order processing on the royal body that is less than the specific number ^ step 'to use the smaller number of sequential processing steps to manufacture the semiconductor device test structure U The steps are to test the S-type semiconductor device and the defect of the semiconductor device. 'The + conductor element structure determines the 8. I. If order 7 of the scope of the patent application for manufacturing a complete semiconductor element sequence I', a limited number of steps is a unit lead. Measure the basic body of the body, a method of unilateral material, material 7 body, guide half of Fan Guili in the special application, please apply for the form, compared to the structure of 9 Jiu '... Page 11 414995 VI. Scope of Patent Application 11. The method according to item 7 of the scope of patent application, wherein the semiconductor device structure is tested to analyze the formed defects. 1 2. The method of claim 7 in the scope of patent application, wherein the body is a wafer having a plurality of regions and a plurality of the semiconductor elements, and the structure of the test semiconductor element is formed on the body and is further included in the crystal. Steps for testing semiconductor devices in each part. 1 3. The method according to item 7 of the patent application scope, wherein testing the semiconductor element and testing the structure of the semiconductor element to determine flaws of the semiconductor element at least include: contacting the first polycrystalline silicon contact end with the second polycrystalline silicon Contact terminal (Polysilicon to Another Polysi1 icon, Pviao); Wiring connecting the road channel (Landing-Via) and the polysilicon terminal as the node terminal; and the second polycrystalline stone (P 〇) 1 ysi 1 ic ○), as the bit line contact (B it-Line C ntact) terminal, for measuring semiconductor devices (Cell Device) of random memory. Page 12