五、發明說明（1) 發明之領域 本發明提供一種檢視一半曰 (test key)内導電層電性 奴日日片上之一測斌區 試區内兩導電層來測試一主#^丄尤指一種利用檢視一測 橋樑（bridge)現象而導致帝内孓導電層間是否發生 干双I性瑕疵之方法。 背景說明 在半導體製程中，為維j主 生產之半導體元件不斷:行4 $品f f的穩定，須針對所 同時，亦會採用相同的步‘ f j °通常在進行各項製程的 該測試用元件的各項功沪曰=乍一測試用元件，藉由測量 質。 、此^否正常，以有效控制產品品 目前業界係採用一晶片 ^ acceptance test, ΨΑΤ)，接义度 /則試（wafer (peripheryarea)提供福叙兩1 C日日片（d 1 e )之週邊區域 監控半導體晶片之各項缺r 個測試鍵（test key)，用以 割道處，且經由一金屬墊=、鱼f常測試鍵係位於晶片之切 試鍵係用以測試晶片各項=π妾至一外部接腳，而每一測 r, , , , + M之功能，諸如啟始電壓 (threshold voltage, VT)及飽 cur rent， I SAT)等。透過加諸 /；，L sa ura e -^ ^ ^ + &曰& 名—控制偏壓於測試鍵，即可 措由所碩出之電流置值偵測ψ立 、J出產品缺陷。隨著半導體製程 492128 五、發明說明（2) 的日益精密複雜，測試鍵的運用亦日趨廣泛，如何增進其 測試準確度，實為一重要的課題。 半導體產業歷經長期以來的發展，各項製程的製程線 寬亦隨之縮小。當相鄰的兩導電層相夢通而呈現電連接狀 _ 態時稱為「橋樑（bridge)現象」，導致產品產生電性瑕 ， 疵。習知利用測試鍵檢驗橋樑現象的方法，係先利用一由 電子式掃描顯微鏡(scanning electron microscope, SEM)所產生之電子束（e-bearn)射向測試鍵隊之導電層，以 得到一電壓反射圖形。然後藉由檢視比較數組測試鍵内所 得到的圖形中各兩導電層之圖形是否一致，判定其中所得 4 圖形與他組相異之測試鍵内導電層有電性瑕，疵。或者僅以 肉眼或機器判定該某測試鍵内兩導電層之間發生橋樑現 象。然而當該兩導電層之間相導通的部份極為細微時，僅 只憑藉肉眼或機器比較圖形往往會因為無法明確辨識出瑕 疵而誤判為合格，導致產品電性受損，後段各項製程良率 亦同時降低。 發明概述 因此本發明之主要目的在於提供一種檢視一半導體晶 _ 片上之一測試區（t e s t k e y )内兩導電層以判斷主動區域内 _ 兩導電層間是否發生橋樑（b r i d g e )現象而導致電性瑕/疵之 方法，以解決上述習知檢驗方法無法有效判定極細微瑕疵V. Description of the Invention (1) Field of the Invention The present invention provides a method for testing a master by examining one of the two conductive layers in the test zone of the test zone on one of the test layers of the electrical layer in the test key. A method for inspecting and measuring the bridge phenomenon to cause the occurrence of dry double I defects between the conductive layers of the emperor. Background note In the semiconductor process, the semiconductor components produced for the main dimension of J are constantly: the stability of the line 4 $ ff, the same steps must be used for the same time, fj ° the test components usually used in various processes The performance of each component is the first test component, by measuring the quality. 2. Is this normal? In order to effectively control the product, the industry currently adopts a chip ^ acceptance test (ΨAT), and the test (wapher (peripheryarea)) provides two 1 C day films (d 1 e) The peripheral area monitors each of the semiconductor wafers without r test keys, which are used to cut the path, and through a metal pad =, the test key system located on the wafer is used to test the wafers. = π 妾 to an external pin, and each function of r,,,, + M, such as threshold voltage (VT) and full rent (I SAT). By adding / ;, L sa ura e-^ ^ ^ + & said & name-control bias voltage to the test key, you can measure the ψ stand by the current setting value, J product defects. With the semiconductor process 492128 V. Invention Description (2) is becoming more and more sophisticated and the use of test keys is becoming more and more extensive. How to improve its test accuracy is an important issue. After a long period of development in the semiconductor industry, the process line width of each process has also decreased. When the two adjacent conductive layers are in an electrical connection state, they are called a "bridge phenomenon", resulting in electrical defects in the product. The conventional method for testing the bridge phenomenon using test keys is to first use an electron beam (e-bearn) generated by a scanning electron microscope (SEM) to strike the conductive layer of the test key team to obtain a voltage. Reflection graphics. Then, by examining and comparing the patterns of the two conductive layers in the patterns obtained in the test keys of the array, it is judged that the conductive patterns in the test keys in which the obtained 4 patterns are different from other groups have electrical flaws and defects. Or it can be judged only with the naked eye or the machine that a bridge occurs between two conductive layers in a certain test key. However, when the conductive part between the two conductive layers is extremely minute, comparing the graphics only with the naked eye or the machine will often result in a false judgement of failure because the defect cannot be clearly identified, resulting in damage to the electrical properties of the product. It also decreases. SUMMARY OF THE INVENTION Therefore, the main purpose of the present invention is to provide a method for inspecting two conductive layers in a test region (testkey) on a semiconductor chip to determine whether there is a bridge phenomenon between the two conductive layers in the active area. Defective method to solve the above-mentioned conventional inspection methods can not effectively determine the extremely small defects
492128 五、發明說明（3) 的問題。 在本發明的最佳實施例中，一半導體晶片上包含有複 數個主動區域以及該測試區。首先於該測試區内形成一第 一導電層，再於該測試區内形成一介$層，並覆蓋該第一 導電層。接著於該介電層内形成一插塞洞（plug hole)， · 通達至該第一導電層表面，並於該插塞洞内形成一導電插 塞。之後於該測試區内之該導電插塞上方形成一第二導電 層，-以及於該測試區内距該第二導電層一預定距離之該介 電層其他區域表面上形成一第三導電層，並同時於各該主 動，區域内形成與該第二導電層以及該第三導電層間一隔相同 + 距離之一第四導電層以及一第五導電層。最後利用一由一 電子式掃Ί苗鼻頁 4效鏡(scanning electron microscope, SEM)所產生之電子束（e-beam)，檢視該第二導電層以及該 第三導電層是否發生橋樑現象。 由於本發明之檢驗方法係先於該第二導電層下方形成 該以導電插塞與該第二導電層導通之第一導電層，使該第 二導電層與該第三導電層因下方結構不同而具有不同顏色 的電壓反射圖形，因此在利用一由一電子式掃描顯微鏡所 產生之電子束射向該第二導電層以及該第三導電層以得到 _ 一電壓反射圖形後，可藉由檢視所得到的圖形中該第二導 電層以及該第三導電層所屬區域之顏色是否互有差異，判 定該弟二導電層與該弟二導電層之間，以及各該主動區域492128 Fifth, the problem of invention description (3). In a preferred embodiment of the present invention, a semiconductor wafer includes a plurality of active areas and the test area. A first conductive layer is formed in the test area, and then a dielectric layer is formed in the test area and covers the first conductive layer. Then, a plug hole is formed in the dielectric layer, and it reaches the surface of the first conductive layer, and a conductive plug is formed in the plug hole. A second conductive layer is then formed over the conductive plug in the test area, and a third conductive layer is formed on the surface of the other area of the dielectric layer at a predetermined distance from the second conductive layer in the test area. A fourth conductive layer and a fifth conductive layer at the same distance from the second conductive layer and the third conductive layer are formed in each of the active and active regions. Finally, an electron beam (e-beam) generated by an scanning electron microscope (SEM) is used to examine whether the second conductive layer and the third conductive layer have a bridge phenomenon. Because the inspection method of the present invention is to form the first conductive layer that is conductive with the conductive plug and the second conductive layer under the second conductive layer, the second conductive layer and the third conductive layer are different due to the underlying structure. The voltage reflection pattern with different colors, so after an electron beam generated by an electronic scanning microscope is radiated to the second conductive layer and the third conductive layer to obtain a voltage reflection pattern, it can be viewed by Whether the colors of the second conductive layer and the area where the third conductive layer belongs to each other are different from each other in the obtained pattern, determine whether the second conductive layer and the second conductive layer, and each of the active areas
第8頁 492128 五、發明說明（4) 内之該第四導電層與該第五導電層之間是否發生橋樑現 象。所以即使當該第二導電層以及該第三導電層相導通的 部份極為細微時，亦可明確辨識出瑕疵，有效彌補了習知 檢驗方法中以肉眼判定所造成的誤差，因此可以確保產品 電性正常，並提昇後段各項製程良率_。 ‘ 發明之詳細說明 請參考圖一至圖四，圖一至圖四為本發明檢視一半導--------- 體晶片上之一測試區（t e s t k e y )内兩導電層間是否發生橋 樑（bridge)現象而導致電性瑕疵之方法示意圖。如圖一所 φ 示，一半導體晶片30包含有一矽基底32，矽基底3 2又包含 有複數個主動區域以及複數個測試區。圖一中以一主動區 域3 4以及一測試區3 6作說明。 如圖二所示，首先於測試區3 6内之矽基底3 2上形成一 第一導電層3 8，並隨即同時於主動區域3 4以及測試區3 6内 形成一介電層40，覆蓋於主動區域3 4内之矽基底3 2表面以 及測試區3 6内之第一導電層3 8表面。接著如圖三所示，於 測試區3 6内之介電層4 0内形成一插塞洞（ρ 1 u g h ο 1 e )，通 達至第一導電層3 8表面，且於該插塞洞内形成一導電插塞 42。 ❿ 之後如圖四所示，於測試區3 6内之導電插塞4 2上方形Page 8 492128 V. Description of the invention (4) Whether a bridge phenomenon occurs between the fourth conductive layer and the fifth conductive layer. Therefore, even when the conductive portions of the second conductive layer and the third conductive layer are extremely minute, defects can be clearly identified, which effectively makes up for the errors caused by the naked eye in the conventional inspection method, thus ensuring the product. The electrical property is normal, and the yield of each process in the later stage is improved. '' For a detailed description of the invention, please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are views of a half-conductor of the present invention. ) The schematic diagram of the method that causes electrical defects. As shown in Fig. 1, a semiconductor chip 30 includes a silicon substrate 32, and the silicon substrate 32 also includes a plurality of active areas and a plurality of test areas. Figure 1 illustrates an active area 34 and a test area 36. As shown in FIG. 2, a first conductive layer 38 is first formed on the silicon substrate 32 in the test area 36, and then a dielectric layer 40 is formed in the active area 34 and the test area 36 at the same time to cover The surface of the silicon substrate 32 in the active area 34 and the surface of the first conductive layer 38 in the test area 36. Next, as shown in FIG. 3, a plug hole (ρ 1 ugh ο 1 e) is formed in the dielectric layer 40 in the test area 36, and reaches the surface of the first conductive layer 38, and the plug hole is formed in the plug hole. A conductive plug 42 is formed therein. ❿ Then, as shown in Figure 4, the conductive plug 4 2 in the test area 36 is squared.
第9頁 492128 五、發明說明（5) 成一第二導電層4 4，並於測試區3 6内距第二導電層4 4一預 定距離介電層4 0其他區域表面上形成一第三導電層 4 6，同時於各主動區域3 4内，依相同步驟形成一第四導電 層48以及一第五導電層50，且第四導電層48與第五導電層 5 0之間的距離亦為L !。由於測試區3 6巧之第二導電層4 4以 及第三導電層4 6與主動區域3 4内之第四導電層4 8及第五導 電層5 0係利用同一步驟製作而成，因此可以用來檢視各主 動區域3 4内間隔距離同為L A第四導電層4 8及第五導電層 5 0是否發生橋樑現象而相互連接，造成產品電性瑕疵。 最後利用一由一電子式掃描顯微鏡（s c a η n i n g electron microscope, SEM)戶斤產生之電子束（e-beam)射 向第二導電層4 4以及第三導電層46，以得到一電壓反射圖 形。由於第二導電層44下方尚有導電插塞42以及第一導電 層38，故在第二導電層4 4以及第三導電層4 6未有橋樑連接 而導通的情況下，其電壓反射圖形所得的反差顏色應較第 三導電層4 6之電壓反射圖形的顏色淺。相反地，當第二導 電層4 4以及第三導電層4 6相導通而發生橋樑現象時，則兩 者的電壓反射圖形反差會近似或相同。藉由檢視所得到的 圖形中第二導電層4 4以及第三導電層4 6所屬區域之顏色是 否互有差異，即可輕易判定第二導電層4 4以及第三導電層 4 6是否發生橋樑現象，亦即判定各主動區域3 4内之第四導 電層4 8以及第五導電層5 0之間是否發生橋樑現象。Page 9 492128 V. Description of the invention (5) A second conductive layer 4 4 is formed, and a third conductive layer 4 4 is formed a predetermined distance from the second conductive layer 4 4 in the test area 3 6 and a third conductive layer is formed on the surface of the other area. A layer 46 is formed in each active area 34, and a fourth conductive layer 48 and a fifth conductive layer 50 are formed according to the same steps. The distance between the fourth conductive layer 48 and the fifth conductive layer 50 is also L!. Since the second conductive layer 44 and the third conductive layer 46 in the test area 36 and the fourth conductive layer 48 and the fifth conductive layer 50 in the active area 34 are made by the same step, they can It is used to check whether the separation distance within each active area 34 is the same as the fourth conductive layer 48 and the fifth conductive layer 50 of the LA are connected to each other, resulting in electrical defects of the product. Finally, an electron beam (e-beam) generated by a scanning electron microscope (SEM) is used to strike the second conductive layer 44 and the third conductive layer 46 to obtain a voltage reflection pattern. . Since the conductive plug 42 and the first conductive layer 38 are still under the second conductive layer 44, the voltage reflection pattern is obtained when the second conductive layer 44 and the third conductive layer 46 are conductive without a bridge connection. The contrast color should be lighter than the color of the voltage reflection pattern of the third conductive layer 46. Conversely, when the second conductive layer 44 and the third conductive layer 46 are in phase conduction and a bridge phenomenon occurs, the voltage reflection patterns of the two will be approximately the same or the same. By checking whether the colors of the areas where the second conductive layer 44 and the third conductive layer 46 belong to each other in the obtained graph can be easily judged whether a bridge occurs in the second conductive layer 44 and the third conductive layer 46. Phenomenon, that is, determining whether a bridge phenomenon occurs between the fourth conductive layer 48 and the fifth conductive layer 50 in each active region 34.
第10頁 492128 五、發明說明（6) 相較於習知技術，本發明之檢驗方法係先於第二導電 層4 4下方形成以導電插塞4 2與第二導電層4 4導通之第一導 電層38，使第二導電層4 4與第三導電層4 6因下方結構不同 而具有不同顏色的電壓反射圖形，因此在利用一由一電子 式掃描顯微鏡所產生之電子束射向第；導電層44以及第三 * 導電層4 6以得到一電壓反射圖形後，可藉由檢視所得到的 -電壓反射圖形中第二導電層4 4以及第三導電層4 6所屬區域 之顏色是否互有差異，判定第二導電層4 4與第三導電層46 之間，以及各主動區域3 4内之第四導電層4 8與第五導電層 5 0之間是否發生橋樑現象。所以即使當第二導電層4 4以及 第三導電層4 6相導通的部份極為細微時，亦可明確辨識出 φ 瑕疵，有效彌補了習知檢驗方法中以肉眼判定所造成的誤 差，因此可以確保產品電性正常，並提昇後段各項製程良 率。 以上所述僅本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋 範圍。Page 10 492128 V. Description of the invention (6) Compared with the conventional technology, the testing method of the present invention is to form the first conductive layer 4 4 with the conductive plug 4 2 and the second conductive layer 4 4 under conduction. A conductive layer 38 allows the second conductive layer 44 and the third conductive layer 46 to have voltage reflection patterns of different colors due to different structures below. Therefore, an electron beam generated by an electronic scanning microscope is used to strike the first ; After the conductive layer 44 and the third * conductive layer 46 have obtained a voltage reflection pattern, you can check whether the color of the area where the second conductive layer 44 and the third conductive layer 46 belong to the obtained voltage reflection pattern. There are differences between each other, and it is determined whether a bridge phenomenon occurs between the second conductive layer 44 and the third conductive layer 46 and between the fourth conductive layer 48 and the fifth conductive layer 50 in each active region 34. Therefore, even when the conductive portions of the second conductive layer 44 and the third conductive layer 46 are extremely fine, the φ defect can be clearly identified, which effectively makes up for the errors caused by the naked eye in the conventional inspection method. It can ensure that the electrical properties of the product are normal, and improve the yield of various processes in the later stage. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.
492128 圖式簡單說明 圖示之簡單說明 圖一至圖四為本發明檢視測試區内兩導電層間是否發 生橋樑現象而導致電性瑕疵之方法示意圖。 圖示之符號說明 30 半 導 體 晶 片 32 矽 基 底 34 主 動 區 域 36 測 試 區 38 第 一 導 電 層 40 第 一 導電層 42 導 電 插 塞 44 第 二 導電層 46 第 導 電 層 48 第 四 導電層 50 第 五 導 電 層492128 Simple description of the diagrams Simple explanation of the diagrams Figures 1 to 4 are schematic diagrams of the method for inspecting whether a bridge phenomenon occurs between two conductive layers in the test area and causing electrical defects. Symbols shown in the figure 30 Semiconductor wafers 32 Silicon substrate 34 Active area 36 Test area 38 First conductive layer 40 First conductive layer 42 Electrical plug 44 Second conductive layer 46 Fourth conductive layer 48 Fourth conductive layer 50 Fifth conductive layer
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