JPS6127648A - Failure analysis for integrated circuit - Google Patents

Failure analysis for integrated circuit

Info

Publication number
JPS6127648A
JPS6127648A JP14890784A JP14890784A JPS6127648A JP S6127648 A JPS6127648 A JP S6127648A JP 14890784 A JP14890784 A JP 14890784A JP 14890784 A JP14890784 A JP 14890784A JP S6127648 A JPS6127648 A JP S6127648A
Authority
JP
Japan
Prior art keywords
chip
probe electrode
integrated circuit
electric field
ammeter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14890784A
Other languages
Japanese (ja)
Inventor
Takeshi Ando
毅 安東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14890784A priority Critical patent/JPS6127648A/en
Publication of JPS6127648A publication Critical patent/JPS6127648A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To enable to easily detect a leakage current generating place by a method wherein an electric field or a magnetic field is locally impressed on the surface of a chip and a current to flow on the circuit of the integrated circuit is monitored while the probe electrode is made to shift on the surface of the chip. CONSTITUTION:An electric field is locally impressed vertically on the surface of an integrated circuit chip 1 placed on a metallic stage 2 using a probe electrode 5 and this probe electrode 5 is made to shift on the surface of the chip 1. Probes 3 and 4 are erected on the pads of the chip 1 and a power source 7 and an ammeter 8 are connected. A power source 6 is given to the probe electrode 5 and a power electric field in a degree that the field affects the electric conduction of the surface of the chip 1 is set. When the probe electrode 5 comes to a place where a surface inversion leak exists, a change is generated in the ammeter 8. Even when a magnetic field is used instead of an electric field, the similar effect can be obtained.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は集積回路のリーク不良となる故障個所を検出す
る故障解析法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a failure analysis method for detecting a failure location that causes a leak defect in an integrated circuit.

〈従来の技術〉 近年、集積回路は、微細化、高集積化が進んでいる。そ
のためにデバイス構造も複雑化している。
<Background Art> In recent years, integrated circuits have become increasingly finer and more highly integrated. As a result, device structures are becoming more complex.

たとえばアルミニウム配線の多層化や、ポリシリコン配
線の利用がある。特にMOS、LSIにおいてその動向
が著しい。このような従来動向は、必然的にLSIの故
障個所を検出することを困難にしている。従来は故障個
所を検出するために、アルミニウム配線をレーザ光にて
切断し、アルミニウム配線上にプローブ用針を立てて、
電圧または電流を測定しながら故障個所を検出していた
。しかし、この方法は今後は、微細化のための針立ても
困難となシかつ非常に局所化した微少−6リーク個所を
発見することはきわめてむつかしくな如、多大な時間と
手間を要するという欠点を有している。
For example, there are multiple layers of aluminum wiring and use of polysilicon wiring. This trend is particularly noticeable in MOS and LSI. Such conventional trends inevitably make it difficult to detect failure locations in LSIs. Conventionally, in order to detect failure points, aluminum wiring was cut with a laser beam, a probe needle was placed on top of the aluminum wiring, and
Failure locations were detected while measuring voltage or current. However, in the future, this method has the disadvantage that it will be difficult to set up needles for miniaturization, and it will be extremely difficult to find extremely localized micro-6 leak points, requiring a great deal of time and effort. have.

〈発明が解決しようとする問題点〉 本発明の目的は、微細化、高集積化のなされた半導体集
積回路のリーク電流の生じている個所を容易に発見でき
る集積回路の故障解析法を得ることにある。
<Problems to be Solved by the Invention> The purpose of the present invention is to obtain a failure analysis method for integrated circuits that can easily find locations where leakage current is occurring in semiconductor integrated circuits that have been miniaturized and highly integrated. It is in.

〈問題を解決するための手段〉 本発明によれば、半導体チップの表面上に、電界や磁界
を印加すると半導体表面の電気伝導が変化することを利
用して、プローブ電極によシ局所的に電界や磁界を印加
し、このプローブ電極を移動せしめてリーク電流発生個
所を簡単に検出する故障解析法を得る。
<Means for Solving the Problem> According to the present invention, applying an electric field or a magnetic field to the surface of a semiconductor chip changes the electrical conductivity of the semiconductor surface, so that the probe electrode can be locally applied to the surface of the semiconductor chip. We obtain a failure analysis method that applies an electric field or magnetic field and moves this probe electrode to easily detect the location where leakage current occurs.

〈実施例〉 本発明を、第1図を用いて説明する。金属製ステージ2
上に載置された集積回路チップ1のチ。
<Example> The present invention will be explained using FIG. 1. metal stage 2
1 of the integrated circuit chips 1 placed on top.

プ表面に、プローブ電極5を用いて、局所的に電界を垂
直に印加し、このプローブ電極5をチップ10表面上で
移動している。集積回路チップ1のパッドにはプローブ
針3,4が立てられ、これらプローブ針3,4間には、
電源7と電流計8が接続されている。プローブ電極5に
は電源6が与えられておシ、電界を変えるためにこの電
源6は可変となりている。このような構成にて、集積回
路チップ1の表面の電気伝導に影響を与えることができ
る程度の適切な電界を電源6で設定する。次に、プロー
ブ電極の位置を移動しながら電流計8を観察する。表面
反転リークが存在する個所にプローブ電極5が来た場合
、電流計8に変化が生ずる。
An electric field is locally applied perpendicularly to the surface of the chip 10 using a probe electrode 5, and the probe electrode 5 is moved on the surface of the chip 10. Probe needles 3 and 4 are set up on the pads of the integrated circuit chip 1, and between these probe needles 3 and 4,
A power source 7 and an ammeter 8 are connected. A power source 6 is applied to the probe electrode 5, and this power source 6 is variable in order to change the electric field. With such a configuration, an appropriate electric field is set by the power source 6 to the extent that it can influence the electrical conduction on the surface of the integrated circuit chip 1. Next, the ammeter 8 is observed while moving the position of the probe electrode. When the probe electrode 5 comes to a location where surface inversion leak exists, a change occurs in the ammeter 8.

チップ10表面の伝導型の反転を抑制するような電界で
あればリーク電流は小さくなるし、逆に反転を促進する
場合はリーク電流は大きくなる。このチップ1の表面状
態変化の現象を利用することにより、従来微少リーク個
所を検出することが難しかつたことが簡単に行える。
If the electric field suppresses conduction type reversal on the surface of the chip 10, the leakage current will be small; on the other hand, if the electric field promotes the reversal, the leakage current will increase. By utilizing this phenomenon of changes in the surface state of the chip 1, it is possible to easily detect minute leakage points that have been difficult to detect in the past.

故障解析装置としては、プローブ電極5の位置移動と電
流変化とを連動するように構成することによ)、故障位
置検出がよシ効率的となる。電界の代わりに磁界を用い
ても同様の効果を得ることができる。
By configuring the failure analysis device so that the positional movement of the probe electrode 5 and the current change are linked, the failure position detection becomes more efficient. A similar effect can be obtained by using a magnetic field instead of an electric field.

〈発明の効果〉 本発明によれば、簡単にリーク電流の発生個所を検出で
き、集積回路が高密度化、微細化しても故障個所の発見
は容易になされる。
<Effects of the Invention> According to the present invention, the location where a leakage current occurs can be easily detected, and even when integrated circuits become denser and finer, the location of failure can be easily discovered.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による故障解析中の集積回路
チップの断面と故障個所検出用測定回路である。1・・
・・・・集積回路チップ、2・・・・・・金属製ステー
ジ、3,4・・・・・・プローブ針、5・・・・・・プ
ローブ電極、6・・・・・・電界用電源、7・・・・・
・チップ用電源、−・・・・・・電流計。
FIG. 1 shows a cross section of an integrated circuit chip during failure analysis and a measurement circuit for detecting a failure location according to an embodiment of the present invention. 1...
...Integrated circuit chip, 2...Metal stage, 3, 4...Probe needle, 5...Probe electrode, 6...For electric field Power supply, 7...
・Power supply for chip, -...Ammeter.

Claims (1)

【特許請求の範囲】[Claims]  集積回路のチップ表面に局所的に電界または磁界を印
加できかつ位置可変なプローブ電極を前記集積回路のチ
ップ表面を移動しながら、前記集積回路の回路電流をモ
ニターすることにより、該集積回路の故障個所を検出す
ることを特徴とする集積回路の故障解析法。
Failure of the integrated circuit is detected by monitoring the circuit current of the integrated circuit while moving a positionally variable probe electrode capable of locally applying an electric or magnetic field to the chip surface of the integrated circuit. A failure analysis method for integrated circuits characterized by detecting locations.
JP14890784A 1984-07-18 1984-07-18 Failure analysis for integrated circuit Pending JPS6127648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14890784A JPS6127648A (en) 1984-07-18 1984-07-18 Failure analysis for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14890784A JPS6127648A (en) 1984-07-18 1984-07-18 Failure analysis for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6127648A true JPS6127648A (en) 1986-02-07

Family

ID=15463329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14890784A Pending JPS6127648A (en) 1984-07-18 1984-07-18 Failure analysis for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6127648A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04180645A (en) * 1990-11-15 1992-06-26 Nec Yamagata Ltd Device for evaluating electrostatic withstanding voltage of wafer
JP2008193079A (en) * 2007-01-31 2008-08-21 Internatl Business Mach Corp <Ibm> Method and apparatus for implementing ic device test improved in spql, reliability, and yield performance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04180645A (en) * 1990-11-15 1992-06-26 Nec Yamagata Ltd Device for evaluating electrostatic withstanding voltage of wafer
JP2008193079A (en) * 2007-01-31 2008-08-21 Internatl Business Mach Corp <Ibm> Method and apparatus for implementing ic device test improved in spql, reliability, and yield performance

Similar Documents

Publication Publication Date Title
FR2356949A1 (en) INTEGRATED CIRCUIT TEST STRUCTURE
US9157935B2 (en) Apparatus and method for endpoint detection during electronic sample preparation
JP2000357962A5 (en)
JPS6127648A (en) Failure analysis for integrated circuit
US6909296B2 (en) Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting
JPH02224354A (en) Inspection of deviation of contact hole in semiconductor device
JPS6171644A (en) Failure analysation of ic
JPH065674A (en) Semiconductor integrated circuit device
JP2943399B2 (en) Semiconductor integrated circuit
JP2767991B2 (en) Inspection board, circuit board inspection method and circuit board inspection apparatus
JP2006003135A (en) Method for diagnosing failure of semiconductor integrated circuit
JPS61120435A (en) Inspecting apparatus of semiconductor integrated circuit
KR100265841B1 (en) Semiconductor element manufacturing process monitoring method
JPH0555337A (en) Mos transistor
JPH0815361A (en) Inspection method for printed wiring board
JPH0595045U (en) Semiconductor device
JPS61181142A (en) Method of analyzing trouble in integrated circuit
JPS61252641A (en) Inspecting method for semiconductor integrated circuit
JPS6167238A (en) Semiconductor device
JPS62194681A (en) Semiconductor device
JPS59174771A (en) Tester for insulation resistance of circuit board
JPS63122136A (en) Integrated circuit
JPH0485848A (en) Semiconductor integrated circuit device
JPS6257255B2 (en)
JP2000040717A (en) Tab tape and electric-characteristic measuring and testing method thereof