JPS61117251U - - Google Patents
Info
- Publication number
- JPS61117251U JPS61117251U JP57585U JP57585U JPS61117251U JP S61117251 U JPS61117251 U JP S61117251U JP 57585 U JP57585 U JP 57585U JP 57585 U JP57585 U JP 57585U JP S61117251 U JPS61117251 U JP S61117251U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuits
- temperature
- bounce
- switching transistor
- temperature chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の試験装置の一実施例の回路構
成図、第２図は従来の試験装置の回路構成図であ
る。
１……ＩＣ、５……スイツチングトランジスタ
、６……コモン回路、７……小形コネクタ。
FIG. 1 is a circuit configuration diagram of an embodiment of the testing device of the present invention, and FIG. 2 is a circuit diagram of a conventional testing device. 1...IC, 5...Switching transistor, 6...Common circuit, 7...Small connector.
Claims (1)
を行なう装置において、高温槽内に収容した複数
の集積回路の各所定の端子をこの高温槽内に設け
た耐高温特性の良好なガリウムヒ素のＦＥＴのス
イツチングトランジスタに接続し、このスイツチ
ングトランジスタの出力を並列接続して前記高温
槽の壁面を貫通する信号端子数を減したことを特
徴とするバアン・イン法による集積回路の試験装
置。 In an apparatus for high-temperature testing of integrated circuits and the like by the bounce-in method, each predetermined terminal of a plurality of integrated circuits housed in a high-temperature chamber is provided with a gallium arsenide FET with good high-temperature resistance characteristics. 1. A testing device for integrated circuits using a bounce-in method, characterized in that the number of signal terminals passing through the wall of the high temperature chamber is reduced by connecting a switching transistor and connecting the outputs of the switching transistor in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57585U JPS61117251U (en) | 1985-01-07 | 1985-01-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57585U JPS61117251U (en) | 1985-01-07 | 1985-01-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61117251U true JPS61117251U (en) | 1986-07-24 |
Family
ID=30472545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57585U Pending JPS61117251U (en) | 1985-01-07 | 1985-01-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61117251U (en) |
-
1985
- 1985-01-07 JP JP57585U patent/JPS61117251U/ja active Pending
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