JPS648674U - - Google Patents

Info

Publication number
JPS648674U
JPS648674U JP10409487U JP10409487U JPS648674U JP S648674 U JPS648674 U JP S648674U JP 10409487 U JP10409487 U JP 10409487U JP 10409487 U JP10409487 U JP 10409487U JP S648674 U JPS648674 U JP S648674U
Authority
JP
Japan
Prior art keywords
load resistor
semiconductor device
bias current
maximum bias
device testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10409487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10409487U priority Critical patent/JPS648674U/ja
Publication of JPS648674U publication Critical patent/JPS648674U/ja
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本考案の実施例を示すブロツ
ク図、第3図は従来の半導体素子試験装置の試験
回路を示すブロツク図である。 1……コレクタ・ベース間バイアス電源、2…
…被試験半導体素子、3……最大バイアス電流用
負荷抵抗、4……エミツタ・ベース間バイアス電
源、5……負荷抵抗取付用プリント板、6……追
加用負荷抵抗、7……コネクタ。
1 and 2 are block diagrams showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a test circuit of a conventional semiconductor device testing apparatus. 1... Collector-base bias power supply, 2...
... Semiconductor element under test, 3... Load resistor for maximum bias current, 4... Emitter-base bias power supply, 5... Printed board for mounting load resistor, 6... Load resistor for addition, 7... Connector.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 負荷抵抗を用いて半導体素子にバイアス電流を
印加し、該半導体素子の試験を行う半導体素子試
験装置において、最大バイアス電流用負荷抵抗と
、プリント板に実装された追加用負荷抵抗との組
を有し、前記プリント板を装着するコネクタを前
記最大バイアス電流用負荷抵抗に直列に接続した
ことを特徴とする半導体素子試験装置。
A semiconductor device testing device that applies a bias current to a semiconductor device using a load resistor to test the semiconductor device has a set of a maximum bias current load resistor and an additional load resistor mounted on a printed circuit board. A semiconductor device testing apparatus characterized in that a connector for mounting the printed board is connected in series to the maximum bias current load resistor.
JP10409487U 1987-07-07 1987-07-07 Pending JPS648674U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10409487U JPS648674U (en) 1987-07-07 1987-07-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10409487U JPS648674U (en) 1987-07-07 1987-07-07

Publications (1)

Publication Number Publication Date
JPS648674U true JPS648674U (en) 1989-01-18

Family

ID=31335509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10409487U Pending JPS648674U (en) 1987-07-07 1987-07-07

Country Status (1)

Country Link
JP (1) JPS648674U (en)

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