JPS61108234A - Supervisory system of time division multiple access device - Google Patents

Abstract

PURPOSE:To attain fault supervision with on-line and high reliability by inserting a supervisory pattern in a transmission data string and transmitting the result during time slots while no transmission burst is transmitted and extracting the supervisory pattern from the signal string so as to apply supervision. CONSTITUTION:A data signal of plural series is inputted to a synthesis circuit 2 via interface (IF) circuits 1a, 1b...1n. The logical processing is executed in the logical processing circuit 3 during time slots including a transmission data and a carrier signal in time slots other than the said time slots is shut off from a modulator 4. A supervisory pattern generating circuit 5 uses a data gate signal as a clock signal to generate the supervisory pattern, which is inserted to the time slot shut off by the modulator 4. A supervisory pattern detection circuit 6a supervises the synthesis circuit 2 by extracting the supervisory pattern inserted in the synthesis circuit 2 and detecting it. Similarly, a fault of device after the logical processing circuit 3 is detected respectively by a corresponding supervisory pattern detection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault monitoring system for a time division multiple access device used in satellite communications and the like.

[Prior art]

In time division multiple access (TDMA) communications using satellites, transmission signals sent from each earth station to the satellite are made so that they do not overlap in time with burst signals sent by other earth stations on the satellite. There is a need to. Therefore, each earth station transmits the reference burst signal in synchronization with the reference burst signal, thereby establishing a communication line between the plurality of earth stations.

In order to achieve the above synchronization, each earth station transmits a burst signal that includes a synchronization unique word (5TJW), and the timing at which this burst signal is received by the earth station that transmitted the burst signal via the satellite is known. A method of detecting the timing of signal transmission from your own station (so-called closed-loop synchronization)
Alternatively, monitor the timing at which the above burst signal is received by an earth station other than the earth station that sent this burst signal via the satellite, and contact the earth station that sent the burst signal to synchronize the results. Various methods of holding (so-called open-loop synchronization) and so-called burst synchronization are used.

Incidentally, fault monitoring in conventional TDMA devices is performed by checking whether a unique word (StW) included in a burst signal is detected, that is, whether burst synchronization is achieved, or during a continuity test after line setup.

[Problem that the invention seeks to solve]

However, the detection of the unique word requires determining the reception timing of the 'l' DMA device.

It must be extracted from the received data immediately after demodulation. Therefore, only equipment failures from the unique word insertion section to the detection section need to be monitored. This means that the compression/reception processing for transmitting and receiving data in TDMA devices is
Decompression buffer circuit, signal synthesis/distribution circuit, error correction encoding/decoding circuit.

This means that faults in the scrambling/descrambling circuits are not monitored.

In addition, in the continuity test after setting up two lines, especially the prediction assignment'
In I'DMA communication, line settings are not changed very often, so they are not constantly monitored.

Therefore, they are not monitored online.

Furthermore, in a method that uses a dedicated time slot to monitor equipment failures in TDMA equipment via a satellite link, the efficiency of using two lines decreases, especially in communication systems that do not have a closed loop (such as satellite communication using spot beams). There is a problem in that it is not possible to monitor station equipment failures.

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to provide a monitoring method that can perform online fault monitoring of a TDMA device and can perform fault monitoring with high reliability.

Another object of the present invention is to provide a fault monitoring system that can easily distinguish between faults in the transmitting system and faults in the receiving system of a TDMA device.

Still another object of the present invention is to provide a fault monitoring method that does not require a dedicated fault monitoring time slot and is applicable even when the burst time plan in the communication system is changed.

According to the present invention, in a monitoring scheme used in a time division multiple access device comprising a modulator and transmitting a transmission burst during a period in which the modulator is on, a monitoring pattern generation for generating a predetermined monitoring pattern is provided. means for inserting and combining the monitoring pattern into a transmission data stream during a time slot in which the transmission burst is not transmitted; It has an extraction means for extracting a monitoring pattern, and a detection means for detecting the extracted monitoring pattern.

A monitoring method for a time division multiple access device that monitors a fault in the time division multiple access device based on the detected monitoring/o-turn is obtained, and has high reliability and high efficiency.

It is possible to realize a fault monitoring method that is easy to maintain.

In the present invention, the monitoring pattern is inserted into the transmission data string and sent out by using it as a carrier gate signal or data optical tag signal/clock signal in the time slot turned off by the modulator, and the monitoring pattern is sent out by inserting it into the transmission data string. By monitoring this monitoring pattern at the input or output, fault conditions up to the modulator are monitored.

[Embodiments of the invention]

The present invention will be explained below based on examples.

FIG. 1 is a block diagram showing the flow of data signals in a transmission system in a TDMA device.

Multiple series of data signals are sent to the interface circuit (la
, lb...In) to the synthesis circuit 2.

In the synthesis circuit 2, multiple series of data signals input in parallel are rearranged into series.

In the synthesis circuit 2, a data gate (DATAGATE) signal indicating the data period of the data signal is sent to the next stage logic processing circuit 3 together with the data signal. Logic processing circuit 3
Logic processing such as error correction, scrambling, and preamble word insertion is performed.

Incidentally, these logical processes are performed only during time slots that include data to be transmitted. The signal that has been subjected to these logical processes is modulated by the modulator 4, which is the output terminal on the transmitting side of the TDMA device, but in the modulator 4, the carrier signals of time slots other than the time slot containing the data to be transmitted are turned off. Sh.

Therefore, no signal is output from the modulator 4.

Since each processing section of a TDMA device is mostly composed of logic ICs, the failure mode of each processing section is that its output is II O.
It is often a recess fixed at II or '1''.

Therefore, by monitoring the operation of each processing section in a time slot in which the carrier signal is off, it is also possible to monitor the operation of each processing section in a time slot in which the carrier signal is on.

As shown in FIG. 1, the monitoring pattern generation circuit 5
The output of is connected to the synthesis circuit 2.

The monitoring pattern generation circuit 5 generates a predetermined monitoring pattern using the carrier gate signal or the data gate signal as a clock signal, and this monitoring pattern is inserted into the time slot portion where the modulator 4 is turned off.

That is, it is input to the synthesis circuit 2 together with each data signal and synthesized. As shown in the figure, the synthesis circuit 2. A monitoring pattern detection circuit 6a is provided at the output end of the processing section such as the logic processing circuit 3.

6b...6n are connected. A data signal into which the aforementioned monitoring pattern is inserted is input to the monitoring pattern detection circuit 6a connected to the output terminal of the synthesis circuit 2.

The monitoring pattern detection circuit 6a extracts and detects the monitoring pattern inserted by the synthesis circuit 2 from the data signal string. As described above, since the synthesis circuit 2 is constituted by a logic IC, it is possible to monitor failures in the synthesis circuit 2 based on this detection result.

Similarly, a device failure in the logic processing circuit 3 is detected by the monitoring pattern detection circuit 6b. In this way, the modulator 4
Equipment failures in each processing unit up to this point are detected by the corresponding monitoring pattern detection circuit.

Here, determination of a two-device failure will be explained with reference to FIGS. 2 and 3. It is assumed here that three series of data signals are input.

The three series of data signals are input to the combining section 21 of the combining circuit 2 via the interface circuit, and are rearranged into a data signal vl having three transmission bursts in an ITDMA frame, as shown in FIG. 3(,). This data signal vl is then applied to the AND circuit 22. A data signal v2 (FIG. 3(b)) indicating the data period of the data signal shown in FIG. 3(a) is applied to the AND circuit 22. As a result, the AND circuit 22 outputs a data signal v1 similar to that shown in FIG. 3(a).

Further, the data dirt signal v2 is input to the clock terminal 52 of the monitoring pattern generation circuit 5 composed of a D flip-flop circuit 51, and the data dirt signal v2 is frequency-divided by half in the monitoring i9 turn generation circuit 5. Then, a signal v3 (monitoring pattern) shown in FIG. 3(d) is output from the Q terminal. This monitoring pattern v3 is input to the AND circuit 24. On the other hand, the data gate signal V2 is converted by the inverter 23.

A signal V4 shown in FIG. 3(c) is input to the AND circuit 24. As a result, the AND circuit 24 outputs a signal V5 shown in FIG. 3(e). Signals v5 and vl are OR circuit 2
5, and the OR circuit 25 outputs a signal V6 shown in FIG. 3(f). The output from this composite path 2 is monitored as described above. The signal is input to the turn detection circuit 6.

As shown in FIG. 2, the monitoring/main turn detection circuit 6 is composed of an extraction circuit 61 having one D flip-flop 61a, a detection judgment circuit 62 having one D flip-flop 62a, and an adder 62b. The output v6 from the synthesis circuit 2 is input to the D terminal of the extraction circuit 61.

At the same time, the data gate signal v2 is input to the clock terminal C, and the data gate signal v2 is inputted from the Q terminal to the clock terminal i shown in Fig.
9th turn v3 is played. This reproduced monitoring pattern v3 is input to the D terminal of the detection/judgment circuit 62, and at the same time, the data dirt signal V2 is input to the clock terminal C.
The output from the Q terminal is input to the adder 62b together with the monitoring turn V3 as shown in FIG.

When the synthesis circuit 2 is normal (when a normal data signal is output), the monitoring pattern detection circuit 6 shown in FIG.
As is clear from this, the output from this circuit is always "1"
” (however, - level is set to 1). Also, if a failure occurs in the synthesis circuit 2, the logic r
In the failure mode c, the output remains fixed at '0'' or '1'', so the output from the monitoring pattern detection circuit 6 shown in FIG. 2 becomes a pulse-like signal. Therefore.

A failure can be determined by detecting this mother pass.

Note that in the above embodiment, a data gate signal is used as the clock signal, but a carrier gate signal may also be used.

〔Effect of the invention〕

As explained above, according to the monitoring method of the present invention, there is no need to provide a dedicated monitoring time slot, and highly reliable equipment failure monitoring that can be applied to any burst time plan is performed online. be able to. Furthermore, as is clear from the above description, since failure monitoring is performed for each device (processing unit), there is an advantage that failures in the transmitting system and the receiving system can be easily isolated.

Margin below

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a transmission system of a TDMA device to show an embodiment of the present invention, and Fig. 2 shows an example of a synthesis circuit, a monitoring/turn generation circuit, and a monitoring pattern detection circuit used in the invention. Figure 3(a) is a time chart showing the data signal, Figure 3(b) is a time chart showing the data gate signal, and Figure 3(e) is the time chart showing the output from the inverter shown in Figure 2. 3(d) is a time chart showing the output from the monitoring i4 turn generation circuit, FIG. 3(e) is a time chart showing the output from one AND circuit shown in FIG. 2, and FIG. f) is a time chart showing a signal obtained by combining a data signal and a monitoring pattern. 1... Interface circuit, 2... Synthesis circuit, 3
Logic processing circuit, 4 Modulator, 5 Monitoring pattern generation circuit, 6 Monitoring pattern detection circuit.

Claims (1)

[Claims] 1. In a monitoring method used in a time division multiple access device that includes a modulator and sends out a transmission burst during a period in which the modulator is on, a monitoring pattern generating means for generating a predetermined monitoring pattern; synthesis means for inserting and synthesizing a monitoring pattern into a transmission data string during a time slot in which the transmission burst is not transmitted; and extracting the monitoring pattern from a signal string in which the monitoring pattern and the transmission data signal are combined. 1. A monitoring method for a time division multiple access device, comprising an extraction means for detecting the extracted monitoring pattern, and a detection means for detecting the extracted monitoring pattern, and for monitoring a failure in the time division multiple access device based on the detected monitoring pattern.