RU2207730C1 - Procedure of reception, demodulation and processing of signals of satellite and radio relay communication lines - Google Patents

Abstract

FIELD: radio engineering, digital technology. SUBSTANCE: technical result consists in increased efficiency with short-time decrease of signal-to-noise ratio across input of facility below threshold level leading to synchronization malfunction. Salient feature of invention lies in that signal with high signal-to-noise ratios and provision for frame-by-frame synchronization is processed in real time by hardware and in case of synchronization malfunction digital signal after demodulation is recorded on hard magnetic disk of personal computer and is later processed in postreal time by software methods. Hardware information is corrected by processing results. EFFECT: increased efficiency of procedure. 2 dwg

Description

 The method relates to the field of radio engineering and digital technology and can be used in the reception, demodulation, decompression and channel separation of various signals with temporary compression.

 The need to transmit large amounts of information has led to the creation of branched satellite and microwave links with complex digital stream conversions on the transmitting side and various types of modulation: CCITT recommendations G 232, G 733, G 741, G746, G747, G751, G752, G754 and others with phase modulation modes 2FM, 4FM, 4FMS, 8FM, KAM16, KAM32, etc. [1, 2].

For each signal (communication system), as a rule, its own special equipment for receiving, demodulating, and processing is developed according to a generalized method, in which:
- the signal is received and converted into an intermediate frequency;
- the signal is demodulated - converted into a digital stream;
- synchronization signals are selected from the digital stream on the frequency interval of the digital stream;
- count the number of clock pulses from the moment the sync signal is allocated;
- according to the calculation results, strobes are formed for each component of the digital stream (service bits, information stream bits, stuffing control commands, stuffing bits);
- emit clock pulses of each of the components of the digital stream;
- clock signals of the selected components select information from the total digital stream.

 The disadvantage of this method is its determinism for each type of compaction and the complexity of the hardware implementation.

 According to this method, domestic equipment for the IKM-30, IKM-120, IKM-480, IKM-1920 signals, as well as foreign equipment, was built.

 In [3], a method was proposed that ensures the adaptation of equipment to various types of compaction.

According to this method, as in the analogue:
- the signal is received and converted into an intermediate frequency;
- the signal is demodulated - converted into a digital stream, accompanied by clock pulses;
- synchronization signals are selected from the digital stream on the frequency interval of the digital stream (frame, super-frame or super-frame synchronization signals);
- synthesize a model of a digital stream (signal);
- enter the signal model into RAM;
- the signal model is synchronously with the digital stream read the signal model from the random access memory (RAM);
- generate clock signals of the corresponding parts of the digital stream;
- selected clock signals select the information parts of the components of the digital stream.

 The disadvantage of this method is its low efficiency when for some reason the signal-to-noise ratio at the input of the device decreases below a threshold level, which usually leads to a breakdown of the synchronization system and loss of information.

 The aim of the invention is to increase efficiency with a short-term decrease in the signal-to-noise ratio at the input of the device below the threshold level, leading to synchronization failures.

 To achieve this goal, a method is proposed in which a signal is received (converted to an intermediate frequency), demodulated (converted to a digital stream), synchronization signals are selected from the digital stream on the frequency interval of the digital stream (frame, superframe and superframe synchronization signals), a digital model is synthesized flow (signal), enter the signal model into RAM and the signal synchronously with the digital stream read the signal model from the memory and generate clock signals with leaving parts of the digital signal, which select the information parts of the components of the digital stream.

 According to the invention, the presence of synchronization is constantly monitored (by frames, superframes, superframes), and if synchronization is disturbed, the signal after demodulation is recorded on the hard magnetic disk of a computer. Then, according to the optimal algorithms, program methods in post-real time process the signal (determine the clock signals and, with reference to them, demultiplex the digital stream stored in the memory). According to the processing results, the information received by the hardware is corrected, which avoids the loss of information due to synchronization failures caused by noise or a decrease in the signal-to-noise ratio for some reason, i.e. the received signals are processed in post-real time, which allows the use of optimal synchronization, decoding and demultiplexing algorithms, which, although they take longer than the real-time operation of the equipment, allow them to process signals with a small signal to noise ratio (a large number of errors) .

The solution to the problem of processing signals with small signal-to-noise ratios (a large number of errors in the digital stream P _osh ≥2 • 10 ^-2 ) by circuit-technical methods leads to a significant complication of all devices. In particular, in [1, p. 101] provides a schematic technical solution for an adaptive clock receiver, which is much more complicated than a non-adaptive receiver circuit. A similar picture can be seen in other adaptive devices of the reception path, demodulation, and processing of digital streams.

 A similar solution is not described in the literature, therefore, the method meets the criteria of novelty and inventive step.

 In FIG. 1 shows a structural block diagram of a device according to the proposed method.

 Figure 2 shows the structural diagram of a device for high-speed input.

The proposed method performs the following sequence of operations:
- the signal is received (converted to an intermediate frequency);
- the signal is demodulated (the signal is converted into a digital stream accompanied by a clock frequency);
- synchronization signals are selected from the digital stream on the frequency interval of the digital stream (frame, super-frame or super-frame synchronization signals);
- synthesize a model of the processed signal;
- enter the signal model into RAM;
- a signal model is read from the RAM in synchronization with the digital stream;
- generate clock signals of the constituent parts of the digital stream;
- selected clock signals select the information parts of the components of the digital stream;
- constantly monitor the presence of frame, superframe and superframe synchronization;
- in the event of a synchronization violation (due to an increase in the number of errors in the digital signal), the signal after demodulation is converted into a parallel code and recorded on a PC hard disk;
- according to well-known algorithms, using a PC, a detailed processing of the recorded digital stream in a post-real-time time scale is performed and information of the constituent parts of the input total digital stream is extracted;
- according to the processing results, the hardware information is corrected.

 The structure of the device that implements the proposed method (Fig. 1) includes serially connected radio receiver 1, demodulating device 2, clock selector 3, RAM with write and read circuits 4, clock regenerator 5, information regenerator 6, and a PC model of signal 7 and delay units 8, 9. In this case, the outputs of demodulator 2 are connected to the inputs of the high-speed input device 10 introduced into the PC 7, the output of the synchronizer 3, which signals a synchronization failure, is connected to the input of the PC 7, the inputs of the delay units 8 and 9 are connected to the clock and information outputs of the demodulator 2, the outputs of the delay elements 8 and 9 are connected to the corresponding inputs of the regenerators 5 and 6.

 The input of the device is the input RPU1, and the outputs are the outputs of the regenerator 6, and if synchronization fails, the outputs of the PC 7.

 The device operates as follows.

 The input signal at a high frequency (for example, in the range of 500-2000 MHz) is fed to the input of RPU 1, where the signal is filtered and converted into an intermediate frequency (for example, 70 MHz). Next, the signal is demodulated (converted into digital form) in demodulator 2. The signals after demodulation, accompanied by a clock frequency, are fed to the input of the clock selector 3. The allocated clock starts reading RAM 4, into which the signal model synthesized in PC 7 is pre-recorded. Next, the clock signals component flows are regenerated in the regenerator 5 with delay compensation by element 8 and with these signals the information coming from demodulator 2 with delay compensation by element 9 is gated. As a result, Exit regenerator 6 formed information flow components of the total digital stream (overhead bits, stuffing bits commands stuffing bits, the signaling bits, united component flows, etc.).

 In the event of a failure for any synchronization reasons, block 3 issues a command to the PC 7 and allows recording the digital stream after demodulator 2 to the PC hard disk magnetic 7.

 When synchronization is restored, the hardware of the device begins to work, and the signal recorded in the PC 7 is processed in real time by software methods. According to the results of signal processing using a PC 7 adjust the output information of the device.

 The HDD memory capacity of modern PCs reaches ~ 40 GB. The information speed after demodulator 2 is a maximum of 150 Mbit / s, which, taking into account the 3-bit soft solution (for decoding according to the Viterbi procedure with a soft solution), will be ~ 450 Mbit / s or ~ 56 MB / s.

 With a memory capacity of 40 GB, the signal recording time will be 40,000 GB: 56 MB = 700 s ~ 11 min.

 To ensure the recording of high-speed digital streams from the demodulator 2 to the PC 7, the PC includes a high-speed input device (air-blast) 10 made on a board inserted into one of the ports of the PC 7 (figure 2).

 The air-blast unit includes a serial-connected converter in parallel code 11, a PCI bridge 12, a RAID controller 13 and HDD 14, while the PCI bridge 12 and the RAID controller 13 are connected to the PC PCI bus 7.

 Air-blast works as follows.

The digital stream from demodulator 2 in the form of a single-bit hard solution or a 3-bit soft solution is fed to the converter in parallel code, where it is converted to a 16- or 32-bit code. Next, the parallel code through the PCI bridge 12, the PCI bus and the RAID controller 13 arrays is entered into the memory of the HDD 14 to establish synchronization. After the synchronization is established, the PC 7 enters the processing mode of the recorded signal, extracting it from the HDD 14 through the controller of the RAID arrays 13. Based on the processing results, the hardware information is adjusted. As a result of using the method, the following effect was obtained:
- provides recording of digital signals in case of failure of synchronization;
- provides the processing and selection of information by machine methods of recorded digital streams and the restoration of information in the intervals where the hardware does not provide signal processing.

 At present, a mock-up of a high-speed input device has been made, its tests have been carried out, and work has also been done on software processing of digital streams in real-time. The results are positive.

Sources of information
1. L.S. Levin, M.A. Plotkin. Digital information transfer systems. - M.: Radio and Communications, 1996.

 2. V.L. Banquet, V.M. Dorofeev. Digital methods in satellite communications. - M.: Radio and communications, 1998.

 3. Patent 2122291 of November 20, 1998.

Claims (1)

 A method of receiving, demodulating and processing signals of satellite and microwave links, in which a signal is received, converted to an intermediate frequency, demodulated, converted to a digital stream, frame, superframe, superframe synchronization signals are selected from the digital stream on the frequency interval of the digital stream, a digital model is synthesized stream, enter the model of the digital stream into RAM, by the synchronization signal synchronously with the digital stream read a pre-recorded model of the digital stream h of random access memory, form the clock signals of the components of the digital stream, selected clock signals select the information parts of the components of the digital stream, characterized in that they constantly monitor the presence of frame, superframe and superframe synchronization and in case of synchronization failure, the signal after demodulation is converted to parallel code and recorded to the hard magnetic disk of a personal electronic computer, after which the recorded digital stream is processed ayut program methods to postrealnom time and secrete components of the input information of the total digital stream.

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