JPS60216644A - Supervisory equipment of time division multiple access equipment - Google Patents

Abstract

PURPOSE:To attain the surpervision for a faulty state of each circuit in a signal path by inserting a surpervisory pattern signal in synchronizing with an output preamble signal of a demodulator of a receiver of a time division connecting equipment to a reception data signal and providing a supervisory pattern discriminating means to each part of the signal path. CONSTITUTION:A supervisory pattern generator 18 is provided between a demodulator 12 of a time division multiple access (TDMA) equipment and a unique word detecting circuit 13. Moreover, supervisory pattern detectors 19-1-19-3 are provided with an output of the unique word detection circuit 13, a logical processing circuit 14 and a distribution circuit 15. Furthermore, a supervisory patter detector 19-4 is provided to an output of interface circuits 16-1-16-3. Thus, whether or not a fault exists in the receiver and which device in the receiver is at fault are recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a fault monitoring device for a time division multiple access device used in satellite communications and the like.

[Description of prior art]

In time division multiple access Vt (hereinafter referred to as rTDMAJ) communication, each earth station accessing the satellite sets standards for its own transmission signal so that the bursts transmitted by other stations do not overlap in time with each other on the satellite repeater. Communication lines between multiple stations are set up by transmitting in synchronization with bursts.

For this purpose, burst synchronization must be performed.

Conventional fault monitoring for TDMA equipment is performed by checking whether a synchronization unique word used for burst synchronization is detected, that is, whether burst synchronization is achieved, or by conducting a continuity test after line setup. ing.

However, since the synchronization unique word is detected to determine the reception timing of the TDMA device, it must be extracted from the received data immediately after demodulation. therefore,
In a fault monitoring device for TDMA equipment using burst synchronization,
Only equipment failures are monitored from the synchronization unique word insertion section to the detection section, and the TDMA device processes the transmitted and received data, including the compression/expansion bassophon circuit, signal synthesis/distribution circuit, error correction coding/decoding circuit, and scrambling circuit. Failures such as descrambling circuits were not monitored.

In addition, TDMA to which preliminary time slots are assigned
In communications, line settings are not changed very often during continuity tests after line settings, so they are not constantly monitored. In other words, it is not monitored online.

Furthermore, using a dedicated time slot to monitor temperature and equipment failures via a satellite link reduces line utilization efficiency.

(Objects of the Invention) The first object of the present invention is to provide a TDMA device that has high reliability and performs % failure monitoring online.

A second object of the present invention is to provide a fault monitoring device that can easily determine whether the fault is in the transmitting system or the receiving system when a fault occurs in a TDMA device.

Third, it is an object of the present invention to provide a fault monitoring device that does not require a dedicated monitoring time slot and can be applied even when the burst time plan of a communication system is changed.

[Features of the invention]

A monitoring pattern generated using a preamble word gate signal as a clock is inserted into the time slot of a used preamble word in the demodulator or unique word detection circuit of the receiving device.1. By monitoring this pattern at the input or output point of each logic processing circuit, it is possible to monitor the failure state of each logic processing circuit in the receiving system from the demodulator or unique word detection circuit to the interface circuit. .

That is, the present invention includes a demodulator that demodulates a received input signal;
A unique word detection circuit that detects a unique word from the output of this demodulator, a logic processing circuit that processes received data from the output of this unique word detection circuit, and the output of this logic processing circuit is distributed to each channel for the own station. In a receiving device of a time division multiple access device, which is equipped with a distributor that outputs a signal from the receiver and an interface circuit that connects the output of the distributor to a terrestrial line, a monitoring pattern signal is generated in synchronization with a preamble signal of the output of the demodulator. and a monitoring pattern signal generation circuit including means for inserting the monitoring pattern signal into the received data signal; The present invention is characterized by comprising a monitoring pattern detection circuit including means for extracting the monitoring pattern signal from the signal sequence and determining the monitoring pattern.

[Explanation based on examples]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The received intermediate frequency signal input terminal 11 is connected to a demodulator 12, and the demodulator 12 is connected to a unique word detection circuit 13,
A plurality of logic processing circuits 14 and a distribution circuit 15 are connected in series, and a plurality of interface circuits 16-1 to 16-1 are connected in series.
6-3 are connected in parallel to the output of the distributor 15, and data output terminals 17-1 to 17-3 are connected to the respective interface circuits 16-1 to 16-3.

Here, in the circuit that characterizes the present invention, a monitoring pattern generation circuit 18 is connected between the demodulator 12 and the unique word detection circuit 13, and the monitoring pattern detection circuits 19-1 to 1
9-4 is branched from and connected to the output of the unique word detection circuit 13, the output of the logic processing circuit 14, the distribution circuit 15, and the respective outputs of the ink-face circuits 16-1 to 16-3.

The demodulator 12, which demodulates the received intermediate frequency signal and reproduces the received data signal, usually extracts the carrier and clock signal reproduction code provided at the beginning of the received burst signal, and uses this to reproduce the data signal. It regenerates the carrier signal and clock signal necessary for

Further, the output data signal from the demodulator 12 is sent to the next stage unique word detection circuit 13, where a unique word is extracted from the received data string in order to synchronize the 1'DMA communication.

In general, after the carrier and clock signal reproduction codes are extracted by the demodulator 12, they are not used in logic processing circuits in subsequent stages. Similarly, the unique word code is not used in subsequent stages after a unique word is detected. The logic processing circuits in the next and subsequent stages perform logic processing such as descrambling, error correction, distribution into multiple series of data signals, and their interfaces, which are necessary for TDMA communication, but none of these processes are performed during actual reception. It is effectively performed only during the time slots of necessary information data, and not during the time slots of preamble words such as carriers, clock recovery signals, and unique word codes.

Since most of each logic processing circuit is made of logic integrated circuits, the failure mode is often that the output remains fixed at "0" or rlJ.

Therefore, by monitoring the monitoring pattern inserted into the time slot of the preamble word, the operation of each logic processing circuit can be monitored.

The monitoring pattern generation circuit 18 is driven by a preamble gate signal, and this signal can be easily obtained, for example, from the detection output of the envelope of the intermediate frequency signal used when reproducing the carrier and clock components.

The output of the monitoring pattern generation circuit 18 is inserted into the carrier and clock recovery code time slot portions of the received data string and synthesized by the unique word detection circuit 13. The output of the unique word detection circuit 13 is branched and input to the monitoring pattern detection circuit 19-1. The monitoring pattern detection circuit 19-1 detects the previously inserted monitoring pattern from the data signal sequence using the preamble gate signal transmitted at the same time, and uses this result to detect equipment failure in the unique word detection circuit 13. can be monitored. One output of the unique word detection circuit 13 is input to the logic processing circuit 14 at the next stage, subjected to logic processing, and then outputted to the next stage, and also branched to the monitoring pattern detection circuit 19-2 for manual input. A monitoring pattern is detected there and used for equipment failure monitoring of the logic processing circuit 14.

Similarly, the distribution circuit 15 to which the received data signal is distributed
an interface circuit 1 that connects the output of , and the data signal obtained by distributing this output into multiple series to the ground-side terminal equipment;
A monitoring pattern detection circuit 19 is connected to the outputs of 6-1 to 16-3.
-3.19-4 enables monitoring of failures in each circuit. Each operation of the receiving device of the DMA device is performed by monitoring pattern detection circuits 19-1 to 19-1.
By distributing 4, it is possible to monitor the failure.

FIG. 2 is a time chart of data signals.

When the preamble gate signal 22 indicating the preamble portion 26 of the received data signal 21 from the demodulator 12 is divided into 1/2 by the monitoring pattern generation circuit 18, the waveform is as shown in the signal 23 in FIG. Become. Using this as a monitoring pattern, the unique word detection circuit 13
- When combining the signal 22 with the received data string 21, the unique word detection circuit 13 outputs 24 waveforms. When this combined output is sampled in each of the monitoring pattern detection circuits 19-1 to 19-4 using the preamble gate signal 22, the monitoring pattern 23 is reproduced.

FIG. 3 is a block diagram of the monitoring pattern generation circuit 18. FIG. 3(A) shows a D-type flip-flop circuit 32.
FIG. 3B is a block diagram of a circuit for inserting and synthesizing monitoring patterns. The output of an insertion/synthesis circuit 35 that inserts the monitoring pattern generated by the monitoring pattern generator 31 and alternately synthesizes it with the manual data from the received data string input terminal 36 is sent to the combined data string output terminal 37.

FIG. 4 is a block diagram of the monitoring pattern detection circuit. This example is comprised of a D-type flip-flop circuit 32, an extraction circuit 42 for extracting a monitoring pattern, and a detection judgment circuit 42 for detecting and judging the extracted monitoring pattern. In a normal state, the output of the monitoring pattern detection circuit is always "1". However, the output of the monitoring circuit for monitoring the output of the faulty logic section becomes a pulse.

By detecting this pulse, it is determined whether or not there is a failure.

As described above, according to the present invention, reliable fault monitoring can be performed online that can be applied to any burst time plan without providing a dedicated monitoring time slot.

Furthermore, if a failure occurs and the device of the present invention determines that there is no abnormality in the receiving device, it can be determined that the cause of the failure is in the transmitting device. can be easily identified.

Although the monitoring pattern in Fig. 3 is the rl 010J pattern, the same effect can be obtained by comparing a PN pattern generated using the data gate signal or carrier gate signal as a clock, or a complicated fixed pattern. It will be done.

In addition, in FIG. 1, as a preamble gate signal,
Although the envelope detection signal from the demodulator is used, a unique word detection pulse may be used instead of this signal. In that case, the logic processing circuits that can be monitored are those after the unique word detection circuit.

〔Effect of the invention〕

By distributing the monitoring pattern detection circuit, highly reliable fault monitoring that can be applied to any burst time plan can be performed online without the need for dedicated monitoring time slots. You can easily identify whether it is a system or a receiving system.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a receiving device of a TDMA device, not showing one embodiment of the present invention. FIG. 2 is a time chart of data signals. FIG. 3A is a block configuration diagram showing an example of a monitoring pattern generation circuit, and FIG. 3B is a configuration diagram showing an example of a monitoring pattern signal insertion and synthesis circuit. FIG. 4 is a block diagram showing an example of a monitoring pattern signal extraction and detection determination circuit. 11... Reception intermediate frequency signal input terminal, 12... Demodulator, 13... Unique word detection circuit, 14... Logic processing circuit, 15... Distribution circuit, 16-1 to 16-3
...Interface circuit, 17-1 to 17-3...
Data signal output terminal, 1B... Monitoring pattern generation circuit, 19-1 to 19-4... Monitoring pattern detection circuit, 2
1... Received data signal, 22... Preamble gate signal, 23... 1/2 frequency division monitoring pattern, 24...
・Unique word detection circuit output, 25...'rD M
A frame, 26... Preamble, 27... Data, 28... Reception burst, 31... Monitoring pattern generator, 32... D-type flip-flop circuit, 33
... PW GATE, 34... Monitoring pattern output terminal, 35... Insertion synthesis circuit, 36... Reception data string input terminal, 37... Synthesis data string output terminal, 41.
...Extraction circuit, 42...Detection judgment circuit, 43...Reception data string input terminal, 44...Judgment result output terminal. Patent applicant: NEC Corporation. Agent: Patent attorney Takashi Ide. Foil 2 Figure (A) (B) Cloth 3 Figure

Claims (1)

[Claims] +11 A demodulator that demodulates a received input signal, a unique word detection circuit that detects a unique word from the output of this demodulator, and a logic processing circuit that processes received data from the output of this unique word detection circuit. and a time division multiple access device equipped with a distributor that distributes the output of this logic processing circuit for each channel for its own station, and an interface circuit that connects the output of this distributor to a terrestrial line. In the apparatus, a monitoring pattern signal generation circuit including means for generating a monitoring pattern signal in synchronization with a preamble signal output from the demodulator and inserting the monitoring pattern signal into the received data signal; and a monitoring pattern detection circuit connected to a path through which a signal train in which the received data signals are synthesized passes, and includes means for extracting the monitoring pattern signal from the signal train and determining the monitoring pattern. A monitoring device for a time division multiple access device.