JPS61107831A - Signal processor - Google Patents

Abstract

PURPOSE:To minimize the effect of a data error by transmitting a special code when a sampling digital value goes to the special value at modulation and decoding the specific code into a level signal corresponding to the specific value at demodulation. CONSTITUTION:An analog signal A(t) is subject to A/D conversion 1, converted into a digital signal Ai, which is differentiated to form a difference DELTAAi with a level of the preceding step, a space factor sigma is obtained at a peak-hold circuit 4, a compression difference data DELTAAi/sigma of the suppression DPCM system is obtained by a divider 7 and fed to a mix circuit 16. When it is detected that the Ai/sigma passes through the specific value, it is converted forcibly to the specific value at an inhibition circuit 8. On the other hand, a delay 12 and a level detector 13 detect three special values including zero level, then a switch 15 shuts a signal from the circuit 8 to give the three kinds of specific codes corresponding to the specific level of the sampling value Ai from a level code generator 14 via the circuit 16. When the specific signal is detected at the reception side, the code is demodulated forcibly to the special value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a signal processing device, and particularly to a signal processing device such as a PCM system that transmits, receives, records and reproduces digital values corresponding to changes in signal level.

[Prior Art] In recent years, with the development of digital technology, the DPCM system has been widely adopted for transmitting, recording and reproducing audio or video signals. As is well known, in the DPCM method, a signal to be processed is A/D converted, and only the difference (or compressed value of the difference) at each sampling point is transmitted or recorded or reproduced.

FIG. 1 shows the principle of the DPCM method, where the signal waveform to be processed is shown as A (t) as a function of time. This analog signal A (t) is converted into A/
When D-converted, the step-like waveform shown in the figure is obtained. (Here, for simplicity, the sampling interval is shown very roughly.) In the DPCM method, the difference ΔAi between the sampled digital value Ai at sampling point i and the immediately preceding sampling digital value Ai-1. sequentially transmitted or recorded. The transmitted or recorded data ΔAt is integrated on the demodulation side to restore the digital level signal Ai, which is further D/A converted to reproduce the original signal.

In addition, in order to further increase efficiency, a so-called suppressed DPCM method is also used, in which the difference ΔAt is divided by a scale factor σ corresponding to the peak value of ΔAi over a fixed time width, and a value ΔAi/σ is transmitted or recorded. .

In any case, in the DPCM system, only the difference ΔAt is actually transmitted or recorded, so if a -H data error occurs during the transmission, recording and reproduction process, its effect remains and the subsequent reproduction signal is biased up. (or down) and there is a risk that a level shift will occur. This level shift causes the reproduced signal to enter the non-linear region of the downstream amplifier on the reproduction side, causing distortion, or in extreme cases, leaving the operating region and causing the sound to disappear, making it impossible to restore the normal original signal. It could have been possible.

[Purpose] The present invention has been made in view of the above-mentioned problems, and even if an error occurs due to a data error, the influence of the error can be minimized, and the present invention can provide a signal that can be transmitted or recorded and reproduced with high reliability. The purpose is to provide processing equipment.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings. However, in the following, a case where the signal to be processed is an audio signal will be explained.

In the present invention, when the sampling digital value At in the DPCM modulation process reaches a specific value, a special code is transmitted, and on the demodulation side, this special code is not treated as a difference signal but is instead treated as a signal corresponding to the previous specific value. Configure to pull the signal back to level. With such a configuration, even if a level shift occurs due to a data error, each time the sample value passes a specific value, the demodulation side will always pull back the reproduced signal to the level value corresponding to that specific value, which eliminates the problem of conventional technology. It is possible to prevent extreme signal deterioration as described in .

Although the specific level value of Ai for performing the above control can be determined arbitrarily, the level value will be assumed to be O for the sake of simplicity. The signal A (t
), in analog terms this signal A (t) is point A,
It passes through the zero point at six points B, C, D, E, and F. However, the sampling value Ai does not necessarily become 0 at these zero-crossing points. For example, in the conversion shown in Figure 1, the sampling value Ai becomes 0 at point B.
However, at other points A and C-F, the sampling value Ai is not O due to the difference between the sampling period and the zero cross of A (t).

Let's consider how often such chances occur. Let's assume that the audio signal is a sine wave of approximately 1 KHz and 2
Assume that sampling is performed at a sampling frequency of 0 KHz, and that the sampling level value is quantized in 4096 steps so as to be represented by a 12-bit code. This situation is shown in FIG. 2(A). When the vicinity of the sampling point i in this figure is enlarged, it becomes as shown in FIG. 2(B).

Considering an IKHz sine wave, Sinθ=Δθ (Δθ is minute), so the range in which the sine wave zero-crosses is a range of width T centered on the sampling point i. Therefore, the probability that the sampling value At is O is 20/4096
= 17200.

In other words, in this case, the average room is 10 times per second.
Ai=0 occurs at the interval.

In other words, although it does not correspond to the actual number of zero-crossings of the analog signal, a point where the sampling level value Ai=O always occurs with a certain probability.

Now, set the sampling level value Ai to a specific value (0 in the above example).
) may be determined as follows, for example.

In the DPCM method, the difference value Δ is determined by the sign of a predetermined number of bits.
Since Ai is expressed, the sampled difference value Δ is adjusted by adjusting the level and limiting the frequency band before A/D conversion.
Ai is prevented from exceeding a predetermined bit. Therefore, if this limited range is expanded very slightly so that bits slightly smaller than full bits are output through sampling and quantization, values larger than that can be used as special codes.

For example, in the case of quantization to 12 bits (4096 steps), conventionally the quantization result was 2 rubies/)Hllll.
...IIIJ (four digits in the middle are omitted), or to prevent it from getting close to it, but in the present invention, this limit value is set to, for example, the value rllll...1100J with the last two digits of 12 bits being 0. do.

With this expansion of level regulation, rllll...1
101J, rllll...lll0J and r
Three types of codes 1111...IIIJ can be used as special codes different from the difference value ΔAi. This level regulation is also done in the analog stage, but a prohibition circuit is further provided in the digital stage.
When the three types of differential data above occur, they are all transmitted as rllll...l100J.

Even if such processing is performed, the error will be only in the last two digits, so that almost no characteristic deterioration will occur due to this.

Furthermore, in suppression type DPCM, the difference ΔAi divided by the scale factor σ is transmitted or recorded as ΔAi/σ, but if ΔAi/σ has an 8-bit configuration, the last two digits are set to the inhibit circuit as described above. Regulated by III
IIOIJ.

rIIIIIIIOJ, r1111111
All 1J may be transmitted and recorded as "11111'100". This can be easily accomplished by adding some ingenuity to the scale factor σ. Even with such a restriction, it can be said that there is no deterioration of the characteristics at all since there are only 3 steps out of the total 256 steps of the 8-bit code.

Since an 8-bit special code is used, in order to prevent the difference data ΔAt from generating a value corresponding to this special code, the third
It is sufficient to provide a prohibition circuit as shown in the figure. In the figure, symbols a7 to aO are assumed to be parallel 8B/l' data expressing differential data ΔAt. Then, the lower two bits al and a□ used for the special code are converted to
2 and 33, and when the upper 6 bits become rIIIIIIJ, bits al and 'a
No matter what the input of o is, it is forcibly turned into a Nando game) by blocking the AND gate 32.33 by 31.
Make sure that ooJ is output. If such a circuit is provided, a special code will not be generated even if scale over occurs due to the analog circuit in the previous stage.

The above special code shows the case where the last two digits of the predetermined bits are used, but of course only the last one digit is r! lll1111J.

Only rIIIIIIOJ may be used, and in some cases, the upper digits do not necessarily have to be consecutive 1's.

A special code for level correction can be set as above. In the DPCM or suppressed DPCM system, when 2 bits in a specific case are used as a special code as described above, it becomes possible to assign specific values of three types of sampling levels, so the specific value is the 0 mentioned above.
In addition to the level, any other suitable value may be set. For example, in the suppressed DPCM system, 8-bit special codes rIIIIIIOIJ, rllllll
lOJ.

r 111111114 respectively as the sampling value Ai
=+000...01. -000...01 and ro
If it corresponds to the three specific levels of o...0OJ (O level code), the probability that these specific values will occur will be three times as high as when the special code is sent only when Ai=O. In other words, the level correction is performed approximately once every 30 msec on average, making it possible to perform level correction more frequently and reliably.

Now, circuits for realizing the level correction operation as described above are shown as blow diagrams in FIGS. 4 and 5.

FIG. 4 shows an example of a circuit on the modulation (transmission or recording) side, and FIG. 5 shows an example of a circuit on the demodulation (reception or reproduction) side. However, an embodiment using a suppressed DPCM method is shown here.

The reference numeral 1 in FIG. 4 is an A/D converter that performs known sampling and quantization operations. A/
The analog signal A (t) input to the D converter l is 12
It is converted into a bit digital signal Ai. This Ai is input to a differentiating circuit consisting of a subtracter 2 and an l-step delay 3, and a difference ΔAi from the level value of the previous step is formed.

This difference data ΔAi is input to the peak hold circuit 4, and a scale factor σ for the maximum value of ΔAi for each fixed interval (here, 256 steps) is obtained.

On the other hand, the digital value Ai is 25
It is also input to 6-step delay 5.

This delay 5 is provided to set a fixed interval of 256 steps using a fixed scale factor σ.

The basic modulation operation in the circuit of FIG. 4 is performed as follows. That is, the 12-bit level data that has been delayed by a predetermined interval by delay 5 is processed by one step delay 11. A differentiation circuit consisting of a subtracter 6 converts it into 12-bit difference data ΔA'i, and further converts this difference data ΔA'i into 12-bit difference data ΔA'i.
By dividing 'i by the scale factor σ (constant) for each section formed by the block 4 in the divider 7, the difference data ΔAt/σ compressed to 8 bits is obtained. This compressed difference data ΔAi/σ is the mix circuit 1
The scale factor σ is inserted in front of each block of 256 blocks for demodulation.

However, since the original data of the compressed data has a 12-bit configuration, even if the data is multiplied by σ, an error naturally occurs. Therefore, error correction is performed using feedback loops indicated by symbols 9, 10, and 11.

That is, the actually compressed signal is multiplied by σ in the multiplier 9 to return it to the original 12 bits, and further, in the integration circuit formed by the adder 10 and the 1-step delay 11, it is returned to the signal A'i, which is converted into the signal A'i as described above. The error is corrected by using it as one input of a differentiating circuit consisting of a subtracter 6 and a one-step delay 11. (In the above, signals containing errors are indicated with a dash.) The configuration shown so far is almost the same as the known suppression type DPCM system, but in the present invention, as shown by reference numeral 8, The compressed difference signal ΔAt/σ is output through the same inhibition circuit as shown in FIG. In other words, if the 8-bit differential signal formed as described above exceeds rIIIlooJ, the prohibition circuit 8 inhibits any bit configuration from rIIIlo.
Forcibly converted to oJ. Since the inhibition circuit 8 is provided in the correction feedback loop consisting of blocks 9 to 11 as shown in the figure, even if such bit conversion is performed, the error is corrected instantly, so there is no signal deterioration on the demodulation or reproduction side. There is almost no need to worry. Furthermore, the error is as small as the last two digits, and the probability that a bit pattern corresponding to a special code will occur is also small, as described above, so from this point of view as well, it can be said that there is almost no signal deterioration.

As above, rllllllolJ, NIII
IIIOJ and r'11111. Three types of bit patterns of +11J are secured as special codes.

On the other hand, the output of the 256-step delay 5 in FIG. 4 is also input to the level detector 13 via the l-step delay 12. The level detector 13 inputs sampled level values into three specific values, namely r +
0000...0OOIJ.

r -oooo...0OOIJ and zero cross r
It is configured to generate an active signal corresponding to the case of oooo...0000J (all 12 bits). Such a circuit can be easily realized by using a gate circuit as shown in FIG. The active signals corresponding to the detection of the three specific level values are given to the switch 15, which causes the switch 15 to cut off the difference signal ΔAi/σ output from the inhibition circuit 8 to the mix circuit 16, and generate a level code instead. It is switched to input the output of the device 14.

On the other hand, the active signal corresponding to each detected specific level is also given to the level code generator 14, so that the level code generator 14 outputs the sampled value Ai
Specific level value r + 0000...0001J
, r-0000...0OOIJ, r 0
The above three types of 8-bit special codes rIIIIIIO correspond to 000...0OOOJ (12 bits), respectively.
IJ, r 11111110Jr 1111111
1” is generated.

As described above, the sampling value Ai is set to three specific values +
1.0. -1, a special code indicating this is transmitted or recorded instead of the actual difference data.

As can be easily inferred from the above, when the demodulating or reproducing side receives a special code, it is sufficient to generate a corresponding level code and use it instead of the demodulating level data. Therefore, the demodulating or reproducing side device may be configured as shown in FIG.

That is, as shown in FIG. 5, the difference signal ΔAi/σ modulated as described above is first input to the dividing circuit 51. The input signal is the scale factor σ sent every 256 data and the compressed difference signal ΔAt/σ.
divided into. The extracted scale factor σ is held in the bold circuit 52 for a predetermined period of 256 data, and is multiplied by the divided difference signal ΔAi/σ in the multiplier 53. As a result, 12-bit difference data ΔAi is output from the multiplier 53.

The difference data ΔAt is further integrated by an integrating circuit consisting of an adder 54 and a one-step delay 55 to form level data At. This level data At is further passed through a known D/A converter to restore the original analog signal.

On the other hand, the output of the dividing circuit 51 is also input to the level code detector 58 after passing through an l step delay 57 in order to match the timing with the demodulated signal. The level code detector is a circuit equivalent to that shown in Figure 4, except that it uses the 8-bit special code rIII mentioned earlier.
IIOIJ.

rllllllllOJ, rllllllllJ
is configured to detect.

The level code detector 58 receives these signals and generates active signals corresponding to the respective signals in the same manner as on the modulation side. This active signal is used as a load signal for an l-step delay 55 consisting of a memory element, etc., and is also used as a control signal for a level code generator 59. That is, the level code generator 59 generates r + 0000-OOOIJ, r-000 corresponding to the special code detected by the level code detector 58.
0-OOOOIJ.

Generate and output three specific level values: roooo...0OOOJ. These specific level values are input to the one-step delay 55 in synchronization with the load signal, and are used in place of the reproduction level code.

As described above, when a special code is input on the playback side, the output value is forcibly switched to a level value corresponding to the special code. Therefore, even if an error occurs in the differential data due to noise being mixed in during the transmission or reproduction process, the output value is automatically corrected to the correct level every time the signal passes a certain specific level value. Of course, the corrected normal level is the same as the result obtained if the modulation/demodulation is operating normally, so if the signal to be processed is an audio signal, it will not cause any discomfort to the listener. , it is possible to obtain playback signals with smooth connections. Furthermore, if there is an abnormality in the modulation/demodulation process, the level instantly returns to the normal position.

Particularly when dealing with audio signals, the specific values to be regulated as described above are ro'', r+1. , +, r-IJ, etc., the chances of correction will be very large, so even if automatic correction is performed, it is expected that the amount of correction will be very small. However, only a slight lick sound effect remains.

In the above, level correction is performed based on passage of three specific level values, but even if correction is performed only based on zero crossings, a sufficient number of corrections can be obtained in terms of probability as described above. Furthermore, if a corresponding number of special codes can be created, it is of course possible to perform level correction based on more than three specific values. Further, the specific level value does not necessarily need to be set near zero crossing, and a value that is easy to pass may be arbitrarily determined depending on the signal to be handled.

[Effect] As is clear from the above explanation, according to the present invention, A/
In a signal processing device that transmits, receives, or records/reproduces a difference value corresponding to a level change of an analog signal obtained from an analog signal by D conversion, the digital value passes one or more specific values to the transmitting or recording side device. and a means of detecting what has happened.

means for generating a special code having a predetermined configuration based on the detection result of the detection means and transmitting or recording it in place of the digital value; and means for preventing the special code from occurring as the digital value. Since the receiving or reproducing side device is provided with a means for detecting the special code and a means for forcibly outputting the specific value based on the detection result of the special code detecting means, the influence of data errors can be avoided. Therefore, it is possible to provide an excellent signal processing device that is resistant to external disturbances and can perform highly reliable signal processing without the risk of level shift.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram explaining the principle of the DPCM system, Figure 2 (A) is a waveform diagram explaining the processing of sine waves in the DPCM system, and Figure 2 (B) is the signal for the case of Figure 2 (A). A diagram showing the probability that the level passes a specific value, FIG. 3 is a circuit diagram showing an example of the inhibition circuit used in the present invention, and FIG. 4 is a block diagram showing the configuration of the suppression type DPCM modulation circuit according to the present invention. 5 are block diagrams showing the configuration of a suppression type DPCM demodulation circuit according to the present invention. 1... A/D converter 2, 6... Subtractor 3.11
, 12.57... l Step delay 7... Divider 8... Inhibition circuit 9.53... Multiplier 13.58... Level detector 14.59... Level code generator 15...・Switch 56...Decrease to D/A converter.

Claims (1)

[Claims] When transmitting/receiving signals or recording/reproducing signals using the DPCM method, the transmitting or recording side detects that the digital value corresponding to the analog signal passes one or more specific values, and if detected, a predetermined configuration is performed. means for generating and transmitting or recording a special code having a DPCM value in place of the DPCM value;
A means for inhibiting the generation of the same DPCM value as the special code as a CM value is provided, and a means for detecting the special code is provided in the receiving or reproducing device, and when the special code is detected, the decoded signal of DPCM is transmitted to the decoded signal of the DPCM. A signal processing device characterized in that each signal processing device is provided with means for forcibly returning to a specific value.