JP2612061B2 - Muting circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a predictive coding type muting circuit employing a leaky incomplete integration method.

[Conventional technology]

In digital audio equipment and the like, no unpleasant noise is generated between the time when the power is turned on and the operation of the equipment is stabilized, and no large noise is generated when the reproduction (reception) state is extremely bad. For this purpose, a muting circuit is used.

FIG. 6 is a block diagram showing a conventional muting circuit based on the zero-cross mute method. In the figure, 1
Detects a zero-crossing point of an input digital audio input signal Ai, that is, a timing at which the audio input signal Ai changes from a positive level to a negative level, or from a negative level to a positive level, and detects a logic level low (hereinafter, L level).
Level) to a logic level high (hereinafter, referred to as H level). Reference numeral 2 denotes D which holds an input muting signal M in response to a trigger clock output from the zero-cross detector 1.
3 is controlled by the output of the D-type flip-flop 2 and gates a 16-bit audio input signal Ai to output a 16-bit audio output signal.
There are 16 AND gates that output Ao.

Next, the operation will be described. FIG. 7 is a signal waveform diagram for explaining the muting operation. During normal operation, since the muting signal M input to the D-type flip-flop 2 is at the H level, a trigger clock is supplied to the D-type flip-flop 2 from the zero-cross detector 1 which has detected a zero-cross point. Also, the output of D-type flip-flop 2 is at H level. Accordingly, each AND gate 3 is open, and the input audio input signal Ai passes through each AND gate 3 as it is and is output as an audio output signal Ao.

Here, even if the muting signal M changes from the H level to the L level, the D-type flip-flop 2 keeps holding the H level of the muting signal M up to that time. Ai is output directly from each AND gate 3 as an audio signal output Ao. Thereafter, when a zero-cross is detected by the zero-cross detector 1, a trigger clock is input to the D-type flip-flop 2, and the D-type flip-flop 2 holds the L level of the muting signal M. Therefore, each AND gate 3 is turned off by being supplied with the signal of L level by the D-type flip-flop 2, and the audio input signal Ai is not transmitted to the output of the AND gate 3. As described above, the audio output signal Ao becomes “0” after being delayed until the next zero-cross point comes after the muting signal is turned on, and is in a mute-on state. This is shown in FIG.

Even if the muting signal M changes to the L level in such a mute-on state, the D-type flip-flop 2 keeps holding the L level up to that time, so that the mute-on state is continued and the audio output is continued. The signal Ao remains “0”. Thereafter, when a trigger clock is input to the D-type flip-flop 2 from the zero-cross detector 1 that has detected the zero-cross, the D-type flip-flop 2 holds the H level of the muting signal M. Therefore,
Each AND gate 3 is turned on by this H level signal, and the audio input signal Ai is
It is output as it is as audio output signal Ao,
The muting state is released. FIG. 7 (b) shows this state. After the muting signal is turned off, the state is muted off after a delay until the next zero cross point comes.

[Problems to be solved by the invention]

Since the conventional muting circuit is configured as described above, when entering the muting state or canceling the muting state, the signal level of the audio output signal Ao is rapidly maintained at "0" level. Therefore, there is a problem that noise such as a click sound may occur. As an approximation technology, "Radio technology, 198
March 7th, P86 DAT technology and its practice ".

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a muting circuit that does not easily generate noise such as a click sound when muting is turned on / off.

[Means for solving the problem]

A muting circuit according to the present invention includes: a polarity detection unit that detects the polarity of an audio input signal and an audio output signal; and a muting circuit that detects when the polarity of the audio input signal and the polarity of the audio output signal detected by the polarity detection unit are different. Muting control means for supplying a muting signal to a switch means for switching whether or not to supply an audio input signal to the decoder.

[Action]

The muting control means in the present invention supplies the muting signal to the switch means when the polarity of the audio input signal detected by the polarity detection means is different from the polarity of the audio output signal, and outputs the audio input signal to the decoder. Muting on / off by supplying
Prevents noise when turned off.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 4 denotes a decoder which decodes a digital audio input signal Ai which has a predetermined leak coefficient K smaller than 1 and is predictively coded by an incomplete integration method and outputs a digital audio output signal Ao. Differential PCM as
The decoder 5 is controlled by the muting signal M, and is an AND gate as a switch for switching whether or not to supply the audio input signal Ai to the differential PCM decoder 4. An adder 41 adds the output of the AND gate 5 and an output of a later-described K multiplier 43 to generate the audio output signal Ao, and a delay element Z delays the output of the adder 41 by one sample. ^-1 delay unit 43 is a K multiplier for multiplying the output of the Z ^-1 delay unit 42 by a leak coefficient K,
The difference PCM decoder 4 is formed by these.

FIG. 2 shows a case where a digital audio signal A is predictively encoded by an incomplete integration method having a predetermined leak coefficient K (K <1), and an audio input signal Ai decoded by the differential PCM decoder 4 is generated. FIG. 3 is a block diagram illustrating a configuration of a differential PCM encoder. In the figure, 6 is a differential PCM encoder, 61 is a Z ^-1 delay unit for delaying a digital audio signal A by one sample, 62
Is a multiplier for multiplying the output of the Z ^-1 delay unit 61 by a leak coefficient K.
A multiplier 63 is a differentiator for calculating a difference between the audio signal A and the output of the K multiplier 62.

Next, the operation will be described. First, on the differential PCM encoder 6 side, the audio signal A one sample before obtained by the Z ^-1 delay unit 61 is multiplied by a leak coefficient K by a K multiplier 62 and input to a difference unit 63. The difference unit 63 calculates the difference between the current siple value of the audio signal A and the output of the K multiplier 62, and sends the difference to the difference PCM decoder as the audio input signal Ai.

On the differential PCM decoder side, if the muting signal M is off, that is, if the AND gate 41 is open at the H level, the audio input signal Ai is input to the differential PCM decoder 4. In the differential PCM decoder 4, the signal one sample before the audio output signal Ao output from the adder 41 is calculated.
It is obtained by the Z ^-1 delay unit 42, multiplied by the leak coefficient K by the K multiplier 43, added by the adder 41 to the sent audio input signal Ai, and then added to the audio output signal.
Output as Ao.

Next, it will be described by an equation. The audio signal A input to the differential PCM encoder 6 and the audio input signal Ai output therefrom have the following relationship: Ai = A · (1−K · Z ⁻¹ ) (1) On the other hand, the relationship between the audio input signal Ai input to the differential PCM decoder 4 and the audio output signal Ao output therefrom is: Ao · K · Z ⁻¹ + Ai = Ao (2) ∴Ai = Ao · (1 −K · Z ⁻¹ ) (3) Therefore, when there is no error during transmission according to equations (1) and (2), that is, the audio input signal Ai output from the differential PCM encoder 6 is
Ao = A, and the signal is transmitted reliably.

In general, the differential PCM method has good compression efficiency but has a drawback that it cannot transmit a DC level. Therefore, in order to reproduce the DC level, one of the proposed methods is a differential PCM method using this leak coefficient. Even if an error occurs during transmission and the DC level temporarily fluctuates,
It is designed to attenuate automatically. That is, from equation (3) Therefore, if it is an impulse error, K
It attenuates by ⁿ (n = 0,1,2, ...) times.

Here, on the differential PCM decoder side, when the muting signal M input to the AND gate 5 is turned on, that is, at the L level, the AND gate 5 is closed, the audio input signal Ai is cut off, and the differential PCM decoder 4 Input becomes "0". Therefore, at that time, the level of the audio output signal Ao decoded by the differential PCM decoder 4 becomes
By passing through the loop of the Z ^-1 delay unit 42, the K multiplier 43, and the adder 41, the attenuation characteristic is smoothly reduced by the attenuation characteristic of K ⁿ (n = 0, 1, 2,...) Converge to “0” level. Third
FIG. 7A shows this state, and the muting operation is started smoothly at the same time when the muting signal M is turned on.

When the muting signal M changes from on to off, the AND gate 5 is opened, and the audio input signal Ai from the differential PCM encoder 6 is transmitted to the differential PCM decoder 4.
Is input to Immediately, muting is released more smoothly than the “0” level, and a normal decoding state is set. FIG. 3 (b) illustrates this.

Here, in the muting circuit configured as described above, the muting operation is started at the same time when the muting signal M is turned on, and the signal level starts to attenuate.
As shown in FIG. 3 (c), a sharp waveform may be generated at the moment when the muting state is entered, which may generate a click sound. FIG. 4 is a block diagram showing a muting circuit which also prevents the generation of such a click sound.

In the figure, 4 is a differential PCM decoder, 5 is an AND gate, 41 is an adder, 42 is a Z ^-1 delay unit, 43 is a K multiplier,
Since these are the same as or equivalent to those given the same reference numerals in FIG. 1, detailed description will be omitted. Also, 71
Is an input polarity discriminator for discriminating the polarity of the audio input signal Ai input to the differential PCM decoder 4;
An output polarity discriminator 7 for discriminating the polarity of the audio output signal Ao output from the decoder 4, and 7 is a polarity detecting means including an input polarity discriminator 71 and an output polarity discriminator 72. Reference numeral 8 denotes muting control means for supplying a muting signal M to the switch means 5 when the polarity of the audio input signal Ai and the polarity of the audio output signal Ao detected by the polarity detection means 7 are different.

Next, the operation will be described. When the input muting signal M is turned on, the muting control means 8 determines the polarity of the audio input signal Ai input to the differential PCM decoder 4 by the input polarity discriminator 71,
The polarity of the audio output signal Ao output from the PCM decoder 4 is discriminated by the output polarity discriminator 72, and the muting operation is temporarily suspended until the polarities of both signals become different signs. When it is detected that the polarities of both signals have different signs, the muting control means 8 transmits the muting signal M which is turned on to the AND gate 5.
The AND gate 5 is closed by this muting signal M, the audio signal input Ai is cut off, and the differential
The input of the PCM decoder 4 becomes "0". Therefore, the level of the audio output signal Ao decoded by the differential PCM decoder 4 at that time is equal to the Z ^-1 delay unit 42, the K multiplier 43,
By passing through the loop of the adder 41, K ⁿ (n = 0,1,
2,...) Times the attenuation characteristic and smoothly decreases, and finally converges to the “0” level. As described above, after the muting signal M is turned on, the input / output polarity of the differential PCM decoder 4 waits until the input / output polarity becomes a different sign to turn on the mute-on state. There is no sharp waveform as in c), and a click sound due to this can be prevented. FIG. 5 (a) shows such a situation, in which a smooth muting operation is started.

Similarly, when the muting signal M changes from on to off, the muting control means 8 releases muting until the polarity determined by the input polarity discriminator 71 and the output polarity discriminator 72 becomes a different sign. It waits for the input, and when it is detected that the code is different, the muting signal M that is turned off is transmitted to the AND gate 5. The AND gate 5 is opened by the muting signal M,
The audio input signal Ai is input to the differential PCM decoder 4. Then, the muting is immediately released without skipping the level from the “0” level, and a normal decoding state is set. FIG. 5 (b) illustrates this.

In the above embodiment, the case where the differential PCM method is used has been described. However, any method may be used as long as it is a predictive coding method and has a leak having a predetermined leak coefficient K, such as an attenuation curve. However, the same effect as in the above embodiment can be obtained, although there may be a slight difference in the above.

〔The invention's effect〕

As described above, according to the present invention, when the polarity of the audio input signal and the audio output signal are different from each other, the polarity detection unit that detects the polarity of the audio input signal and the audio output signal is different. And muting control means for supplying a muting signal to a switch means for switching whether or not to supply an audio input signal to the decoder. This has the effect of obtaining a muting circuit that can more reliably prevent noise such as sound.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a muting circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a differential PCM encoder for providing an audio input signal to the muting circuit, and FIG. 4 is a signal waveform diagram for explaining the operation of the muting circuit shown in FIG. 4, FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a signal waveform diagram for explaining the operation thereof, and FIG. Is a block diagram showing a conventional muting circuit, and FIG. 7 is a signal waveform diagram for explaining the operation. 4 is a decoder (difference PCM decoder), 41 is an adder, 42 is Z ^-1
A delay unit, 43 is a K multiplier, 5 is a switch means (AND gate), 7 is a polarity detecting means, 71 is an input polarity discriminator, 72 is an output polarity discriminator, and 8 is a muting control means. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A decoder for decoding an audio input signal encoded by predictive encoding of an incomplete integration method having a smaller predetermined leak coefficient, and outputting the decoded audio input signal as an audio output signal; Switch means controlled by a signal to switch whether or not to supply the audio input signal to the decoder; polarity detection means for detecting the polarity of the audio input signal and the audio output signal; and Muting control means for supplying the muting signal to the switch means when the polarity of the audio input signal detected by the means is different from the polarity of the audio output signal.