JPH02183632A - Muting circuit - Google Patents

Abstract

PURPOSE:To devise a circuit such that a noise such as a clock noise hardly takes place at muting on/off-state by providing a switch means using a muting signal so as to control the supply of an audio input signal to a decoder. CONSTITUTION:In the case of turning muting signal M on a decoder 4 uses a switching means 5 to interrupt the input of an audio input signal Ai, thereby allowing a smooth muting operation according to the attenuation of K<n>-times (n=1, 2,...) with respect to a signal level of an audio output signal AO at that point of time in response to a prescribed leakage coefficient K (K<1) Moreover, in the case of turning the muting signal M off, the switching means 5 receives the audio input signal Ai to release immediately the muting without level jump from the '0' level. Consequently, a noise such as a clock noise hardly takes place at muting on/off-state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a predictive coding muting circuit that employs an incomplete integration method with leakage.

[Conventional technology]

With digital audio equipment, etc., it is important to prevent unpleasant noises from occurring after the power is turned on until the equipment's operation becomes stable, and to prevent large noises from occurring even when the playback (reception) conditions are very poor. To do this, a muting circuit is used.

FIG. 6 is a block diagram showing a conventional muting circuit using the zero-cross muting method. In the figure, 1 detects the zero-crossing point of the manually input digital audio input signal At, that is, the timing at which the audio input signal Ai changes from a positive level to a negative level or from a negative level to a positive level, and detects the logic level low ( This is a zero-cross detector that generates a trigger clock by the rising edge output from logic level high (hereinafter referred to as H level). Also, 2
D holds the muting signal M manually input by the trigger clock output from the zero cross detector 1.
The D-type flip-flop 3 is controlled by the output of the D-type flip-flop 2, and 16 AND gates gate the 16-bit audio input signal Ai to output the 16-bit audio output signal AO.

Next, the operation will be explained. FIG. 7 is a signal waveform diagram for explaining the muting operation. During normal operation, the muting signal M input to the D-type flip-flop 2 is at H level, so the trigger clock is set to D by the zero-cross detector 1 that has detected the zero-cross point.
Even if the signal is applied to the D-type flip-flop 2, the output of the D-type flip-flop 2 is at H level.

Therefore, each AND gate 3 is open, and the input audio input signal At passes through each AND gate 3 as it is and is output as an audio output signal AO.

Here, even if the muting signal M changes from the H level to the L level, the D-type flip-flop 2 continues to hold the H level of the muting signal M up to that point, so the manually input audio input signal At is directly output from each AND gate 3 as an audio signal output AO. Thereafter, when a zero cross is detected by the zero cross detector 1, a trigger clock is input to the D-type flip-flop 2, and the D-type flip-flop 2 holds the muting signal M at the L level. Therefore, each ant gate 3 is supplied with an L level signal by the D-type flip-flop 2 and turned off, and the audio input signal At is not transmitted to the output of the AND gate 3. In this way, the audio output signal AO is delayed from when the muting signal is turned on until the next zero-crossing point arrives, and then becomes 0' and enters the mute-on state. The situation is described in Section 7 (a).

In such a mute-on state, even if the muting signal M changes to L level, the D-type flip-flop 2
continues to hold the previous L level, the mute-on state continues and the audio output signal AO becomes “
0゛.

It remains as it is. Thereafter, when a trigger clock is input to the D-type flip-flop 2 from the zero-cross detector 1 that has detected the zero-cross, the D-type flip-flop 2 holds the muting signal M at the H level. Therefore, each ant gate 3 is switched on by this H level signal, and the audio input signal A1 is directly output from the AND gate 3 as the audio output signal AO.
The muting state is canceled. FIG. 7(b) shows this situation; after the muting signal is turned off, there is a delay until the next zero-crossing point arrives, and then the mute-off state is entered.

[Problem to be solved by the invention]

Since the conventional muting circuit is configured as described above, when entering the muting state or canceling the muting state, the signal level of the audio output signal Ao is suddenly maintained at the “0°° level.” Because it is a digital camera, there is a problem in that it may produce click-like noise.In addition, as an approximation technology, it was described in ``Radio Technology, March 1987 issue, P.86, DAT technology and its practice''. There is something.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a muting circuit that is less likely to produce noise such as a click sound when muting is turned on/off.

[Means for Solving the Problems] A muting circuit according to the present invention includes a decoder that decodes an audio input signal predictively encoded by an incomplete integration method having a predetermined leak coefficient smaller than 1; The muting circuit according to another aspect of the present invention further comprises a switch means for controlling supply of the signal to the decoder using a muting signal. The device includes a polarity detection means for detecting and a muting control means for supplying a muting signal to the switch means when the detected polarity is different.

[Effect]

In the decoder of the present invention, when the muting signal is on, the switch means cuts off the input of the audio input signal, thereby adjusting the signal of the audio output signal at that time according to a predetermined leak coefficient K (K<1). The muting operation is performed smoothly according to the attenuation of Kn (n = 1.2, 3.----) times from the level, and when the muting signal is off, the audio input signal is inputted by the switch means, and the muting operation is performed immediately.゛°0°° To cancel muting without level jumping from the level. Further, in another aspect of the present invention, the muting control means supplies a muting signal to the switch means when the input signal and the output signal of the decoder have different polarities, muting operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 4 is a decoder that decodes a digital audio input signal Ai predictively encoded using an incomplete integration method and outputs a digital audio output signal Ao, which has a predetermined leak coefficient K smaller than 1. Difference P
The CM decoder is an AND gate 5 which is controlled by the muting signal M and serves as a switch means for switching whether or not to supply the audio input signal Ai to the differential PCM decoder 4. In addition, 41 adds the output of the AND gate 5 and the output of the multiplier 43, which will be described later.
The adder 42 that generates the audio output signal Ao delays the output of the adder 41 by one sample z −
1 delay device 43 is a multiplier that multiplies the output of this z-1 delay device 42 by a leakage coefficient K, and the differential PCM decoder 4 is formed by these.

Further, in FIG. 2, a digital audio signal A is predictively encoded by an incomplete integration method having a predetermined leakage coefficient K (K<1) to generate an audio input signal Ai that is decoded by the differential PCM decoder 4. FIG. 2 is a block diagram showing the configuration of a differential PCM encoder. In the figure, 6 is its differential PCM encoder, and 61 is z-1 which delays the digital audio signal A by one sample.
A delay device 62 is a multiplier for multiplying the output of the z-1 delay device 61 by a leakage coefficient K, and 63 is a difference device for taking the difference between the audio signal A and the output of the multiplier 62.

Next, the operation will be explained. First, on the side of the differential PCM encoder 6, a leak coefficient K is applied to the audio signal A obtained by the Z-1 delay device 61 one sample before the multiplier 6.
The resultant signal is multiplied by 2 and input to the subtractor 63. The subtractor 63 takes the difference between the current sipule value of the audio signal A and the output of the multiplier 62, and sends it to the differential PCM decoder side as an audio input signal At.

On the differential PCM decoder side, if the muting signal M is off, that is, at H level and the AND gate 41 is open, the audio input signal At is input to the differential PCM decoder 4.

The differential PCM decoder 4 converts the signal one sample before the audio output signal Ao output from the adder 41 by z-1
The signal obtained by the delay device 42 is multiplied by the leakage coefficient K by the K multiplier 43, and the signal is added to the transmitted audio input signal At by the adder 41, which is output as the audio output signal Ao.

Next, it will be explained using a formula. Between the audio signal A input to the differential PCM encoder 6 and the audio input signal Ai output from it, Ai=A・(1−K −Z−′) −−−−−−−−(
There is the relationship 1). On the other hand, the relationship between the audio input signal Ai manually input to the differential PCM decoder 4 and the audio output signal Ao output from it is A o −K −Z−′+A i =A o −−−
--(2),'-A i =Ao ・(1-K -Z-
') -----(3). Therefore, formula (1),
(2) If there is no error during transmission, that is, the difference P
Audio input signal A output from CM encoder 6
If t is manually input to the differential PCM decoder 4 as it is, Ao=A, and the signal will be reliably transmitted.

- Although the differential PCM method for IHQ has good compression efficiency, it has the drawback of not being able to transmit DC levels. One of the methods proposed to reproduce the DC level
One is a differential PCM method that uses this leak coefficient, and even if an error occurs during transmission and the DC level fluctuates over time, it is automatically attenuated. That is, from equation (3), it can be expressed as 81 Ao= = Ai・(1,000 to −Z−′+ to 24−2+ to 34−3+−−−)1−K・z−1, so the impulse-like If it is wrong, K'
It is attenuated by (n=o, 1, 2.---) times.

Here, on the differential PCM decoder side, when the muting signal M input to the AND gate 5 is turned on, that is, goes to L level, the anchor 5 is closed, the audio input signal At is cut off, and the manual input of the differential PCM decoder 4 is becomes 0″°. Therefore, at that point, the level of the audio output signal AO decoded by the differential PCM decoder 4 is
0 (n=o, 1,
2. -----) times the damping characteristic, and finally converges to the ``0'' level. FIG. 3(a) shows this situation, and the muting operation starts smoothly at the same time as the muting signal M is turned on.

Further, when the muting signal M changes from on to off, the AND gate 5 is opened and the audio input signal Ai from the differential PCM encoder 6 is input to the differential PCM decoder 4. Immediately, muting is canceled without any level jump beyond the "o" level, and a normal decoding state is established. This situation is shown in FIG. 3(b).

Here, in the muting circuit configured in this way,
The muting operation starts at the same time as the muting signal M turns on, and the signal level begins to attenuate.
As shown in Figure (C), a sharp waveform may be generated at the moment the muting state is entered, which may generate a click sound. FIG. 4 is a block diagram showing a muting circuit that prevents the generation of such lick sounds.

In the figure, 4 is a differential PCM decoder, 5 is an AND gate, 41 is an adder, 42 is a z-1 delay device, and 43 is a multiplier, and these are the same as those with the same symbols in FIG. Since this is a considerable portion, detailed explanation will be omitted. Further, 71 is an input polarity discriminator for discriminating the polarity of the audio input signal At input to the differential PCM decoder 4, and 72 is an output polarity discriminator for discriminating the polarity of the audio output signal AO output from the differential PCM decoder 4. 7 is the input polarity discriminator 71 and the output polarity discriminator 7.
This is a polarity detection means consisting of 2. Reference numeral 8 denotes muting control means for supplying a muting signal M to the switch means 5 when the polarity of the audio input signal Ai and the polarity of the audio output signal AO detected by the polarity detection means 7 are different.

Next, the operation will be explained. Muting control means 8
When the muting signal M input manually is turned on, the input polarity discriminator 71 determines the polarity of the audio input signal Ai input manually to the differential PCM decoder 4.
The output polarity discriminator 72 discriminates the polarity of the audio output signal Ao output from the differential PCM decoder 4, and if the polarities of both signals are of opposite signs, the muting operation is temporarily put on hold. When it is detected that the polarities of the two signals have opposite signs, the muting control means 8 transmits the muting signal M which is turned on to the AND gate 5. This ON muting signal M closes the AND gate 5, cuts off the audio signal input At, and the input of the differential PCM decoder 4 becomes 0°.Therefore, at that point, the differential PCM decoder 4 decodes the signal. The level of the audio output signal Ao is z
-1 delayer 42, K multiplier 43, adder 41 loop to 0 (n = 0, 1, 2
, --1-) times the damping characteristic, and finally reaches the °゛O''O'' level. In this way, after the muting signal M is turned on, the mute-on state is established after waiting for the input and output polarities of the differential PCM decoder 4 to have opposite signs, so the point at which attenuation starts is shown in FIG. There is no sharp waveform as shown in C), and the click noise caused by this can be prevented. FIG. 5(a) shows this situation, and a smooth muting operation is started.

Similarly, when the muting signal M changes from on to off, the muting control means 8 cancels the muting until the polarities determined by the input polarity discriminator 71 and the output polarity discriminator 72 have opposite signs. When the muting signal M is detected as having a different sign, the muting signal M, which is turned off, is transmitted to the AND gate 5. The AND gate 5 is opened by this muting signal M, and the audio input signal Ai is input to the differential PCM decoder 4. Immediately, the muting is canceled without any level jump above the OII level, and the normal decoding state is established. This situation is shown in FIG. 5(b).

In the above embodiment, a differential PMC method is used, but any predictive coding method may be used as long as it has leakage at a predetermined leakage coefficient. Although some differences may occur, the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, when the muting signal is on, the input of the audio input signal is cut off by the switch means, and the attenuation characteristic is set according to the predetermined leakage coefficient K from the signal level of the audio output signal at that time. According to
The muting operation is performed smoothly, and when the muting signal is turned off, the audio input signal is input using the switch means and the muting is immediately canceled, so noises such as clicks are not generated when the muting is turned on/off. It is possible to obtain a muting circuit that is unlikely to generate noise, and there is no delay time from when the muting signal turns on or off until it actually enters the muting state or until the muting state is actually released. There is an effect that the circuit can obtain.

According to another aspect of the present invention, when the polarity of the input signal and the output signal of the decoder are different, a muting signal is supplied to the switch means to cause the decoder to perform the above-mentioned muting operation. Since the structure is configured such that the muting is turned on and off, it is possible to obtain a muting circuit that can more reliably prevent noises such as click sounds when muting is turned on and off.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a muting circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a differential PCM encoder that provides an audio input signal to the muting circuit, and FIG. FIG. 4 is a block diagram showing another embodiment of the present invention; FIG. 5 is a signal waveform diagram explaining the operation; FIG. 6 is a signal waveform diagram for explaining the operation of the muting circuit shown in FIG. 7 is a block diagram showing a conventional muting circuit, and FIG. 7 is a signal waveform diagram for explaining its operation. 4 is a decoder (differential PCM decoder), 41 is an adder, 4
2 is a z-1 delay device, 43 is a doubler, and 5 is a switch means (
7 is a polarity detection means, 71 is a manual polarity discriminator, 72 is an output polarity discriminator, and 8 is a muting control means. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1 (0) Mute on Figure 3 5 Switch means (completed) -to-off

Claims (2)

[Claims] (1) A decoder that decodes an audio input signal encoded by incomplete integral predictive encoding with a predetermined leak coefficient smaller than 1 and outputs it as an audio output signal, and a decoder that is controlled by a muting signal. and switch means for switching whether or not to supply the audio input signal to the decoder. (2) a decoder that decodes an audio input signal encoded by incomplete integral predictive coding with a predetermined leak coefficient smaller than 1 and outputs it as an audio output signal; and a decoder that is controlled by a muting signal. a switch means for switching whether or not to supply the audio input signal to the decoder; a polarity detection means for detecting the polarity of the audio input signal and the audio output signal; A muting circuit comprising muting control means for supplying the muting signal to the switch means when the polarity of the audio input signal and the polarity of the audio output signal are different.