JPS61107238U - - Google Patents
Info
- Publication number
- JPS61107238U JPS61107238U JP19162484U JP19162484U JPS61107238U JP S61107238 U JPS61107238 U JP S61107238U JP 19162484 U JP19162484 U JP 19162484U JP 19162484 U JP19162484 U JP 19162484U JP S61107238 U JPS61107238 U JP S61107238U
- Authority
- JP
- Japan
- Prior art keywords
- separation area
- tuner
- circuit board
- circuit
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims 8
- 239000000758 substrate Substances 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
Description
第１Ａ図および第１Ｂ図は本考案の一実施例と
しての回路基板を示す図、第２図はチユーナ回路
とＩＦ処理回路を別々の基板として用いる場合の
図解図第３Ａ図、第３Ｂおよび第３Ｃ図は本考案
の他の実施例を示す図である。
１，１３……回路基板、２，２′……チユーナ
回路用補助基板、３，３′……ＩＦ処理回路用補
助基板、５，７……接続器具、１０……ミシン目
、１１，１１′……接続用電極、１４……Ｖ字溝
。
1A and 1B are diagrams showing a circuit board as an embodiment of the present invention, and FIG. 2 is an illustrative diagram of the case where the tuner circuit and the IF processing circuit are used as separate boards. Figure 3C shows another embodiment of the present invention. 1, 13... Circuit board, 2, 2'... Auxiliary board for tuner circuit, 3, 3'... Auxiliary board for IF processing circuit, 5, 7... Connecting device, 10... Perforation, 11, 11 '... Connection electrode, 14... V-shaped groove.
Claims (1)
基板上に電気回路的に独立し離間配置すると共に
、このチユーナ回路と中間周波処理回路間の基板
にそれら両者の分離を可能にする切離区域が形成
され、かつこの切離区域で分離される２つの基板
を電気的に接続する接続端子部を前記チユーナ回
路及び中間周波処理回路側の基板上に形成したこ
とを特徴とするチユーナ用回路基板。 (2) 前記切離区域は、Ｖ字溝であることを特徴
とする実用新案登録請求の範囲第(1)項記載のチ
ユーナ用回路基板。 (3) 前記切離区域は、ミシン目に形成されてい
ることを特徴とする実用新案登録請求の範囲第(1
)項記載のチユーナ用回路基板。 (4) 前記接続端子部は、前記切離区域に交差し
て２つの基板を電気的に接続するように形成され
た導電パターンであることを特徴とする実用新案
登録請求の範囲第(1)項ないし第(3)項のいずれか
に記載のチユーナ用回路基板。 (5) 前記接続端子部は、前記切離区域に交差し
て形成された導電パターンと、切離区域で区切ら
れる２つの基板のそれぞれに装着されかつ対応す
る導電パターンに電気的に接続された接続器具と
を含むことを特徴とする実用新案登録請求の範囲
第(1)項ないし第(3)項のいずれかに記載のチユー
ナ用回路基板。[Claims for Utility Model Registration] (1) A tuner circuit and an intermediate frequency processing circuit are electrically separated and arranged independently on a common board, and both of them are arranged on a board between the tuner circuit and the intermediate frequency processing circuit. A separation area that enables separation is formed, and a connection terminal portion for electrically connecting the two substrates separated by the separation area is formed on the substrate on the tuner circuit and intermediate frequency processing circuit side. A circuit board for tuners featuring the following. (2) The tuner circuit board according to claim (1), wherein the separation area is a V-shaped groove. (3) Utility model registration claim No. (1) characterized in that the separation area is formed at a perforation.
Circuit board for tuner described in ). (4) Utility model registration claim (1) characterized in that the connection terminal portion is a conductive pattern formed to cross the separation area and electrically connect the two substrates. The tuner circuit board according to any one of items (3) to (3). (5) The connection terminal portion is attached to a conductive pattern formed across the separation area and to each of two substrates separated by the separation area and electrically connected to the corresponding conductive pattern. A circuit board for a tuner according to any one of claims (1) to (3) of the claims registered as a utility model, characterized in that the circuit board includes a connecting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19162484U JPS61107238U (en) | 1984-12-17 | 1984-12-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19162484U JPS61107238U (en) | 1984-12-17 | 1984-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107238U true JPS61107238U (en) | 1986-07-08 |
Family
ID=30749064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19162484U Pending JPS61107238U (en) | 1984-12-17 | 1984-12-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107238U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006314027A (en) * | 2005-05-09 | 2006-11-16 | Sharp Corp | High frequency receiver |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5339248B2 (en) * | 1974-12-26 | 1978-10-20 |
-
1984
- 1984-12-17 JP JP19162484U patent/JPS61107238U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5339248B2 (en) * | 1974-12-26 | 1978-10-20 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006314027A (en) * | 2005-05-09 | 2006-11-16 | Sharp Corp | High frequency receiver |
| JP2015195272A (en) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | Semiconductor device and semiconductor manufacturing method |
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