JPS61103973U - - Google Patents
Info
- Publication number
- JPS61103973U JPS61103973U JP1984186387U JP18638784U JPS61103973U JP S61103973 U JPS61103973 U JP S61103973U JP 1984186387 U JP1984186387 U JP 1984186387U JP 18638784 U JP18638784 U JP 18638784U JP S61103973 U JPS61103973 U JP S61103973U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- output terminal
- input terminal
- emphasis
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Television Systems (AREA)
- Filters And Equalizers (AREA)
Description
第１図は本考案のプリエンフアシス回路の基本
回路図。第２図は直流バイアスを任意に設定でき
るようにした本考案のプリエンフアシス回路図。
第３図は従来のプリエンフアシス回路の基本回路
図。第４図は直流バイアスを設定できる従来のプ
リエンフアシス回路図。第５図はプリエンフアシ
ス、デイエンフアシスの説明図。第６図はプリエ
ンフアシス回路の周波数特性グラフ。横軸は周波
数、縦軸は相対レベルの対数である。第７図はｆ
１＝０．１８７ＭＨｚ，ｆ２＝０．８７５ＭＨｚ
とした時のプリエンフアシス（実線）、デイエン
フアシスカーブを示すグラフ。横軸は周波数を対
数目盛で示し、縦軸は相対レベルを対数目盛で示
す。
Ｒ１，Ｒ２……回路定数設定用抵坑、Ｃ……回
路定数設定用コンデンサ、Ｒｄ，Ｒｕ……直流バ
イアス設定用抵抗。Ｃａ，Ｃｄ……コンデンサ。
FIG. 1 is a basic circuit diagram of the pre-emphasis circuit of the present invention. FIG. 2 is a pre-emphasis circuit diagram of the present invention that allows DC bias to be set arbitrarily.
Figure 3 is a basic circuit diagram of a conventional pre-emphasis circuit. Figure 4 is a conventional pre-emphasis circuit diagram that can set DC bias. FIG. 5 is an explanatory diagram of pre-emphasis and de-emphasis. Figure 6 is a frequency characteristic graph of the pre-emphasis circuit. The horizontal axis is the frequency, and the vertical axis is the logarithm of the relative level. Figure 7 shows f
1 = 0.187MHz, f 2 = 0.875MHz
Graph showing pre-emphasis (solid line) and de-emphasis curve when The horizontal axis indicates frequency on a logarithmic scale, and the vertical axis indicates relative level on a logarithmic scale. R1 , R2 ...Resistor for circuit constant setting, C...Capacitor for circuit constant setting, Rd, Ru...Resistor for DC bias setting. Ca, Cd... Capacitor.
Claims (1)
互いに相補な出力端子ＯＵＴと出力端子を
有し、入力端子ＩＮと出力端子ＯＵＴぎ抵抗Ｒ１
とコンデンサＣの並列体によつて接続され、入力
端子と出力端子がが抵抗Ｒ１とコンデ
ンサＣの並列体によつて接続され、かつ両出力Ｏ
ＵＴ，間が抵抗２Ｒ２で接続されており、
伝達函数が Ｈ（Ｓ）＝１十τ１Ｓ１十τ２Ｓ τ１＝ＣＲ１ τ２＝Ｃ（Ｒ１Ｒ２） で与えられる事を特徴とするプリエンフアシス回
路。[Claims for Utility Model Registration] An input terminal IN and an input terminal that are complementary to each other and an output terminal OUT and an output terminal that are complementary to each other, and a resistor R1 between the input terminal IN and the output terminal OUT.
and a capacitor C in parallel, the input terminal and the output terminal are connected by a resistor R1 and a capacitor C in parallel, and both outputs O
UT, is connected with a resistor 2R2 ,
A pre-emphasis circuit characterized in that a transfer function is given by H(S)=10τ 1 S10τ 2 S τ 1 =CR 1 τ 2 =C(R 1 R 2 ).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984186387U JPS61103973U (en) | 1984-12-07 | 1984-12-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984186387U JPS61103973U (en) | 1984-12-07 | 1984-12-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103973U true JPS61103973U (en) | 1986-07-02 |
Family
ID=30743854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984186387U Pending JPS61103973U (en) | 1984-12-07 | 1984-12-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103973U (en) |
-
1984
- 1984-12-07 JP JP1984186387U patent/JPS61103973U/ja active Pending
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