JPS61103974U - - Google Patents
Info
- Publication number
- JPS61103974U JPS61103974U JP1984186388U JP18638884U JPS61103974U JP S61103974 U JPS61103974 U JP S61103974U JP 1984186388 U JP1984186388 U JP 1984186388U JP 18638884 U JP18638884 U JP 18638884U JP S61103974 U JPS61103974 U JP S61103974U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input terminal
- output terminal
- terminal
- complementary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Television Systems (AREA)
- Filters And Equalizers (AREA)
Description
第１図は本考案のデイエンフアシス回路の基本
回路図。第２図は本考案のデイエンフアシス回路
であつて直流バイアスを与えた回路図。第３図は
デイエンフアシス回路の基本回路図。第４図は従
来のデイエンフアシス回路図。第５図は従来のデ
イエンフアシス回路であつて直流バイアスを与え
た回路図。第６図はプリエンフアシス、デイエン
フアシスの説明図。第７図はデイエンフアシスカ
ーブの説明図。第８図はプリエンフアシス、デイ
エンフアシスカーブのグラフ。
Ｒ１，２Ｒ２，２Ｒ３……回路定数設定用抵抗
、Ｃ……回路定数設定用コンデンサ、Ｒｕ，Ｒｄ
……直流バイアス設定用抵抗、Ｃａ，Ｃｄ……コ
ンデンサ。
FIG. 1 is a basic circuit diagram of the de-emphasis circuit of the present invention. FIG. 2 is a circuit diagram of the de-emphasis circuit of the present invention, in which a DC bias is applied. Figure 3 is a basic circuit diagram of the de-emphasis circuit. Figure 4 is a conventional de-emphasis circuit diagram. FIG. 5 is a circuit diagram of a conventional de-emphasis circuit in which a DC bias is applied. FIG. 6 is an explanatory diagram of pre-emphasis and de-emphasis. FIG. 7 is an explanatory diagram of the day emphasis curve. Figure 8 is a graph of pre-emphasis and de-emphasis curves. R 1 , 2R 2 , 2R 3 ... Resistor for circuit constant setting, C ... Capacitor for circuit constant setting, Ru, Rd
...DC bias setting resistor, Ca, Cd...capacitor.
Claims (1)
互いに相補な出力端子ＯＵＴと出力端子を
有し、入力端子ＩＮと出力端子ＯＵＴが抵抗Ｒ１
によつて接続され、入力端子と出力端子
が抵抗Ｒ１によつて接続され、かつ両出力端子
ＯＵＴ，間が抵抗２Ｒ３と、コンデンサＣ
／２と抵抗２Ｒ２の直列体とによつて接続されて
おり、伝達函数が Ｈ（Ｓ）＝１十τ２Ｓ１十τ１Ｓ τ１＝Ｃ（Ｒ１Ｒ３＋Ｒ２） τ２＝ＣＲ２ で与えられる事を特徴とするデイエンフアシス回
路。[Claims for Utility Model Registration] It has an input terminal IN and an input terminal that are complementary to each other and an output terminal OUT and an output terminal that are complementary to each other, and the input terminal IN and the output terminal OUT are connected to a resistor R1 .
The input terminal and the output terminal are connected by a resistor R1 , and a resistor 2R3 and a capacitor C are connected between both output terminals OUT.
/2 and a series resistor 2R2 , and the transfer function is H(S)=10τ 2 S10τ 1 S τ 1 =C(R 1 R 3 +R 2 ) τ 2 = A de-emphasis circuit characterized by being given by CR2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984186388U JPS61103974U (en) | 1984-12-07 | 1984-12-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984186388U JPS61103974U (en) | 1984-12-07 | 1984-12-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103974U true JPS61103974U (en) | 1986-07-02 |
Family
ID=30743855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984186388U Pending JPS61103974U (en) | 1984-12-07 | 1984-12-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103974U (en) |
-
1984
- 1984-12-07 JP JP1984186388U patent/JPS61103974U/ja active Pending
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