JPS6444724U - - Google Patents
Info
- Publication number
- JPS6444724U JPS6444724U JP13940187U JP13940187U JPS6444724U JP S6444724 U JPS6444724 U JP S6444724U JP 13940187 U JP13940187 U JP 13940187U JP 13940187 U JP13940187 U JP 13940187U JP S6444724 U JPS6444724 U JP S6444724U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input terminal
- inverting input
- level shift
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案によるレベルシフト回路の構成
図、そして第２図は従来のレベルシフト回路の構
成図である。
符号の説明、１，２，４，５，６……抵抗、３…
…演算増幅器。
FIG. 1 is a block diagram of a level shift circuit according to the present invention, and FIG. 2 is a block diagram of a conventional level shift circuit. Explanation of symbols, 1, 2, 4, 5, 6...Resistance, 3...
...Operation amplifier.
Claims (1)
力端子に印加し、 該反転入力端子と出力端子とを第２の抵抗２を
介して接続し、 所定のレベルシフト入力電圧Ｖｉを、前記第２
の抵抗２の抵抗値の、該第２の抵抗２の抵抗値と
前記第１の抵抗１の抵抗値との和に対する比によ
り定められる分圧比で分圧したものを、非反転入
力端子に印加する演算増幅器３を有してなること
を特徴とするレベルシフト回路。 ２ 前記レベルシフト入力電圧Ｖｉは、抵抗４を
介して前記演算増幅器３の非反転入力端子に印加
され、該非反転入力端子は抵抗５を介して接地さ
れ、 該抵抗４と該抵抗５との抵抗値の比は前記抵抗
２と抵抗１との抵抗値の比に等しい実用新案登録
請求の範囲第１項記載のレベルシフト回路。[Claims for Utility Model Registration] 1. Applying the input signal e i to the inverting input terminal via the first resistor 1, connecting the inverting input terminal and the output terminal via the second resistor 2, The level shift input voltage V i of the second
A voltage divided by a voltage dividing ratio determined by a ratio of the resistance value of the resistor 2 to the sum of the resistance value of the second resistor 2 and the resistance value of the first resistor 1 is applied to the non-inverting input terminal. 1. A level shift circuit comprising an operational amplifier 3. 2. The level shift input voltage V i is applied to the non-inverting input terminal of the operational amplifier 3 via a resistor 4, the non-inverting input terminal is grounded via a resistor 5, and the resistance between the resistor 4 and the resistor 5 is 2. The level shift circuit according to claim 1, wherein the ratio of the resistance values is equal to the ratio of the resistance values of the resistor 2 and the resistor 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940187U JPS6444724U (en) | 1987-09-14 | 1987-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940187U JPS6444724U (en) | 1987-09-14 | 1987-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6444724U true JPS6444724U (en) | 1989-03-17 |
Family
ID=31402624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13940187U Pending JPS6444724U (en) | 1987-09-14 | 1987-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6444724U (en) |
-
1987
- 1987-09-14 JP JP13940187U patent/JPS6444724U/ja active Pending
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