JPS611036A - Aligning method of semiconductor chip - Google Patents
Aligning method of semiconductor chipInfo
- Publication number
- JPS611036A JPS611036A JP12156384A JP12156384A JPS611036A JP S611036 A JPS611036 A JP S611036A JP 12156384 A JP12156384 A JP 12156384A JP 12156384 A JP12156384 A JP 12156384A JP S611036 A JPS611036 A JP S611036A
- Authority
- JP
- Japan
- Prior art keywords
- transfer plate
- semiconductor chips
- polarity
- chip
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は多数の半導体チップをその極性を特定方向に揃
えて整列させる半導体チップの整列方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor chip alignment method for aligning a large number of semiconductor chips with their polarities aligned in a specific direction.
［従来技術］
半導体素子を量産する場合、例えば第３図に示すように
所定のＰ−Ｎ接合を形成した半導体ウェハ（１）を個々
の半導体チップ（２）に分割した後、このチップ（２）
の電気的特性をチェックしながら１個毎に図示を省略し
た真空ピンセットで吸着しリードフレーム（３）上の所
定位置に搭載し以後所定の処理が施されるという方法が
採られている。[Prior Art] When mass producing semiconductor devices, for example, as shown in FIG. )
While checking the electrical characteristics of the lead frame (3), each lead is picked up using vacuum tweezers (not shown), mounted at a predetermined position on the lead frame (3), and then subjected to a predetermined process.
あるいはリードフレーム（３）に搭載する前にシート（
４）上の個々に分割された半導体チップ（２）の特性を
チェックした後、別に用意されたトレイに１個毎に真空
ビンセットで吸着し極性を揃えこれをさらにリードフレ
ーム（３）上に移すという方法が採られている。Alternatively, the sheet (
4) After checking the characteristics of the individually divided semiconductor chips (2) above, they are sucked one by one onto a separately prepared tray using a vacuum bottle set, and the polarities are aligned, and this is further placed on the lead frame (3). The method used is to move.
しかるに上記の方法による場合、多数かつ小片の半導体
チップを手作業で取扱うので作業能率が向上しないとい
う欠点があった。However, the above-mentioned method has the disadvantage that the work efficiency cannot be improved because a large number of small pieces of semiconductor chips must be handled manually.
［発明の概要］
本発明は上記の事情に基づきなされたもので、半導体チ
ップの電気的特性および極性をチェックしつつ良品の半
導体チップのみを特定方向に極性を揃えて大量に整列さ
せることができる半導体チップの整列方法を提供するこ
とを目的とする。[Summary of the Invention] The present invention has been made based on the above circumstances, and it is possible to check the electrical characteristics and polarity of the semiconductor chips and to align only good semiconductor chips in large quantities with their polarities aligned in a specific direction. The purpose of the present invention is to provide a method for aligning semiconductor chips.
［発明の実施例コ
以下に本発明の一実施例につぎ第１図および第２図を参
照して説明する。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は本発明の方法を実施するための装置の要素を概
略的に示したものである。FIG. 1 schematically shows the elements of an apparatus for carrying out the method of the invention.
同図において（１０）は第１の転写板、（１１）は第２
の転写板であって、これらはその表面には縦、横に半導
体チップを収納するための多数の凹所（１０ａ ）、（
１１ａ ＞が形成サレ；Ｘ （７） 凹所（１０ａ）、
（１１ａ）は同一ピッチおよび第２の転写板（１１）上
に第１の転写板（１０）を反転させて重ね合せた場合に
相互に一致する位置に形成されている。In the figure, (10) is the first transfer plate, and (11) is the second transfer plate.
These transfer plates have a large number of recesses (10a) and (10a) on their surfaces for storing semiconductor chips vertically and horizontally.
11a> is the formed sag;X (7) recess (10a),
(11a) are formed at the same pitch and at positions that coincide with each other when the first transfer plate (10) is reversed and stacked on the second transfer plate (11).
上記第１の転写板（１０）および第２の転写板（１１）
は絶縁材料で形成され上記第１の転写板（１０）には凹
所（１０ａ）に連通ずる導体（１２）が設けられている
。The first transfer plate (10) and the second transfer plate (11)
is made of an insulating material, and the first transfer plate (10) is provided with a conductor (12) communicating with the recess (10a).
この導体（１２）は凹所（１０ａ）内に収納される半導
体チップ（１３）の一方の面に接触し電気的特性および
極性をチェックする際の共通電極となる。This conductor (12) comes into contact with one surface of the semiconductor chip (13) housed in the recess (10a) and serves as a common electrode for checking electrical characteristics and polarity.
また、第１の転写板（１０）には各凹所（１０ａ）に通
じる透孔（１０ｂ）が設けられこの透孔（１０ｂ）はメ
イン通路（１０Ｃ）に連通し、このメイン通路（１０ｃ
）はその一端が真空ポンプ（１４）に接続される。Further, the first transfer plate (10) is provided with a through hole (10b) that communicates with each recess (10a), and this through hole (10b) communicates with the main passage (10C).
) is connected at one end to a vacuum pump (14).
（１５）は半導体チップ（１３）の電気的特性および極
性をチェックするための測定用移動ヘッドであってこの
ヘッド（１５）には第１の転写板（１０）の凹所（１０
ａ）のピッチに一致するビッヂの複数の測定針（１５ａ
）を有する。この測定針（１５ａ）はそれぞれ接続線（
１６）を介して測定ｉ？ｌ！（１７）に接続されこの測
定電源（１７）は制御装置（１８）に連結されている。(15) is a measuring movable head for checking the electrical characteristics and polarity of the semiconductor chip (13).
A plurality of measuring needles (15a) of the bitge that match the pitch of
). This measuring needle (15a) is connected to the connecting wire (
16) Measured via i? l! (17), and this measuring power supply (17) is connected to a control device (18).
制御装置（１８）では測定針（１５ａ＞で測定した半導
体チップ（１３）の電気的特性および極性を記憶し、特
性不良および特定極性の半導体チップ（１３）のみを吸
着するように後述の真空吸着ノズルに出力指令を与える
とともに半導体チップ（１３）の吸着移動工程中に特性
不良の半導体チップ（１３）の吸着を解除するように真
空吸着ノズルに指令を与える機能を備えている。The control device (18) memorizes the electrical characteristics and polarity of the semiconductor chip (13) measured by the measuring needle (15a), and performs vacuum suction as described below so as to suction only the semiconductor chip (13) with poor characteristics and a specific polarity. It has a function of giving an output command to the nozzle and also giving a command to the vacuum suction nozzle to release the suction of the semiconductor chip (13) having poor characteristics during the suction movement process of the semiconductor chip (13).
（１９）は吸着ノズル台であって、このノズル台（１９
）には前記凹所（１０ａ）、（１１ａ）のピッチに合せ
た複数の吸着ノズル（１９ａ）が設けてあり、この吸着
ノズル（１９ａ）はそれぞれ真空バルブ（１９ｂ）を介
して真空ポンプ（２０）に接続されている。(19) is a suction nozzle stand, and this nozzle stand (19)
) is provided with a plurality of suction nozzles (19a) matching the pitch of the recesses (10a) and (11a), and each suction nozzle (19a) is connected to a vacuum pump (20) via a vacuum valve (19b). )It is connected to the.
上記の吸着ノズル台（１９）は制御装置（１８）の出力
指令によって第１の転写板（１０）、第２の転写板（１
１）間の水平移動およびそれらの所定列への昇降をなす
ように構成されている。The suction nozzle stand (19) is connected to the first transfer plate (10) and the second transfer plate (1) according to the output command from the control device (18).
1) horizontal movement between them and raising and lowering them to predetermined columns.
図中（２１）は第１の転写板（１０）と第２の転写板（
１１）の間に配置された不良半導体チップ収納箱である
。In the figure (21) is the first transfer plate (10) and the second transfer plate (
This is a defective semiconductor chip storage box placed between 11) and 11).
次に上記構成の装置を用いて本発明の半導体チップの整
列方法について述べる。Next, a method for aligning semiconductor chips according to the present invention using the apparatus having the above configuration will be described.
■ まず所定のＰ−Ｎ接合が形成された半導体ウェハか
ら個々の細片チップに分割された半導体チップ（１３）
が第１の転写板（１０）の凹所（１０ａ＞に供給される
。■ First, a semiconductor chip (13) is divided into individual chip chips from a semiconductor wafer on which a predetermined P-N junction is formed.
is supplied to the recess (10a>) of the first transfer plate (10).
■ 制御装置（１８）からの指令により測定用移動ヘッ
ド（１５）が第１の転写板（１０）の第１列目の凹所（
１０ａ）上に下降しその測定側（１５ａ）を各凹所（１
０，８）内の半導体チップ（１３）の表面に接触する。■ Based on a command from the control device (18), the measuring movable head (15) moves to the recess in the first row of the first transfer plate (10) (
10a) and lower the measurement side (15a) to each recess (1
0,8) in contact with the surface of the semiconductor chip (13).
半導体チップ（１３）の下面は導体（１２）に接触し、
この導体（１２）は接続線（２２）を介して測定電源（
１７）に接続され開回路を構成し、半導体チップ（１３
）の耐几、順方向特性等の電気的特性を測定し、その測
定結果を制御装置（１８）で記憶する。The lower surface of the semiconductor chip (13) is in contact with the conductor (12),
This conductor (12) is connected to the measurement power source (
17) to form an open circuit, and the semiconductor chip (13
) are measured, and the measurement results are stored in the control device (18).
■ 次に測定用移動ヘッド（１５）を所定位置まで上昇
させた後、同じく制御装置（１８）からの指令により吸
着ノズル台（１９）を水平方向に移動しかつ第１の転写
板（１０）の第１列目の凹所（１０ａ）上に下降させる
。■ Next, after raising the measurement moving head (15) to a predetermined position, the suction nozzle stand (19) is moved horizontally according to a command from the control device (18), and the first transfer plate (10) the first row of recesses (10a).
■ 制御装置く１８）では記憶した測定結果に基づぎ特
定方向の極性および特性不良の半導体チップ（１３）を
判別し、これらの°チップ（１３）のみを吸着すべく真
空バルブ（１９ｂ）に「聞」の出力指令を出す。■ The control device (18) identifies semiconductor chips (13) with poor polarity and characteristics in a specific direction based on the memorized measurement results, and applies a vacuum valve (19b) to pick up only these chips (13). Issues an output command of "Listen".
これにより真空ポンプ（２０）から真空が吸着ノズル（
１９ａ）に供給され特・定方向の極性に対して反対極性
となる半導体チップ（１３）を残して他の半導体チップ
（１３）が吸着ノズル（１９ａ）に吸着される。As a result, vacuum is applied from the vacuum pump (20) to the suction nozzle (
The other semiconductor chips (13) are sucked into the suction nozzle (19a) except for the semiconductor chips (13) which are supplied to the semiconductor chip (19a) and have a polarity opposite to the polarity in the specific direction.
■ 制御装置（１８）の出力指令により吸着ノズル台（
１９ンが所定位置まで上昇した後、不良半導体チップ収
納箱（２１）の位置まで水平移動し、ここで同じく制御
装置（１８）の出力指令により特性不良と判別された半
導体チップ（１３）を吸着している吸着ノズル（１９ａ
）の真空バルブ（１９ｂ）を「閉」にすべく出力指令を
出し、吸着ノズル（１９ａ）から特性不良と判別された
半導体チップ（１３）を不良半導体チップ収納箱（２１
）内に落下させる。■ The suction nozzle stand (
After the 19n rises to a predetermined position, it moves horizontally to the position of the defective semiconductor chip storage box (21), where it also picks up the semiconductor chip (13) that has been determined to have defective characteristics based on the output command of the control device (18). suction nozzle (19a)
) is issued an output command to close the vacuum valve (19b), and the semiconductor chip (13) determined to have defective characteristics is transferred from the suction nozzle (19a) to the defective semiconductor chip storage box (21).
).
■ 次いで、再び吸着ノズル台（１９）を第２の転写板
（１１）の対応列、例えば第１の転写板（１０）の［Ｉ
］列を移動しているときには第２の転写板（１１）の［
１Ｆ列の直上位置まで水平移動させた後、下降させ凹所
（１コａ〉内に半導体デツプ（１３）を収納する。■ Next, move the suction nozzle stand (19) again to the corresponding row of the second transfer plate (11), for example, the [I
] column, the second transfer plate (11) [
After being horizontally moved to a position directly above the 1F row, it is lowered and the semiconductor dip (13) is housed in the recess (1 core a).
こうして第２の転写板（１１）のＮ］列には同一極性に
揃えられた半導体チップ（１３）が先の不良半導体チッ
プおよび第１の転写板（１０）に残された半導体チップ
（１３）を除いて所謂歯抜けの状態で整列される。In this way, the semiconductor chips (13) aligned with the same polarity are placed in the N] column of the second transfer plate (11), the previous defective semiconductor chip and the semiconductor chip (13) left on the first transfer plate (10). With the exception of .
以上の動作を最終列まで繰返した後、次の工程に移る。After repeating the above operations up to the last row, move on to the next step.
■ 第１の転写板（１０）の内部に設けたメイン通路（
１０ｃ）に連通ずる外部パイプ（１０ｄ＞に制御装置（
１８）の出力指令により真空・バルブ（１４ａ）を開き
真空ポンプ（１４）からの真空を供給し第１の転写板（
１０）の凹所（１０ａ）に残った半導体チップ（１３）
を吸着しつつ第１の転写板（１０）を第２の転写板（１
１〉上に反転させて重ね合せ第２図（Ｂ）に示す状態と
する。■ The main passage provided inside the first transfer plate (10) (
A control device (
18) opens the vacuum valve (14a) and supplies vacuum from the vacuum pump (14) to the first transfer plate (18).
Semiconductor chip (13) remaining in the recess (10a) of 10)
The first transfer plate (10) is attached to the second transfer plate (10) while adsorbing the
1> Flip it over and put it in the state shown in FIG. 2(B).
■ 制御装置（１８）からの出力指令により真空バルブ
（１４ａ）を閉じ、凹所（１０ａ）内への真空の供給を
断つと、凹所（１０ａ）内の残余の半導体チップ（１３
）が反転されて第２の転写板（１１）の凹所（１１ａ）
内に移る。■ When the vacuum valve (14a) is closed according to an output command from the control device (18) and the supply of vacuum to the recess (10a) is cut off, the remaining semiconductor chips (13) in the recess (10a) are removed.
) is reversed and the recess (11a) of the second transfer plate (11)
move inward.
■ 最後に制御装置（１８）からの出力指令により第１
の転写板（１０）を初期位置に復帰させた後、第２の転
写板（１１）の半導体チップ（１３）が収納されていな
い部分、すなわち特性不良として取除かれた第１の転写
＆（１０）の凹所（１０ａ）に対応する凹所（１１ａ
）の部分にはその数も少いため手作業により特定方向に
極性を揃えて半導体チップ（１３）を補充する。■ Finally, the first
After returning the transfer plate (10) to the initial position, the part of the second transfer plate (11) where the semiconductor chip (13) is not accommodated, that is, the first transfer plate (10) that has been removed due to defective characteristics, is removed. 10) A recess (11a) corresponding to the recess (10a)
) Since there are few semiconductor chips (13), the semiconductor chips (13) are manually added with the polarities aligned in a specific direction.
なお、測定！−１（１５ａ）および吸着ノズル（１９ａ
）のピッチは転写板（１０ａ）、（１１ａ）のピッチの
一つおきのピッチとして、１列の穴を２回に分けて測定
、吸着を行いチップを移動させることにより、微小サイ
ズのチップを取り扱うこともできる。In addition, measurement! -1 (15a) and suction nozzle (19a)
) is every other pitch of the transfer plates (10a) and (11a), and by measuring and adsorbing the holes in one row twice and moving the chips, micro-sized chips can be obtained. It can also be handled.
［発明の効果］
本発明は上記のように構成したので、第２の転写板上に
は半導体チップの極性がすべて同一方向に揃えられしか
も一列毎に同時に自動的に行なわれるので、整列作業の
作業能率を向上させるとともに次工程の例えば半導体チ
ップをリードフレームに供給する場合に極性が同一方向
に揃えられているので、容易に供給工程の自動化が可能
であり、半導体素子の製造効率を向上させ得る。[Effects of the Invention] Since the present invention is configured as described above, the polarities of the semiconductor chips on the second transfer plate are all aligned in the same direction, and the alignment is automatically performed for each row at the same time. In addition to improving work efficiency, the polarity is aligned in the same direction during the next process, for example when feeding semiconductor chips to a lead frame, making it easy to automate the feeding process and improve the manufacturing efficiency of semiconductor devices. obtain.
さらに特性不良の半導体チップが第１の転写板から第２
の転写板へ移動させる工程で自動的に除去することがで
き最終製品の信頼性の向上に寄与することかできる。Furthermore, semiconductor chips with poor characteristics are transferred from the first transfer plate to the second transfer plate.
It can be automatically removed during the transfer process to the transfer plate, contributing to improving the reliability of the final product.
第１図は本発明の半導体チップの整列方法を実施づるた
めに使用する装置の一例を示す構成図、第２図（Ａ）は
上記装置の第１の転写板の構成を示す一部切欠断面図、
同図（Ｂ）は上記第１の転写板と第２転写板を反転させ
て重ね合けだ状態の一部切欠断面図、第３図は従来の整
列方法を説明１゛るための図である。
１０・・・第１の転写板、１０ａ・・・凹所、１１・・
・第２の転写板、１１ａ・・・凹所、１３・・・半導体
チップ、１５・・・測定用移動ヘッド、１５・・・測定
針、 １８・・・制御装置、１９・・・吸着ノズル
台、１９ａ・・・吸着ノズル。
出 願 人FIG. 1 is a configuration diagram showing an example of an apparatus used to carry out the semiconductor chip alignment method of the present invention, and FIG. 2 (A) is a partially cutaway cross-section showing the configuration of the first transfer plate of the above-mentioned apparatus. figure,
The same figure (B) is a partially cutaway sectional view of the first transfer plate and the second transfer plate inverted and overlapping, and FIG. 3 is a diagram for explaining the conventional alignment method. be. 10... First transfer plate, 10a... Recess, 11...
- Second transfer plate, 11a... recess, 13... semiconductor chip, 15... moving head for measurement, 15... measuring needle, 18... control device, 19... suction nozzle Stand, 19a... suction nozzle. applicant
Claims (1)
に半導体チップが供給される工程と、上記第１の転写板
に供給された半導体チップの特性および極性を一列毎に
測定し、その結果を記憶しかつ特定方向の極性および特
性不良の半導体チップを判別する工程と、 この工程で判別された特定方向の極性および特性不良の
半導体チップのみを一列毎に第１の転写板から吸着し搬
送工程途上で前記特性不良の半導体チップのみを除去し
て第２の転写板の対応凹所内に特定方向の極性のみの半
導体チップを一列毎に移す工程と、 前記第１の転写板に残った前記特定極性に対して反対極
性になる半導体チップを当該転写板とともに第２の転写
板上に反転させて重ね合せ残りの半導体チップを第２の
転写板の空所部分に移し第２の転写板上の半導体チップ
を均一に特定方向極性に整列させる工程とを有すること
を特徴とする半導体チップの整列方法。[Claims] A step of supplying a semiconductor chip onto a first transfer plate having a plurality of vertically and horizontally aligned recesses, characteristics of the semiconductor chip supplied to the first transfer plate, and A process of measuring the polarity for each row, storing the results, and identifying semiconductor chips with polarity in a specific direction and defective characteristics, and measuring only semiconductor chips with polarity in a specific direction and defective characteristics determined in this step in each row. a step of adsorbing semiconductor chips from a first transfer plate, removing only the semiconductor chips with defective characteristics during the conveyance process, and transferring semiconductor chips having only polarity in a specific direction one row at a time into corresponding recesses of a second transfer plate; The semiconductor chips remaining on the first transfer plate, which have a polarity opposite to the specific polarity, are inverted and stacked together with the transfer plate on a second transfer plate, and the remaining semiconductor chips are transferred to the empty space on the second transfer plate. 1. A method for aligning semiconductor chips, comprising the step of transferring the semiconductor chips to a designated portion and uniformly aligning the semiconductor chips on a second transfer plate in a specific polarity direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12156384A JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12156384A JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS611036A true JPS611036A (en) | 1986-01-07 |
| JPH02854B2 JPH02854B2 (en) | 1990-01-09 |
Family
ID=14814328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12156384A Granted JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS611036A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02131118U (en) * | 1989-03-31 | 1990-10-31 | ||
| JP2022104810A (en) * | 2020-12-29 | 2022-07-11 | セメス株式会社 | Semiconductor package transfer method, semiconductor package transfer module, and semiconductor package cutting, and sorting device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51148375A (en) * | 1975-06-14 | 1976-12-20 | Fujitsu Ltd | Mesuring method of specific characteristics of semicondutor element |
| JPS5439576A (en) * | 1977-09-02 | 1979-03-27 | Nec Corp | Inspection method for semiconductor device |
-
1984
- 1984-06-13 JP JP12156384A patent/JPS611036A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51148375A (en) * | 1975-06-14 | 1976-12-20 | Fujitsu Ltd | Mesuring method of specific characteristics of semicondutor element |
| JPS5439576A (en) * | 1977-09-02 | 1979-03-27 | Nec Corp | Inspection method for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02131118U (en) * | 1989-03-31 | 1990-10-31 | ||
| JP2022104810A (en) * | 2020-12-29 | 2022-07-11 | セメス株式会社 | Semiconductor package transfer method, semiconductor package transfer module, and semiconductor package cutting, and sorting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02854B2 (en) | 1990-01-09 |
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