JPS61102752A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To alleviate the difference in steps of an interlayer film, by making a first deposited insulating film to remain at the stepped part,forming a gentle curve on a base insulating film, forming a second deposited insulating film on the curve, thereby obtaining the interlayer film. CONSTITUTION:On a semiconductor substrate 1, a base insulating film 2 is formed. Then Al is deposited and a conducting film pattern 3 is formed. Thereafter, a first deposited insulating film 4 is deposited on the entire surface to the same thickness as that of the conducting film. Then the entire surface is etched until the depth the surface of the conducting film pattern 3 is exposed and the surface of the base insulating film 2 is thinly scraped. At this time, a remaining part 4a of etched first deposited insulating film 4 remains on each side surface of a stepped part 3a of the conducting film pattern 3. The remaining part 4a of etching is connected to a smooth curved surface 2a that is obtained by scraping the exposed base insulating film 2 at a position lower than the bottom surface of the stepped part 3a. The surface 2a of the exposed base insulating film 2 and the surface of the remaining part 4a of the etched first deposited insulating film form the continued smooth curved surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to multilayer wiring 4? The present invention relates to a semiconductor device in which steps are reduced in an insulating film such as an i fi interlayer film, and a method for manufacturing the same.

[Technical Background of the Invention] In an 8-integration semiconductor device having a multilayer wiring structure, it is necessary that the wiring and insulating film of each layer be as flat as possible. A growing number of methods have been developed to planarize interlayer dielectrics. Among these known methods, the resist etch-back method is known as a relatively simple and highly useful method.

FIG. 4(a) to FIG. 4(C) are cross-sectional views showing the main steps of a known resist etch-back method.

In this method, first, as shown in FIG. 4(a), after selectively opening a base insulating film 2 (silicon oxide film) formed on the surface of a silicon semiconductor base 1, an i !9N film pattern 3 is formed, and the conductor m11
A primary deposited insulation pattern 4 is formed on the two patterns 3 by, for example, a plasma CVD method. After forming a resist layer 5 whose coated surface is flattened on the stepped insulating film 4, the resist layer 5 and the insulating film 4 are separated as shown in FIG. 4(b). The surface of the secondary deposited insulating film 4 is flattened by etching the entire surface of the convex portion, and then a secondary deposited insulating film 6 (primary deposited insulating film 4 and The same material) is deposited to obtain a flat surface, and upper layer wiring is formed on this secondary deposited insulating film 6.

[Problem in the Background Art 1: According to the well-known resist etch-back method described above, it is theoretically possible to form a completely flat interlayer insulating film, but when implementing this method, the following problems occur. There were some problems, and therefore, it was not possible to manufacture 8 quality semiconductor devices at a high yield.

■ In many cases, pinholes p are likely to be generated in the resist layer 5, as shown in FIG. In the state b), a pinhole p2 is also formed on the surface of the primary deposited insulating film 4, so that the primary H1h'' where the pinhole exists + the secondary j
(When the i-product rupture 16 is formed, the secondary deposited insulation Is! 6
A pinhole p3 is also formed as shown in FIG. 4(C), and as a result, a high-quality interlayer insulation 19 cannot be formed.

- Next 11 (the film quality is different in the flat part of the conductive Ti film pattern and the stepped part 11, etc.). When etching the entire surface of the pattern, the steps of the conductive film pattern...'
: Abnormal etching occurs in the IQ of 7 in 511. Abnormal etching occurs in the straight A, and a defect in the pinhole filter often occurs in that position. As a result, as shown in Fig. 4 (C),
Similarly, the secondary deposited insulation 896 is also prone to defects such as pinholes.

■ Turn the entire surface to 11 and move the first 11 to Regis 1.
When the 1F+'1 insulating film is exposed at the same time, it will not be planarized unless both are etched at the same etch rate. It is quite difficult to etch different areas at the same etching speed.

[Object of the Invention] An object of the present invention is to solve the aforementioned problems associated with the conventional semiconductor device and its manufacturing method manufactured by the above-mentioned known method, and to provide an improved semiconductor device and its manufacturing method. It is. In particular, it is an object of the present invention to provide an improved semiconductor device and a method for manufacturing such a semiconductor device, which is free from the possibility of reducing steps in the interlayer insulating film or causing defects such as pinholes in the interlayer insulating film. It is to provide.

[Summary of the Invention] A semiconductor device according to the present invention includes a conductive I having a stepped portion.
9 patterns, a base insulating film that forms the base of the step part (b1) and the surface of the part where the conductive film pattern is not present is cut lower than the bottom of the step part, and the side surface of the step part. a primary if(fI!I insulating film that covers only It is characterized in that the lower end of the first stacked bonding film is connected to the shaved surface of the underlying insulating film at a position lower than the bottom surface of the stepped portion with a smooth curved surface.

Further, the manufacturing method of the present invention leaves the primary deposited insulating film deposited on the conductive film pattern on the base insulating film only on the side surface of the stepped portion of the conductive film pattern, and also hollows out the surface of the base insulating film. The method is characterized in that after etching by anisotropic etching, a secondary deposited insulating film is deposited on the entire surface.

According to the method of the present invention, since the secondary insulating film is formed on the surface with reduced steps, the surface of the interlayer insulating film is not completely flat, but is relatively flat. n
is n. Furthermore, according to the method of the present invention, unlike the resist etch-back method, it is possible to form the secondary TRT top insulation without forming a resist layer, so defects such as pinholes caused by the resist layer can be formed in the interlayer insulating film. 1q is a semiconductor device h' which does not have a semiconductor device h'.

[Embodiment 1 of the Invention The method of the present invention and the semiconductor device of the present invention manufactured by this method will be described below with reference to FIGS. 2(a) to 2(C) and FIG. ! An example i will be explained. Note that in FIGS. 1 and 2, the parts indicated by the same reference numerals as in FIG. 4 are the same as the constituent parts of the conventional semiconductor device.

In the method of the present invention, first, a base insulating film 2 (SiO, film) is formed on a semiconductor substrate 1 as shown in FIG. Approximately 1 .mu.Ill of A1 is deposited on the insulating film 2, and a conductive film bow 3 is formed by a conventional wet etching method. Next, a primary deposited insulating film 4 (plasma film) is deposited over the entire surface to a thickness of 1 .mu.II, which is approximately the same as the thickness of the conductive film, using a plasma CVD method or the like.

Next, the surface of ηT1 pattern 3 is exposed and the moon base is $1!
! Anisotropic ↑Ii to the depth where the surface of edge pattern 2 is thinly scraped off
When the entire surface is etched, the state shown in FIG. 2(b) is obtained. In this case, an unetched portion 4a of the primary lit product insulating film 4 remains on the 8I11 surface of the stepped portion 3a of the conductive film pattern 3, and the tail (i.e., the lower end) of the etched remaining portion 48 (FIG. 2) As shown in C), the exposed base insulating film 2 is connected to the shaved surface 2a of the exposed base insulating film 2 at a position lower than the bottom surface of the stepped portion 3a with a smooth curved surface. The surface 2a and the primary deposited insulating film constitute a gently curved surface with four turns. In this way, conductive n9
A primary deposited insulating film 4 is formed on the side surface of each stepped portion 3a of the pattern 3.
Figure 2 (a) shows that the remaining part 4a of 1.
As shown in FIG.
This is because the corners of the ft1 insulating film 4 protrude laterally, resulting in a so-called overhang state, and the tail of the etched portion 4a and the exposed surface 2a on the base insulating film form a continuous, clean curved surface. This is because the bottom corners are the least likely to be etched. The etching conditions in this example were CF a 20cc/w
in, I-1210cc/sin, power 320
W, the pressure was 1.3 Pa, and the time was 20 minutes.

As shown in FIG. 2(b), each step portion 3 of the conductive film pattern 3
An etched portion 4 of the primary deposited insulating film 4 is left on the side wall of a.
After performing etching on the entire surface so that the portion a remains, a secondary deposited insulating film 6 made of the same or different material as the primary deposited insulating film 4 is deposited on the entire surface as shown in FIG. I can get it. In particular, although low-temperature plasma simulators have recently been increasingly used as secondary m b'+ insulating films, the deposition rate of low-temperature plasma films tends to depend on the quality of the underlying film. Therefore, the step portion is lft lower than the underlying insulating film.
Compared to the case of A1, which has a faster deposition rate, the effect of improving the step coverage of the present invention is also produced by having the same film quality and the same m-accumulation rate as the underlying insulating film.

In the semiconductor device of the present invention obtained by the above-described manufacturing method, the steps of T, L, and the secondary deposited insulating film are alleviated, and since the resist film is not formed before the entire surface etching, the steps are generated in the resist film. There is no risk of being adversely affected by pinholes.

FIG. 3 shows a second QT in the semiconductor device of the present invention shown in FIG.
This figure shows a semiconductor device with a two-layer wiring structure in which an iF5 pattern 7 and a padding layer 8 are formed thereon, and the secondary insulation film in the semiconductor device having the structure shown in FIG. 1 is selectively opened. After drilling and forming the through hole, the second 8
An X conductive film pattern 7 is formed on the soil of the secondary Iff layer 6, and a plasma silicon nitride pattern 8 as a passivation film is deposited on the L of the second conductive film 7.

The method of the present invention is particularly suitable for forming semiconductor devices with multilayer wiring of two or more layers, and although it cannot be said to be completely flat, the method of the present invention can improve step coverage and improve step coverage. A semiconductor device having wiring and an interlayer insulating film can be formed.

In addition, in the above embodiments, the case where AI is used as the conductive film pattern, that is, the wiring and electrodes is minimized, but it can also be used to manufacture semiconductor devices with polycrystalline silicon as a resistor or semiconductor devices with a stacked structure using polycrystalline silicon. It goes without saying that the present invention can be applied.

[Effects of the Invention] As described above, in the method of the present invention, the primary deposited insulating film is left in the stepped portion, a gently curved surface is formed on the base insulating film, and a secondary insulating film (6 insulating films is formed) is formed on the base insulating film. Since the method of the present invention does not form a resist film, the negative effects of pinholes etc. generated in the resist film are minimized. There is no risk of the film appearing on the interlayer, and therefore the quality and manufacturing yield of semiconductor devices can be improved.

On the other hand, since the semiconductor device of the present invention is free from defects and has an upper insulating film with better step coverage than conventional semiconductor devices, it has higher reliability than semiconductor devices manufactured by conventional methods. .

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of the semiconductor device of the present invention;
2(a) to 2(C) are cross-sectional views for explaining the method of the present invention, FIG. 3 is a cross-sectional view of another embodiment of the semiconductor device of the present invention, and FIG. 4(a) 4C to 4C are cross-sectional views for explaining a conventionally known method. 1... Semiconductor substrate, 2... Base insulating film, 3...
・Conductive film pattern, 4...-order 111 product insulating film,
5... Resist presence, 6... Secondary deposited insulating film, 7
...Second conductive film pattern, 8...Passivation film. Patent applicant: Toshiba Corporation @1 Figure 2

Claims (1)

[Scope of Claims] 1. A conductive film pattern having a stepped portion, which constitutes the base of the stepped portion, and the surface of the portion where the conductive film pattern does not exist is scraped below the bottom surface of the stepped portion. A base insulating film, a primary deposited insulating film covering only the side surfaces of the stepped portion, and a secondary deposit covering the surface of the base insulating film, the surface of the conductive film pattern, and the surface of the primary deposited insulating film. an insulating film, the lower end of the primary deposited film is connected to the shaved surface of the base insulating film around the stepped portion with a smooth curved surface. 2. A conductive film pattern having a step portion, a base insulating film that forms the base of the step portion, and the surface of the portion where the conductive film pattern does not exist is scraped below the bottom surface of the step portion; A primary deposited insulating film that covers only the side surfaces of the stepped portion, and a secondary deposited insulating film that covers the surface of the base insulating film, the surface of the conductive film pattern, and the surface of the primary deposited insulating film. , a method for manufacturing a semiconductor device having a structure in which a lower end of the primary deposited film is connected to a shaved surface of the base insulating film around the stepped portion with a smooth curved surface, the base insulating film forming a predetermined conductive film pattern on the base insulating film after selectively opening the base insulating film, depositing the primary deposited insulating film on the conductive film pattern, and depositing the primary deposited film only on the side surface of the stepped portion. Almost all of the primary deposited insulating film and the surface of the base insulating film are anisotropically separated until the surface of the base insulating film in the portion where the conductive film pattern is not present is lower than the bottom surface of the stepped portion while leaving the insulating film. and a step of depositing a secondary deposited insulating film on the entire surface consisting of the primary deposited insulating film remaining on the side surface of the stepped portion, the conductive film pattern, and the base insulating film. Production method.