JPS61102067A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a shallow junction by making a gate electrode to bite and arranging it so that each surface of source and drain regions is positioned at sections upper than the surface of a channel forming region. CONSTITUTION:A gate electrode 4 is made to bite and disposed between source- drain regions 2, 3 shaped into a substrate 1 so that several surface of the regions 2, 3 is positioned at sections upper than the surface of a channel forming region. A gate insulating film 5 is interposed among the regions 2, 3 and the electrode 4 so that one parts of the regions 2, 3 are coated with end sections. According to such constitution, the effective junction depth of the regions 2, 3 is shallowed, thus reducing a short channel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to miniaturization of transistors (MOS).

[Conventional technology]

A schematic cross-sectional configuration of each individual conventional MOS transistor of this type is shown in FIGS. 3 to 5. That is, FIG. 3 shows the case of an n-channel MOS transistor, l is a p-type semiconductor substrate, and 2a , 3a is a source having n-type conductivity that is diffused on one surface of this p-type semiconductor substrate;
A drain region 4a is formed on these sources and a channel forming region between the drain regions 2a and 3a.
A gate electrode is formed through a thin gate insulating film 5a, and 10 is a thick insulating film for isolation between elements. Also, Fig. 4 shows the case of a p-channel MO5 transistor, where 6 is an n-type semiconductor substrate, and ? a and 8a are source and drain regions having p-type conductivity which are diffused on the 6th surface of this n-type semiconductor substrate, and furthermore, in FIG.
In the case where both channel and n-channel MO9) transistors are included, 9 is a p or n well, 11 is an n or p type semiconductor substrate, 12a and 13a are p or n wells with n or p type conductivity on the 8 side. source with.

14a and 15a are source and drain regions having p- or n-type conductivity on the n- or p-type semiconductor substrate 11 side.

However, in each of these conventional configurations, as is well known, by applying a high positive voltage to each gate electrode 4a, the surface of the channel region under the gate insulating film 5a is brought into an inverted state. In the example of FIG. 3, this inversion region is a source of P or n type conductivity,
Drain region 2a.

In the example of FIG. 4, the junction of source and drain regions 7a and 8a with p-type conductivity, and in the example of FIG. 5, the junction of source and drain regions 12a with n- or p-type conductivity , 13a, and source and drain regions +4a having p or n type conductivity.
, 15a are connected to each other to form a conductive channel, thereby rendering each MOS transistor conductive.

[Problem that the invention seeks to solve]

Therefore, in the case of the MOS transistor in the conventional device, it is necessary to configure the junction depth of the source and drain regions to be deeper, and for this reason, when looking at the characteristics of the element itself, short channel effects etc. The problem was that it was difficult to

This invention was made to solve these conventional problems, and provides a semiconductor device in which the source and drain regions are formed by shallow junctions with low resistance, and which can be miniaturized with less short channel effect. The purpose is to obtain.

[Means for solving problems]

In order to achieve the above object, a semiconductor device according to the present invention provides a semiconductor device in which, in the configuration of a MOS transistor, the source and drain regions are formed such that the surfaces of the source and drain regions are above the surface of the channel forming region. A gate electrode is formed between the gate electrode and the gate electrode with a gate insulating film interposed therebetween.

[For production]

Therefore, in the present invention, the gate electrode is inserted between the source and drain regions and placed through the gate insulating film so that the surfaces of the source and train regions are above the surface of the channel forming region. By this,
When viewed as an element itself, it becomes possible to effectively form shallow junctions, have less short channel effects, and easily obtain miniaturized semiconductor devices.

〔Example〕

Hereinafter, the first embodiment of the semiconductor device according to the present invention will be described.
This will be explained in detail with reference to the figures and FIG.

FIG. 1 shows the present invention in a MOS corresponding to the conventional example shown in FIG. 3.
) shows an embodiment in which the present invention is applied to a transistor, and FIG.
FIG. 3 is a corresponding diagram showing another embodiment when applied to a transistor (OS).

In the apparatus of the embodiment shown in FIGS. 1 and 2, the same reference numerals as in the conventional apparatus shown in FIGS. 3 and 5 indicate the same or corresponding parts.

First, in the device of the embodiment shown in FIG. 1, the surfaces of the source and drain regions 2 and 3 are located above the surface of the channel forming region, and the gate electrode is located between these source and drain regions 2 and 3. 4, and these source and drain regions 2.
A gate insulating film 5 is interposed between the gate electrode 3 and the gate electrode 4 so that both ends of the gate insulating film 5 also cover part of each of the source and drain regions 2 and 3.

Also, in the embodiment device of FIG. 2, the source and drain regions 12.13 and 14.1
The gate electrode 4 is positioned between these source and drain regions 12, 13 and 14.15 so that each surface of the source and drain regions 5 is above the surface of the respective channel forming region. Source and drain regions 12.13 and 14.15 and each gate electrode 4
．． 4, a gate insulating film 5.5 is interposed between each gate insulating film 5.5.

Therefore, in each of these embodiments, the same effect as in the conventional structure is achieved, but in each embodiment, when viewed from the gate electrode 4 side, the source and drain regions 2 in FIG. .3, and in FIG. 2, the effective junction depths of the source and drain regions 12.13 and 14.15, respectively, are shallower, reducing the short channel effect, and on the other hand, reducing the actual junction depth. Since the junction can be formed substantially as deep as in the conventional example, it is possible to sufficiently avoid high resistance caused by shallow junctions.

In the embodiment shown in FIG. 1, n-channel M
I mentioned the O5 transistor, but the p-channel M
Of course, the present invention can also be applied to an OS transistor, and the same effect can be obtained even if it is applied to a semiconductor region formed on a semiconductor substrate or other insulating substrate instead of a semiconductor substrate.

Effects can be obtained.

〔Effect of the invention〕

As detailed above, according to the present invention, in a MOS transistor, a gate electrode is inserted between the source and drain regions so that the surfaces of the source and drain regions are above the surface of the channel forming region. Since this is arranged through a gate insulating film, an effectively shallow junction can be obtained, reducing the short channel effect, and the actual junction depth can be maintained at a predetermined depth, resulting in low resistance. In addition to being able to reduce the number of electrodes, it also prevents electrode penetration, and has the advantage of being relatively simple in structure and easy to implement.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing the essential structure of a MOS transistor to which different embodiments of the device of the present invention are applied, and FIGS. 1A and 1B are cross-sectional views each showing a schematic configuration of a MOS transistor. 1.8.11...Semiconductor substrate, 2, 3, 7, 8, 1
2,13,14.15...source, drain region,
4...Gate electrode, 5...Gate insulating film. Agent Masu Oiwa Yuran Figure 1 Figure 2 Figure 3 Otsua Figure 4 Figure 5

Claims (1)

[Claims] A gate insulating film is formed over at least a semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type diffused within the surface of the semiconductor substrate, and a channel formation region between these source and drain regions. A gate insulating film is formed between the source and drain regions so that the surfaces of the source and drain regions are above the surface of the channel formation region. 1. A semiconductor device characterized in that a gate electrode is formed so as to be positioned so as to bite through the gate electrode.