JPS61101953U - - Google Patents

Info

Publication number
JPS61101953U
JPS61101953U JP18758984U JP18758984U JPS61101953U JP S61101953 U JPS61101953 U JP S61101953U JP 18758984 U JP18758984 U JP 18758984U JP 18758984 U JP18758984 U JP 18758984U JP S61101953 U JPS61101953 U JP S61101953U
Authority
JP
Japan
Prior art keywords
display section
chip
display panel
mos
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18758984U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18758984U priority Critical patent/JPS61101953U/ja
Publication of JPS61101953U publication Critical patent/JPS61101953U/ja
Pending legal-status Critical Current

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Landscapes

  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示す蛍光表示パネル
の平面略図、第2図は同蛍光表示パネルの側面略
図、第3図は第1図の表示部の断面略図、第4図
は本考案の実施例における蛍光表示パネル用基板
を示す部分斜視図、第5図はマルチブレツクスマ
トリクス駆動方式を示す概念図、第6図はアクテ
イブマトリクス駆動方式を示す概念図、第7図は
アクテイブマトリクス駆動方式の従来例における
画素構成を示す略図、第8図は同従来例における
シリコンチツプ上の回路構成略図である。なお、
各図において、 1……表示部、2……MOS ICチツプ、3
……石英基板、4…カバーガラス、5……結晶化
ガラス、6……外部端子、31……スイツチング
素子、32……キヤパシタ、33……パツシベー
シヨン層、34……配線層、35……半導体層、
36……誘電体層、38……蛍光体層、41……
ゲート電極配線群、42……ソース電極配線群、
43……アルミニウム細線、44……外部端子用
電極配線、51……マルチプレツクス駆動方式に
おける表示部、52……行駆動回路、53……列
駆動回路、54……制御回路、55……外部回路
、61……画素、62……FET、63……ゲー
ト電極配線、64……ソース電極配線、71……
電荷蓄積用トランジスタ、72……発光制御用ト
ランジスタ、81……画素アレイ、82……Xレ
ジスタ、83……Yレジスタ、84……ドライバ
である。
Fig. 1 is a schematic plan view of a fluorescent display panel showing an embodiment of the present invention, Fig. 2 is a schematic side view of the fluorescent display panel, Fig. 3 is a schematic cross-sectional view of the display section of Fig. 1, and Fig. 4 is a schematic plan view of the fluorescent display panel according to the present invention. FIG. 5 is a conceptual diagram showing a multiplex matrix driving method, FIG. 6 is a conceptual diagram showing an active matrix driving method, and FIG. 7 is an active matrix driving method. FIG. 8 is a schematic diagram showing a pixel configuration in a conventional example of the system. FIG. 8 is a schematic diagram of a circuit configuration on a silicon chip in the conventional example. In addition,
In each figure, 1...display section, 2...MOS IC chip, 3
... Quartz substrate, 4 ... Cover glass, 5 ... Crystallized glass, 6 ... External terminal, 31 ... Switching element, 32 ... Capacitor, 33 ... Passivation layer, 34 ... Wiring layer, 35 ... Semiconductor layer,
36...dielectric layer, 38...phosphor layer, 41...
Gate electrode wiring group, 42...source electrode wiring group,
43...Aluminum thin wire, 44...External terminal electrode wiring, 51...Display section in multiplex drive system, 52...Row drive circuit, 53...Column drive circuit, 54...Control circuit, 55...External Circuit, 61... Pixel, 62... FET, 63... Gate electrode wiring, 64... Source electrode wiring, 71...
Charge storage transistor, 72...transistor for light emission control, 81...pixel array, 82...X register, 83...Y register, 84...driver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マトリクス状に配列された蛍光体層を有する表
示部と、該表示部を動作させる周辺回路部とが同
一基板上に形成された構造を有する蛍光表示パネ
ルにおいて、基板として石英を用いることと、前
記表示部が多結晶シリコンを半導体材料とするマ
トリクス状のTFT(Thin Film Tr
ansistor)により形成されたスイツチン
グ素子と該素子に接続された蛍光体層から成るこ
とと、前記周辺回路部が単結晶シリコンから成る
MOS(Metal Oxide Semico
nductor)トランジスタから形成されたI
Cチツプから成ることおよび石英から成るカバー
ガラスを用い、結晶化ガラスによつて真空封止す
ることにより、前記表示部およびチツプを同じ真
空容器内に設けたことを特徴とする蛍光表示パネ
ル。
In a fluorescent display panel having a structure in which a display section having a phosphor layer arranged in a matrix and a peripheral circuit section for operating the display section are formed on the same substrate, quartz is used as the substrate; The display part is a matrix TFT (Thin Film Tr) whose semiconductor material is polycrystalline silicon.
MOS (Metal Oxide Semiconductor) consisting of a switching element formed by an auxiliary transistor and a phosphor layer connected to the element, and the peripheral circuit section being a MOS (Metal Oxide Semiconductor
I formed from transistors
1. A fluorescent display panel comprising a C chip, a cover glass made of quartz, and vacuum sealing with crystallized glass, so that the display section and the chip are provided in the same vacuum container.
JP18758984U 1984-12-11 1984-12-11 Pending JPS61101953U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18758984U JPS61101953U (en) 1984-12-11 1984-12-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18758984U JPS61101953U (en) 1984-12-11 1984-12-11

Publications (1)

Publication Number Publication Date
JPS61101953U true JPS61101953U (en) 1986-06-28

Family

ID=30745051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18758984U Pending JPS61101953U (en) 1984-12-11 1984-12-11

Country Status (1)

Country Link
JP (1) JPS61101953U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482437A (en) * 1987-09-24 1989-03-28 Nec Corp Fluorescent display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482437A (en) * 1987-09-24 1989-03-28 Nec Corp Fluorescent display device

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