JPS61100870U - - Google Patents

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Publication number
JPS61100870U
JPS61100870U JP18712984U JP18712984U JPS61100870U JP S61100870 U JPS61100870 U JP S61100870U JP 18712984 U JP18712984 U JP 18712984U JP 18712984 U JP18712984 U JP 18712984U JP S61100870 U JPS61100870 U JP S61100870U
Authority
JP
Japan
Prior art keywords
peripheral circuit
semiconductor
display section
section
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18712984U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18712984U priority Critical patent/JPS61100870U/ja
Publication of JPS61100870U publication Critical patent/JPS61100870U/ja
Pending legal-status Critical Current

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  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す螢光表示パネル
の平面理図、第2図は同螢光表示パネルの側面略
図、第3図は第1図の表示部の断面略図、第4図
は本考案の実施例における螢光表示パネル用基板
を示す部分斜視図、第5図はマルチプレツクスマ
トリクス駆動方式を示す概念図、第6図はアクテ
イブマトリクス駆動方式を示す断念図、第7図は
アクテイブマトリクス駆動方式の従来例における
画素構成を示す略図、第8図は同従来例における
シリコンチツプ上の回路構成略図である。 なお、各図において、1……表示部、2……M
OS ICチツプ、3……フオルステライト基板
、4……カバーガラス、5……低隔点ガラス、6
……外部端子、31……スイツチング素子、32
……キヤパシタ、33……パツシベーシヨン層、
34……配線層、35……半導体層、36……誘
電体層、38……螢光体層、41……ゲート電極
配線群、42……ソース電極配線群、43……ア
ルミニウム細線、44……外部端子用電極配線、
51……マルチプレツクス駆動方式における表示
部、52……行駆動回路、53……列駆動解路、
54……制御回路、55……外部回路、61……
画素、62……FET、63……ゲート電極配線
、64……ソース電極配線、71……電荷蓄積用
トランジスタ、72……発光制御用トランジスタ
、81……画素アレイ、82……Xレジスタ、8
3……Yレジスタ、84……ドライバである。
Fig. 1 is a plan view of a fluorescent display panel showing an embodiment of the present invention, Fig. 2 is a schematic side view of the same fluorescent display panel, Fig. 3 is a schematic cross-sectional view of the display section of Fig. 1, and Fig. 4. 1 is a partial perspective view showing a substrate for a fluorescent display panel in an embodiment of the present invention, FIG. 5 is a conceptual diagram showing a multiplex matrix driving method, FIG. 6 is a cutaway diagram showing an active matrix driving method, and FIG. FIG. 8 is a schematic diagram showing a pixel configuration in a conventional example of an active matrix drive system. FIG. 8 is a schematic diagram of a circuit configuration on a silicon chip in the conventional example. In each figure, 1...display section, 2...M
OS IC chip, 3... Forsterite substrate, 4... Cover glass, 5... Low separation point glass, 6
...External terminal, 31...Switching element, 32
...capacity, 33...passivation layer,
34... Wiring layer, 35... Semiconductor layer, 36... Dielectric layer, 38... Fluorescent layer, 41... Gate electrode wiring group, 42... Source electrode wiring group, 43... Aluminum thin wire, 44 ...Electrode wiring for external terminals,
51...Display section in multiplex drive system, 52...Row drive circuit, 53...Column drive circuit,
54...Control circuit, 55...External circuit, 61...
Pixel, 62... FET, 63... Gate electrode wiring, 64... Source electrode wiring, 71... Charge storage transistor, 72... Light emission control transistor, 81... Pixel array, 82... X register, 8
3...Y register, 84...driver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マトリクス状に配列された螢光体層を有する表
示部と、該表示部を動作させる周辺回路部とが、
同一基板上に形成された構造を有する螢光表示パ
ネルにおいて、基板としてフオルステライトを用
いることと、前記表示部が多結晶シリコンを半導
体材料とするマトリクス状のTFT(Thin
Film Transistor)により形成さ
れたスイツチング素子と該素子に接続された螢光
体層から成ることと、前記周辺回路部が単結晶シ
リコンから成るMOS(Metal Oxide
Semiconductor)トランジスタか
ら形成されたICチツプから成ること、および該
チツプが前記表示部と同じ真空容器内に設けられ
たことを特徴とする螢光表示パネル。
A display section having a phosphor layer arranged in a matrix, and a peripheral circuit section for operating the display section,
In a fluorescent display panel having a structure formed on the same substrate, forsterite is used as the substrate, and the display portion is formed of a matrix TFT (Thin Film) using polycrystalline silicon as a semiconductor material.
The peripheral circuit section is composed of a switching element formed by a film transistor (Film Transistor) and a phosphor layer connected to the element, and the peripheral circuit part is made of a MOS (Metal Oxide) made of single crystal silicon.
1. A fluorescent display panel comprising an IC chip formed from a Semiconductor (Semiconductor) transistor, and the chip is provided in the same vacuum container as the display section.
JP18712984U 1984-12-10 1984-12-10 Pending JPS61100870U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18712984U JPS61100870U (en) 1984-12-10 1984-12-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18712984U JPS61100870U (en) 1984-12-10 1984-12-10

Publications (1)

Publication Number Publication Date
JPS61100870U true JPS61100870U (en) 1986-06-27

Family

ID=30744594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18712984U Pending JPS61100870U (en) 1984-12-10 1984-12-10

Country Status (1)

Country Link
JP (1) JPS61100870U (en)

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