JPS61101793U - - Google Patents

Info

Publication number
JPS61101793U
JPS61101793U JP18570784U JP18570784U JPS61101793U JP S61101793 U JPS61101793 U JP S61101793U JP 18570784 U JP18570784 U JP 18570784U JP 18570784 U JP18570784 U JP 18570784U JP S61101793 U JPS61101793 U JP S61101793U
Authority
JP
Japan
Prior art keywords
display section
section
fluorescent display
display
phosphor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18570784U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18570784U priority Critical patent/JPS61101793U/ja
Publication of JPS61101793U publication Critical patent/JPS61101793U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示す蛍光表示パネル
の平面略図、第2図は同蛍光表示パネルの側面略
図、第3図は第1図の表示部の断面略図、第4図
は本考案の実施例における蛍光表示パネル用基板
を示す部分斜視図、第5図はマルチプレツクスマ
トリクス駆動方式を示す概念図、第6図はアクテ
イブマトリクス駆動方式を示す概念図、第7図は
アクテイブマトリクス駆動方式の従来例における
画素構成を示す略図、第8図は同従来例における
シリコンチツプ上の回路構成略図である。 なお、各図において、1……表示部、2……M
OS ICチツプ、3……ソーダガラス基板、4
……カバーガラス、5……低融点ガラス、6……
外部端子、31……スイツチング素子、32……
キヤパシタ、33……パツシベーシヨン層、34
……配線層、35……半導体層、36……誘電体
層、38……蛍光体層、41……ゲート電極配線
群、42……ソース電極配線群、43……アルミ
ニウム細線、44……外部端子用電極配線、51
……マルチプレツクス駆動方式における表示部、
52……行駆動回路、53……列駆動回路、54
……制御回路、55……外部回路、61……画素
、62……FET、63……ゲート電極配線、6
4……ソース電極配線、71……電荷蓄積用トラ
ンジスタ、72……発光制御用トランジスタ、8
1……画素アレイ、82……Xレジスタ、83…
…Yレジスタ、84……ドライバである。
Fig. 1 is a schematic plan view of a fluorescent display panel showing an embodiment of the present invention, Fig. 2 is a schematic side view of the fluorescent display panel, Fig. 3 is a schematic cross-sectional view of the display section of Fig. 1, and Fig. 4 is a schematic plan view of the fluorescent display panel according to the present invention. FIG. 5 is a conceptual diagram showing a multiplex matrix driving method, FIG. 6 is a conceptual diagram showing an active matrix driving method, and FIG. 7 is an active matrix driving method. FIG. 8 is a schematic diagram showing a pixel configuration in a conventional example. FIG. 8 is a schematic diagram of a circuit configuration on a silicon chip in the conventional example. In each figure, 1...display section, 2...M
OS IC chip, 3...soda glass substrate, 4
...Cover glass, 5...Low melting point glass, 6...
External terminal, 31... Switching element, 32...
Capacitor, 33... Passivation layer, 34
... Wiring layer, 35 ... Semiconductor layer, 36 ... Dielectric layer, 38 ... Phosphor layer, 41 ... Gate electrode wiring group, 42 ... Source electrode wiring group, 43 ... Aluminum thin wire, 44 ... Electrode wiring for external terminals, 51
...Display section in multiplex drive system,
52...Row drive circuit, 53...Column drive circuit, 54
... Control circuit, 55 ... External circuit, 61 ... Pixel, 62 ... FET, 63 ... Gate electrode wiring, 6
4... Source electrode wiring, 71... Charge storage transistor, 72... Light emission control transistor, 8
1...Pixel array, 82...X register, 83...
...Y register, 84...driver.

Claims (1)

【実用新案登録請求の範囲】 (1) マトリクス状に配列された蛍光体層を有す
る表示部と、該表示部を動作させる周辺回路部と
が、同一基板上に形成された構造を有する蛍光表
示パネルにおいて、前記表示部がマトリクス状の
TFT(Thin Film Transist
or)により形成されたスイツチング素子と該素
子に接続された蛍光体層から成ることと、前記周
辺回路部が単結晶シリコンから成るMOS(Me
―tal Oxide Semiconduct
or)トランジスタから形成されたICチツプか
ら成ること、および該チツプが前記表示部と同じ
真空容器内に設けられたことを特徴とする蛍光表
示パネル。 (2) 前記TFTの半導体材料がテルル,セレン
化カドミウム、または硫化カドミウムから選ばれ
た材料からなる特徴とする実用新案登録請求の範
囲第(1)項記載の蛍光表示パネル。
[Claims for Utility Model Registration] (1) A fluorescent display having a structure in which a display section having a phosphor layer arranged in a matrix and a peripheral circuit section for operating the display section are formed on the same substrate. In the panel, the display section is made of a matrix TFT (Thin Film Transistor).
or) and a phosphor layer connected to the switching element, and the peripheral circuit section is composed of a MOS (Me
-tal Oxide Semiconductor
or) A fluorescent display panel comprising an IC chip formed from a transistor, and the chip is provided in the same vacuum container as the display section. (2) The fluorescent display panel according to claim 1, wherein the semiconductor material of the TFT is selected from tellurium, cadmium selenide, or cadmium sulfide.
JP18570784U 1984-12-07 1984-12-07 Pending JPS61101793U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18570784U JPS61101793U (en) 1984-12-07 1984-12-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18570784U JPS61101793U (en) 1984-12-07 1984-12-07

Publications (1)

Publication Number Publication Date
JPS61101793U true JPS61101793U (en) 1986-06-28

Family

ID=30743173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18570784U Pending JPS61101793U (en) 1984-12-07 1984-12-07

Country Status (1)

Country Link
JP (1) JPS61101793U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5496357A (en) * 1977-11-14 1979-07-30 Wagner Electric Corp Integration indicator and method of producing same
JPS5688243A (en) * 1979-12-20 1981-07-17 Ise Electronics Corp Luminescent display tube
JPS59119658A (en) * 1982-12-24 1984-07-10 Nec Corp Fluorescent character display tube

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5496357A (en) * 1977-11-14 1979-07-30 Wagner Electric Corp Integration indicator and method of producing same
JPS5688243A (en) * 1979-12-20 1981-07-17 Ise Electronics Corp Luminescent display tube
JPS59119658A (en) * 1982-12-24 1984-07-10 Nec Corp Fluorescent character display tube

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