JPS61101952U - - Google Patents

Info

Publication number
JPS61101952U
JPS61101952U JP18758884U JP18758884U JPS61101952U JP S61101952 U JPS61101952 U JP S61101952U JP 18758884 U JP18758884 U JP 18758884U JP 18758884 U JP18758884 U JP 18758884U JP S61101952 U JPS61101952 U JP S61101952U
Authority
JP
Japan
Prior art keywords
display section
display panel
section
semiconductor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18758884U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18758884U priority Critical patent/JPS61101952U/ja
Publication of JPS61101952U publication Critical patent/JPS61101952U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す蛍光表示パネル
の平面略図、第2図は同蛍光表示パネルの側面略
図、第3図は第1図の表示部の断面略図、第4図
は本考案の実施例における蛍光表示パネル用基板
を示す部分斜視図、第5図はマルチプレツクスマ
トリクス駆動方式を示す概念図、第6図はアクテ
イブマトリクス駆動方式を示す概念図、第7図は
アクテイブマトリクス駆動方式の従来例における
画素構成を示す略図、第8図は同従来例における
シリコンチツプ上の回路構成略図である。 なお、各図において、1……表示部、2……M
OS ICチツプ、3……ホウケイ酸ガラス基板
、4……カバーガラス、5……低融点ガラス、6
……外部端子、31……スイツチング素子、32
……キヤパシタ、33……パツシベーシヨン層、
34……配線層、35……半導体層、36……誘
電体層、38……蛍光体層、41……ゲート電極
配線群、42……ソース電極配線群、43……ア
ルミニウム細線、44……外部端子用電極配線、
51……マルチプレツクス駆動方式における表示
部、52……行駆動回路、53……列駆動回路、
54……制御回路、55……外部回路、61……
画素、62……FET、63……ゲート電極配線
、64……ソース電極配線、71……電荷蓄積用
トランジスタ、72……発光制御用トランジスタ
、81……画素アレイ、82……Xレジスタ、8
3……Yレジスタ、84……ドライバである。
Fig. 1 is a schematic plan view of a fluorescent display panel showing an embodiment of the present invention, Fig. 2 is a schematic side view of the fluorescent display panel, Fig. 3 is a schematic cross-sectional view of the display section of Fig. 1, and Fig. 4 is a schematic plan view of the fluorescent display panel according to the present invention. FIG. 5 is a conceptual diagram showing a multiplex matrix driving method, FIG. 6 is a conceptual diagram showing an active matrix driving method, and FIG. 7 is an active matrix driving method. FIG. 8 is a schematic diagram showing a pixel configuration in a conventional example. FIG. 8 is a schematic diagram of a circuit configuration on a silicon chip in the conventional example. In each figure, 1...display section, 2...M
OS IC chip, 3...borosilicate glass substrate, 4... cover glass, 5... low melting point glass, 6
...External terminal, 31...Switching element, 32
...capacity, 33...passivation layer,
34... Wiring layer, 35... Semiconductor layer, 36... Dielectric layer, 38... Fluorescent layer, 41... Gate electrode wiring group, 42... Source electrode wiring group, 43... Aluminum thin wire, 44... ...Electrode wiring for external terminals,
51...Display unit in multiplex drive system, 52...Row drive circuit, 53...Column drive circuit,
54...Control circuit, 55...External circuit, 61...
Pixel, 62... FET, 63... Gate electrode wiring, 64... Source electrode wiring, 71... Charge storage transistor, 72... Light emission control transistor, 81... Pixel array, 82... X register, 8
3...Y register, 84...driver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マトリクス状に配列された蛍光体層を有する表
示部と、該表示部を動作させる周辺回路部とが同
一基板上に形成された構造を有する蛍光表示パネ
ルにおいて、基板としてホウケイ酸ガラスを用い
ることと、前記表示部が多結晶シリコンを半導体
材料とするマトリクス状のTFT(Thin F
ilm Transistor)により形成され
たスイツチング素子と該素子に接続された蛍光体
層から成ることと、前記周辺回路部が単結晶シリ
コンからなるMOS(Metal Oxide
Semiconductor)トランジスタから
形成されたICチツプから成ること、およびホウ
ケイ酸ガラスから成るカバーガラスを用いて真空
封止することにより、前記表示部およびチツプを
同じ真空容器内に設けたことを特徴とする蛍光表
示パネル。
In a fluorescent display panel having a structure in which a display section having a phosphor layer arranged in a matrix and a peripheral circuit section for operating the display section are formed on the same substrate, borosilicate glass may be used as the substrate. , the display section is a matrix TFT (Thin F
ilm transistor) and a phosphor layer connected to the element, and the peripheral circuit section is composed of a MOS (Metal Oxide) made of single crystal silicon.
A fluorescent lamp comprising an IC chip formed from a semiconductor (Semiconductor) transistor, and the display section and the chip are provided in the same vacuum container by vacuum sealing using a cover glass made of borosilicate glass. display panel.
JP18758884U 1984-12-11 1984-12-11 Pending JPS61101952U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18758884U JPS61101952U (en) 1984-12-11 1984-12-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18758884U JPS61101952U (en) 1984-12-11 1984-12-11

Publications (1)

Publication Number Publication Date
JPS61101952U true JPS61101952U (en) 1986-06-28

Family

ID=30745050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18758884U Pending JPS61101952U (en) 1984-12-11 1984-12-11

Country Status (1)

Country Link
JP (1) JPS61101952U (en)

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