JPS62151523U - - Google Patents
Info
- Publication number
- JPS62151523U JPS62151523U JP3834886U JP3834886U JPS62151523U JP S62151523 U JPS62151523 U JP S62151523U JP 3834886 U JP3834886 U JP 3834886U JP 3834886 U JP3834886 U JP 3834886U JP S62151523 U JPS62151523 U JP S62151523U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- liquid crystal
- gate
- lines
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims 4
- 239000010409 thin film Substances 0.000 claims 2
- 230000007547 defect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は第１図の部分的拡大図、第３図と第４図とは
従来技術の説明図である。
１１…第１の基板、１２…第２の基板、１３…
ドレイン線、１４…補正用配線、１６…絶縁層、
２０…ゲート線、２２…半導体層、ａ１…補正用
端子。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a partially enlarged view of FIG. 1, and FIGS. 3 and 4 are illustrations of the prior art. 11...first substrate, 12...second substrate, 13...
Drain line, 14... Correction wiring, 16... Insulating layer,
20...Gate line, 22...Semiconductor layer, a1 ...Correction terminal.
Claims (1)
交する複数本のドレイン線を有すると共に、両線
の各交点領域にそれぞれ薄膜トランジスタ及び該
薄膜トランジスタに接続された透明画素電極を有
する第一の基板と、該第一の基板と対向し共通電
極を有する第二の基板と、これら基板間に設けら
れた液晶と、前記ゲート線及びドレイン線の駆動
回路とを具える液晶表示装置において、前記第一
の基板の表示領域内で絶縁層を介し前記ゲート線
又はドレイン線上に前記ゲート線又はドレイン線
の欠陥を補正する補正用配線を設けたことを特徴
とする液晶表示装置。 (2) 補正用配線が第１の基板の表示領域外でゲ
ート線又はドレイン線の両端と直接積層された実
用新案登録請求の範囲第１項記載の液晶表示装置
。 (3) 補正用配線が各画素毎に迂回路を形成した
実用新案登録請求の範囲第１項又は第２項記載の
液晶表示装置。[Claims for Utility Model Registration] (1) A thin film transistor having a plurality of gate lines and a plurality of drain lines perpendicular to these gate lines, and a transparent pixel connected to the thin film transistor at each intersection area of the two lines. A first substrate having an electrode, a second substrate facing the first substrate and having a common electrode, a liquid crystal provided between these substrates, and a driving circuit for the gate line and drain line. A liquid crystal display device, characterized in that a correction wiring for correcting defects in the gate line or drain line is provided on the gate line or drain line via an insulating layer in the display area of the first substrate. Device. (2) The liquid crystal display device according to claim 1, wherein the correction wiring is directly stacked on both ends of the gate line or the drain line outside the display area of the first substrate. (3) The liquid crystal display device according to claim 1 or 2, wherein the correction wiring forms a detour for each pixel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3834886U JPS62151523U (en) | 1986-03-18 | 1986-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3834886U JPS62151523U (en) | 1986-03-18 | 1986-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62151523U true JPS62151523U (en) | 1987-09-25 |
Family
ID=30850506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3834886U Pending JPS62151523U (en) | 1986-03-18 | 1986-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62151523U (en) |
-
1986
- 1986-03-18 JP JP3834886U patent/JPS62151523U/ja active Pending
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