JPH0262421U

JPH0262421U -

Info

Publication number: JPH0262421U
Application number: JP13861988U
Authority: JP
Priority date: 1988-10-26
Filing date: 1988-10-26
Publication date: 1990-05-10

Description

[Brief explanation of drawings]

第１図〜第３図は本考案の一実施例を示したも
ので、第１図は第２図の―線に沿う拡大断面
図、第２図はＴＦＴパネルの一部分の平面図、第
３図は第２図の―線に沿う拡大断面図である
。第４図〜第６図は従来のＴＦＴパネルを示した
もので、第４図はＴＦＴパネルの一部分の平面図
、第５図は第４図のＶ―Ｖ線に沿う拡大断面図、
第６図は第４図の―線に沿う拡大断面図であ
る。１１……透明基板、Ｔ……薄膜トランジスタ、
１２……ゲートライン、１２Ｇ……ゲート電極、
１３……ゲート絶縁膜、１４……半導体層、１５
……コンタクト層、１６Ｓ……ソース電極、１７
Ｄ……ドレイン電極、１８……ブロツキング層、
１９……画素電極、２０……第２の絶縁膜、２０
ａ……コンタクト孔、２１……データライン。 Figures 1 to 3 show one embodiment of the present invention, in which Figure 1 is an enlarged sectional view taken along the line - in Figure 2, Figure 2 is a plan view of a portion of the TFT panel, and Figure 3 is a plan view of a portion of the TFT panel. The figure is an enlarged sectional view taken along the line - in FIG. 2. 4 to 6 show conventional TFT panels, FIG. 4 is a plan view of a portion of the TFT panel, FIG. 5 is an enlarged sectional view taken along line V-V in FIG. 4,
FIG. 6 is an enlarged sectional view taken along the line --- in FIG. 4. 11...Transparent substrate, T...Thin film transistor,
12...gate line, 12G...gate electrode,
13... Gate insulating film, 14... Semiconductor layer, 15
...Contact layer, 16S...Source electrode, 17
D...Drain electrode, 18...Blocking layer,
19... Pixel electrode, 20... Second insulating film, 20
a...Contact hole, 21...Data line.

Claims

[Scope of utility model registration request]

A large number of gate lines and a large number of data lines perpendicular to the gate lines are formed on a transparent substrate, and a large number of transparent pixel electrodes are formed along each of the gate lines and each data line. In a TFT panel in which a large number of thin film transistors for driving each transparent pixel electrode are arranged vertically and horizontally, the thin film transistor is composed of at least a gate electrode, a gate insulating film, a semiconductor layer, a source and a drain electrode, and the stacking position of the transparent pixel electrode is The source electrode is electrically connected to the source electrode so as to be located between the gate line and the data line, and the data line and the drain electrode are connected to each other through a second insulating film different from the gate insulating film. A TFT panel characterized by electrical connection.