JPS61101866A - 二重化プロセツサにおける起動制御方式 - Google Patents

二重化プロセツサにおける起動制御方式

Info

Publication number
JPS61101866A
JPS61101866A JP59223243A JP22324384A JPS61101866A JP S61101866 A JPS61101866 A JP S61101866A JP 59223243 A JP59223243 A JP 59223243A JP 22324384 A JP22324384 A JP 22324384A JP S61101866 A JPS61101866 A JP S61101866A
Authority
JP
Japan
Prior art keywords
processor
processors
reset
register
halt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59223243A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0149984B2 (cs
Inventor
Noboru Ita
板　昇
Shigeru Mitsugi
身次　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP59223243A priority Critical patent/JPS61101866A/ja
Publication of JPS61101866A publication Critical patent/JPS61101866A/ja
Publication of JPH0149984B2 publication Critical patent/JPH0149984B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP59223243A 1984-10-24 1984-10-24 二重化プロセツサにおける起動制御方式 Granted JPS61101866A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59223243A JPS61101866A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける起動制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59223243A JPS61101866A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける起動制御方式

Publications (2)

Publication Number Publication Date
JPS61101866A true JPS61101866A (ja) 1986-05-20
JPH0149984B2 JPH0149984B2 (cs) 1989-10-26

Family

ID=16795038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59223243A Granted JPS61101866A (ja) 1984-10-24 1984-10-24 二重化プロセツサにおける起動制御方式

Country Status (1)

Country Link
JP (1) JPS61101866A (cs)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364115A (ja) * 1986-09-04 1988-03-22 Matsushita Commun Ind Co Ltd ネツトワ−クシステム立上げ方式
JP2003085153A (ja) * 2001-09-13 2003-03-20 Mitsubishi Electric Corp 制御レジスタ及びプロセッサ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364115A (ja) * 1986-09-04 1988-03-22 Matsushita Commun Ind Co Ltd ネツトワ−クシステム立上げ方式
JP2003085153A (ja) * 2001-09-13 2003-03-20 Mitsubishi Electric Corp 制御レジスタ及びプロセッサ

Also Published As

Publication number Publication date
JPH0149984B2 (cs) 1989-10-26

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