JPS6098649A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6098649A JPS6098649A JP58204850A JP20485083A JPS6098649A JP S6098649 A JPS6098649 A JP S6098649A JP 58204850 A JP58204850 A JP 58204850A JP 20485083 A JP20485083 A JP 20485083A JP S6098649 A JPS6098649 A JP S6098649A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- package
- rays
- heat rays
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、甲、！≦一体装買装置するものであり、特に
薄型の樹脂Ｊ１１１１．型半導体装置であってノ１シ板
に面イ・Ｉ実装して用いｌ）れる半導体装置に利用して
（１効か技術に閏するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to A,! ≦Integrated equipment, especially thin resin J1111. It is a type of semiconductor device that is used for face-to-face mounting on a board.
〔背Ｊ、１技術〕
レジンバソゲージ、薄型しジンパノケ〜ジ等の１へ導体
装置の実装に際して、例えば、赤外線加熱装置等により
リフロー半田（ｊｌけを行う場合があ２・（工業調査会
１９８０年出刷の「１（：化実装技術」［・１４０〜Ｉ
）＋４１）。[Back J, 1 Technology] When mounting a conductor device on a resin vaso gauge, thin metal panel cage, etc., reflow soldering is sometimes performed using, for example, an infrared heating device (Industrial Research Association 1980 ``1 (:Implementation technology'') [・140~I
)+41).
このときパッケージの′Ｊ−１＋ｌ休は黒色の１ノジン
かＩン、なっているためパッケージの封１１１体のｌ１
Ｍ度が１゜ｒｊ＋シてリードの温度よりも高くなる。こ
のためリー１へのりフロー半１１１伺は部の４１．１度
が半１１．１に必要ｚＪ゛淵度、例えば、２３０〜２４
０℃になったどきに目、パッケージ本体の温度は２７０
〜２８０°（−となり、パッケージのレジン等の封；１
一体と゛１−導体素ｒ−を取すイ］けるタブ等の熱膨張
係数の差等によ−）で封止体にクランクが発生し、耐湿
性が省力する一ｌ“の問題点があることが本発明者の検
討により明らかになった。At this time, the 'J-1+l' position on the package is the black 1-nozzle or I-in, so the package's seal is 111 units l1.
The M degree becomes 1°rj+ higher than the temperature of the lead. Therefore, the flow to Lee 1 is 41.1 degrees, which is required for half 11.1 degrees, for example, 230 to 24 degrees.
When the temperature reached 0℃, the temperature of the package itself was 270℃.
~280° (-, sealing the resin etc. of the package; 1
Due to the difference in thermal expansion coefficient between the tabs, etc. that connect the conductive element r-), cranks occur in the sealing body, which leads to the problem of labor-saving moisture resistance. This has become clear through study by the present inventor.
二のＭ法文、ｉ策としてパッケージのＪｌ ＋ｌ休の赤
夕１１！ｉｔ ｌ！（ｔ ｆｌ−１側の前面に熱線遮へ
い板を配１７１シて防熱ずろことが考えられる。しかし
ながら、この方法ではいちいち熱線遮へい板をパッケー
ジの１）；１面に配直しなければならない煩わしさとり
フロー丁、［１１イ・Ｊけ作業の効果が低減する欠点が
ある。Second M law text, package Jl +l holiday Red Sunset 11 as i-measure! It l! (It is conceivable to place a heat ray shielding plate on the front surface of the fl-1 side for heat insulation. However, with this method, the heat ray shielding plate must be rearranged on the first side of the package. However, there is a drawback that the effectiveness of the work is reduced.
本発明の目的は、リフロー半［＋’ｌ付けを行なう際に
いちいちパッケージ本体の前面に熱線遮へい板を配置し
なくてもクラック発生を低減し、耐湿性の劣化をまねか
ない半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that reduces the occurrence of cracks without having to place a heat ray shielding plate on the front of the package body each time reflow semi-attaching is performed, and does not cause deterioration of moisture resistance. There is a particular thing.
本発明の前記ならびにその他の目的と新規な特徴は、不
明’ｔ４［”ｆ！Ｆの記述及び添（４図面によって明ら
かになるであろう。The above and other objects and novel features of the present invention will become clear from the description and accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を筒Ｃ１１，に説明すれば、下記のとおりである。A typical outline of the invention disclosed in this application will be explained below with reference to cylinder C11.
すなわち、半導体装置を、リフロー半田（・Ｊけにより
基板に実装を行なう場合、パンケージの封止体のＩ）ｉ
ｉ而にいちいち熱遮へい板を配置し、なくてもよいよう
に、パッケージのＪ’４ ＋Ｉ：体の熱線ＩＫｔ ！１
．１１１１１１の表面に半田付０時の赤外線等の熱線を
反射させる手段を設けた半導体装置である。That is, when a semiconductor device is mounted on a board by reflow soldering (I) of the sealed body of the pan cage,
I also placed a heat shield on each package so that there was no need for it. 1
．． This is a semiconductor device in which a means for reflecting heat rays such as infrared rays at the time of soldering is provided on the surface of 111111.
〔実施１列〕
第１図は１本発明の゛１′導体装置の甲面図、第２図は
、第１図の八−Δ線で切った矢視概略１９ｉ面図である
。[First row of implementation] FIG. 1 is a top view of the conductor device ``1'' of the present invention, and FIG. 2 is a schematic view taken along arrow 19i along line 8-Δ in FIG.
第１図及び第２図において、１はレジン等力臼゛。In Figures 1 and 2, 1 is a resin constant force mill.
なるパッケージの月＋１・体、２はパッケージの月ＩＩ
。Naru Package Moon + 1 Body, 2 is Package Moon II
.
休１の熱線照射側の表面に塗布された白色塗料、３はリ
ード、３△はリード３のり一１〜’１′：ｌＩｌ付け部
。The white paint applied to the heat ray irradiation side surface of 1, 3 is the lead, and 3△ is the glued part of lead 3.
４は半導体素子、５はボンディングワイヤ、（ｊは゛１
４導体素了４を取す付けるタブリ−１・、７は着色マー
クインク又は凹凸で１１：・かれた゛１′導体装置の識
別記号である。4 is a semiconductor element, 5 is a bonding wire, (j is ゛1
The tabs 1 and 7 on which the four-conductor elements 4 are attached are identification symbols of the conductor device 11: and 1, which are marked with colored mark ink or unevenness.
この半導体装置は実装ＪｌＧ仮８に半［１１によって面
イ、１け実装される。すなわち、ガラスエポキシ実装、
１ノー板８１．の銅のブＩＪ：）ｉへ配線層９１．にｌ
’、Ｉｌｌ Ｊ、 （ｌかＪｌう：←゛）れでいる。こ
の１うｌＩｌ １０１−に令でのリ−トのＩＪ−１−コ
ＬＩＴ１イ」け部３．へをテープ’ｈ”ｅ ｌｊ１＋え
イ・等（ｌ叫一段により押接した−１−で、１・方より
赤夕１線加熱ｙｒ ＋、’、。This semiconductor device is mounted on the mounting JlG tentatively 8 with half [11] on the surface A, one digit. i.e. glass epoxy mounting,
1 no board 81. Copper block IJ:)i to wiring layer 91. ni l
', Ill J, (l or Jl う：←゛). IJ-1-LIT1 part 3. Tape ``h''e lj1+e, etc. (-1- pressed by one stage of l scream, 1-ray heating yr +, ', from 1 side.
等からの赤外線を照！１・１【１、加熱す−ろ−７扛に
１、Ｊて’ｌ′、ｒｌ＋ １０をリフローした後、ｔイ
ミ冷する二とに、Ｊ、す゛４４導体装置の実装が行なわ
れろ。Shine infrared rays from etc.! 1.1 [1. After reflowing 1, J, 'l', rl+10 in heating channel 7, cooling at t, then mounting of J, 44 conductor device is carried out.
本実施例はパッケージの１゛４止体１の熱線が照射され
る１４面を白色塗Ｊ’ｌ ２で被覆したので、このパッ
ケージの月１１体ｌの表面で熱線が反ηＪされ、パン）
ｆ−ジの」゛・ｊ重体１に加えられる熱は低；威される
。In this example, the 14 sides of the package 1゛4 stationary body 1 that are irradiated with heat rays are coated with white paint J'l 2, so the heat rays are reflected on the surface of the 11 bodies 1 of this package, and the pan)
The heat applied to the heavy body 1 of f-di is low;
これにより熱線照射時に！１月Ｉｔ ４１けするり・−
１−半ＩＴＩイ、（け部３Δよりパッケージの’Ｊ−）
＋１．：休１の温度はに昇しない。This allows for heat ray irradiation! January It 41 Kesuri・-
1-Half ITI A, ('J- of the package from the edge 3Δ)
+1. :The temperature during rest 1 does not rise to .
なａ：； 、識別マーク７は、この部分に白色塗料を・
令布せず黒色のレジン封止体が露出するようにして設け
てもよい。この場合、識別マーク７の占有面積が小さい
ので熱線の反射には何ら問題はない。a:;, the identification mark 7 is made by applying white paint to this part.
It may also be provided so that the black resin sealing body is exposed without being exposed. In this case, since the area occupied by the identification mark 7 is small, there is no problem with reflection of heat rays.
また、前記白色塗料２の代りにアルミニラ１１等の熱線
反射する薄板を埋め込んでもよい。この場合アルミニウ
ム薄板は反射板の代能ばかりでなく半導体装置からの熱
の放散を助長する放熟板の機能を有し・ている。この場
合も、識別マーグアはこの部分のアルミニウム等を除去
するか、凹凸の刻印によって設けてよい。Further, instead of the white paint 2, a heat-reflecting thin plate such as alumina 11 may be embedded. In this case, the aluminum thin plate not only functions as a reflector but also as a radiation plate that promotes the dissipation of heat from the semiconductor device. In this case as well, the identification margua may be provided by removing the aluminum or the like in this portion or by marking it with concave and convex portions.
レジンパッケージ、薄型レジンパッケージ笠のｊ゛・１
止休の赤外線等の熱線前４１側の表面に熱綿以η１’ｎ
Ｉ？ｊを設けることにより、熱綿遮へい（ノスをいｌ
−、いち配置することなく、熱線照射１１テに才；け７
＋ 、１’；ｌ’ ＋ｌ） ０．：に加えられる熱を低
減することができる１、こＪｌ、により前記封止体の温
度はり−１・’＋４１１１４・１（−１部より１・昇し
ないため１月１１一体のクラック発）１を低）威Ｉ１．
。Resin package, thin resin package shade j゛・1
There is no hot cotton η1'n on the surface in front of the 41 side of the heat rays such as infrared rays.
I? By providing a thermal cotton shield
- 11 degrees of heat ray irradiation without having to place one;
+, 1';l' +l) 0. 1. Due to this Jl, the temperature of the sealed body is -1·'+41114·1 (because it does not rise by 1·1 from -1 part, cracks occurred on January 11) 1 low) Wei I1.
.
ｉ、Ｉ湿性の劣化を防１１．することができ、かつ、リ
フロー’Ｉ′ＩＩＩ （Ｊけ作業の助字も向１させるこ
とができる。i, I Prevent moisture deterioration 11. In addition, the auxiliary character of reflow 'I'III (J-ke operation) can also be changed to direction 1.
以］一本発明者に、１゛ってなされた発明を実施例にも
どづき」５体的に説明したが、本発明は、＋”＋ｉＪ記
実施例に限定されるものでなく、その要旨を逸脱しない
範囲で種々変更＋’ｉ（能であることはいうまでもない
。Hereinafter, the invention made by the present inventor has been explained in detail based on the examples, but the present invention is not limited to the examples described above, and the gist thereof It goes without saying that various changes can be made without departing from the above.
たとえば熱線の反ｎ＝＋丁５段として設けた領域２どし
て、良好な絶縁物が用いｌ）れる場合は、Ｊ・１１１一
体の表面全体、あるいけ月１１０体の１−面全体に渡−
１て前記領域２を設置ｊることもｉｉ（能である。また
、前記反η・１手段として熱線を有効に反ｎ■するもの
であれば他の材料を用いろことももちろんｉｔｒ能であ
る。For example, if a good insulating material is used for the region 2 provided as a heating wire with anti-n = + 5 steps, the entire surface of J.111, or the entire surface 1 of Passing
It is also possible to install the area 2 with the above-mentioned method.Also, it is also possible to use other materials as long as the heat rays can be effectively repelled as a means for preventing heat rays. be.
図面の前＋１ｊ、な説明
第１図は、本発明の−・実施例の平面図、第２図は、第
１図のΔ−Δ線で切った矢視概略断面図である。1 is a plan view of an embodiment of the present invention, and FIG. 2 is a schematic sectional view taken along the line Δ-Δ in FIG. 1.
ｌ・・・パッケージの封１１、体、２・・・白色塗才゛
１．３・・・リート、３Δ・・・リード半１１１伺（づ
部、４・・パ１′：導体諌（了・、５・・・ボンディン
グワイヤ、６・・・タブ、７・・・識別記号。l...Package seal 11, body, 2...white coating 1.3...lead, 3Δ...lead half 111 part, 4...pa 1': conductor・, 5... Bonding wire, 6... Tab, 7... Identification symbol.
第 １ 図 第 ２ 図Figure 1 Figure 2
Claims (1)
を１１αけたことをｔｉｙ徴とする半導体”ＪＵ Ｍｉ
。 ２ 、 ｉ）ｆ記熱線を反、ｌＪする手段として白色塗
料を封止体に塗布したことを特徴とする特許請求の範囲
第１項記・代の半導体装置 ｒ）、前記熱線を反射する手段としてアルミニラ１１等
の反射物体を用いたことを’ｔ、′ｌ′徴とする特３′
（請求の範囲第１項記載の半導体装置。[Claims] 1. Semiconductor "JU Mi" whose tiy characteristic is that a part of the surface of the package is provided with means for reflecting heat rays by 11α
. 2. i) A semiconductor device according to claim 1, characterized in that white paint is applied to the sealing body as a means for reflecting the heat rays (r), a means for reflecting the heat rays; Characteristic 3' where the 't, 'l' feature is that a reflective object such as Aluminum 11 is used as the
(Semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204850A JPS6098649A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204850A JPS6098649A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6098649A true JPS6098649A (en) | 1985-06-01 |
Family
ID=16497427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58204850A Pending JPS6098649A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098649A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294411B1 (en) | 1996-10-25 | 2001-09-25 | Nippon Steel Semiconductor Corporation | Method for molding a semiconductor device utilizing a satin finish |
| US11837554B2 (en) | 2020-03-17 | 2023-12-05 | Kioxia Corporation | Semiconductor package and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49114362A (en) * | 1973-02-28 | 1974-10-31 |
-
1983
- 1983-11-02 JP JP58204850A patent/JPS6098649A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49114362A (en) * | 1973-02-28 | 1974-10-31 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294411B1 (en) | 1996-10-25 | 2001-09-25 | Nippon Steel Semiconductor Corporation | Method for molding a semiconductor device utilizing a satin finish |
| US11837554B2 (en) | 2020-03-17 | 2023-12-05 | Kioxia Corporation | Semiconductor package and semiconductor device |
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