JP2002110862A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002110862A JP2002110862A JP2000297838A JP2000297838A JP2002110862A JP 2002110862 A JP2002110862 A JP 2002110862A JP 2000297838 A JP2000297838 A JP 2000297838A JP 2000297838 A JP2000297838 A JP 2000297838A JP 2002110862 A JP2002110862 A JP 2002110862A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- cover
- semiconductor device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
製造方法に関するものである。The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】図２（ａ），（ｂ）は、従来の半導体装
置の一例を示す概略の構成図であり、同図（ａ）は平面
図、及び同図（ｂ）は同図（ａ）のＸ−Ｘ線における断
面図である。2. Description of the Related Art FIGS. 2A and 2B are schematic structural views showing an example of a conventional semiconductor device. FIG. 2A is a plan view, and FIG. It is sectional drawing in the XX line of a).
【０００３】図２に示すように、この半導体装置は、半
導体チップ１の回路形成面上に絶縁膜２が設けられ、集
積回路の一部であるＡｌ（アルミニウム）電極３からこ
の絶縁膜２上にＣｕ（銅）配線４が設けられている。絶
縁膜２及びＣｕ配線４上は、回路保護用の樹脂５で封止
されている。また、Ｃｕ配線４の外部接続箇所である端
子表面４ａには、半田によるバンプ端子６が搭載されて
いる。As shown in FIG. 2, in this semiconductor device, an insulating film 2 is provided on a circuit forming surface of a semiconductor chip 1, and an Al (aluminum) electrode 3 which is a part of an integrated circuit is formed on the insulating film 2. Is provided with a Cu (copper) wiring 4. The insulating film 2 and the Cu wiring 4 are sealed with a resin 5 for circuit protection. A bump terminal 6 made of solder is mounted on a terminal surface 4a which is an external connection portion of the Cu wiring 4.
【０００４】このような半導体装置は、次のように製造
される。まず、半導体ウエハ上に複数の集積回路を形成
し、絶縁膜２及びＣｕ配線４を設ける。更に、半導体ウ
エハ上の絶縁膜２及びＣｕ配線４を覆うように、樹脂５
を充填する。[0004] Such a semiconductor device is manufactured as follows. First, a plurality of integrated circuits are formed on a semiconductor wafer, and an insulating film 2 and a Cu wiring 4 are provided. Further, a resin 5 is formed so as to cover the insulating film 2 and the Cu wiring 4 on the semiconductor wafer.
Fill.
【０００５】次に、樹脂５で覆われた半導体ウエハの表
面を研磨刃で平らに研磨し、Ｃｕ配線４の端子表面４ａ
を半導体ウエハ表面に露呈させる。そして、半導体ウエ
ハ表面に露呈した端子表面４ａ上にバンプ端子６を搭載
する。Next, the surface of the semiconductor wafer covered with the resin 5 is polished flat with a polishing blade, and the terminal surface 4a of the Cu wiring 4 is polished.
Is exposed on the surface of the semiconductor wafer. Then, the bump terminals 6 are mounted on the terminal surfaces 4a exposed on the semiconductor wafer surface.
【０００６】更に、高速回転する切削刃によって半導体
ウエハを切断して個々の半導体装置に分割する。これに
よって、図２のような半導体装置が得られる。Further, the semiconductor wafer is cut by a high-speed rotating cutting blade and divided into individual semiconductor devices. Thus, a semiconductor device as shown in FIG. 2 is obtained.
【０００７】このような半導体装置を回路基板に組み込
む時には、半導体チップ１の回路形成面を下にして、回
路基板の所定の位置にバンプ端子６が一致するように搭
載する。更に、回路基板をリフロー炉に入れてバンプ端
子６の半田を溶融させ、半導体装置を回路基板に接続す
る。When such a semiconductor device is mounted on a circuit board, the semiconductor chip 1 is mounted with the circuit forming surface of the semiconductor chip 1 down so that the bump terminals 6 coincide with predetermined positions on the circuit board. Further, the circuit board is placed in a reflow furnace to melt the solder of the bump terminals 6, and the semiconductor device is connected to the circuit board.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置では、次のような課題があった。 （１） 半導体装置の裏面（即ち、回路形成面の反対側
の面）がＳｉ（シリコン）の結晶となっているので、こ
の半導体装置を回路基板に押しつけて実装する際に、半
導体チップ１の一部に欠けが発生し、その欠け片によっ
て接続不良が発生することがあった。However, the conventional semiconductor device has the following problems. (1) Since the back surface of the semiconductor device (that is, the surface opposite to the circuit formation surface) is a crystal of Si (silicon), when the semiconductor device is pressed against the circuit board and mounted, the semiconductor chip 1 In some cases, chipping occurred, and the chipped piece sometimes caused poor connection.
【０００９】（２） バンプ端子６の位置が半導体装置
の裏面からは見えないので、この半導体装置を回路基板
に搭載するときに、所定の位置から外れるおそれがあっ
た。(2) Since the position of the bump terminal 6 cannot be seen from the back surface of the semiconductor device, there is a possibility that the bump terminal 6 may be deviated from a predetermined position when the semiconductor device is mounted on a circuit board.
【００１０】（３） 半導体ウエハの表面全体を樹脂５
で封止した後、切断して個々の半導体装置に分割するた
め、切削刃が樹脂によって目詰まりして切削負荷が大き
くなり、半導体チップ１が欠けることがあった。(3) The entire surface of the semiconductor wafer is covered with resin 5
After the sealing, the semiconductor chip is cut and divided into individual semiconductor devices. Therefore, the cutting blade is clogged with the resin, the cutting load is increased, and the semiconductor chip 1 may be chipped.
【００１１】（４） 半導体ウエハの表面全体を樹脂５
で封止した後、個々の半導体装置に切断するようにして
いるので、半導体ウエハ上の良品の数が少ない場合で
も、この半導体ウエハの表面全体に樹脂封止を施さねば
ならず、製造コストが高くなっていた。(4) The entire surface of the semiconductor wafer is covered with resin 5
After that, the semiconductor device is cut into individual semiconductor devices, so even if the number of non-defective products on the semiconductor wafer is small, the entire surface of the semiconductor wafer must be resin-sealed, resulting in lower manufacturing costs. Was higher.
【００１２】本発明は、前記従来技術が持っていた課題
を解決し、製造中や実装中に破損するおそれのない半導
体装置とその製造方法を提供するものである。An object of the present invention is to solve the problems of the prior art and to provide a semiconductor device which is not likely to be damaged during manufacturing or mounting, and a method of manufacturing the same.
【００１３】[0013]
【課題を解決するための手段】前記課題を解決するため
に、本発明の内の第１の発明は、半導体装置において、
半導体基板表面の回路形成面上に集積回路と外部接続用
の複数の電極が形成された半導体チップと、前記半導体
チップ全体を収容できる深さの凹部を有する金属製のカ
バーと、前記カバーの凹部の内部底面に前記半導体チッ
プの裏面を固定する接着剤と、前記カバー内に固定され
た前記半導体チップの回路形成面を封止する封止樹脂
と、加熱溶着によって回路基板に電気的かつ機械的に接
続するために前記半導体チップの各電極上に形成された
バンプ端子とを備えている。According to a first aspect of the present invention, there is provided a semiconductor device, comprising:
A semiconductor chip in which an integrated circuit and a plurality of electrodes for external connection are formed on a circuit forming surface on a surface of a semiconductor substrate; a metal cover having a recess having a depth capable of accommodating the entire semiconductor chip; and a recess of the cover An adhesive for fixing the back surface of the semiconductor chip to the inner bottom surface of the semiconductor chip, a sealing resin for sealing the circuit forming surface of the semiconductor chip fixed in the cover, and electrically and mechanically And bump terminals formed on each electrode of the semiconductor chip for connection to the semiconductor chip.
【００１４】第２の発明では、第１の発明における封止
樹脂を前記カバーの凹部の縁と同一の高さまで充填して
前記半導体チップの回路形成面上を封止するように形成
している。In a second aspect, the sealing resin of the first aspect is filled up to the same height as the edge of the concave portion of the cover so as to seal the circuit forming surface of the semiconductor chip. .
【００１５】第３の発明では、第２の発明において、加
熱溶着によって前記カバーを回路基板に固定するために
該カバーの凹部の縁に前記バンプ端子と同様のバンプを
設けると共に、前記接着剤に導電性を有するものを用い
ている。According to a third aspect, in the second aspect, a bump similar to the bump terminal is provided at an edge of a concave portion of the cover to fix the cover to the circuit board by heat welding, and the adhesive is provided on the adhesive. The one having conductivity is used.
【００１６】第４の発明では、第３の発明における接着
剤として金または銀を用いている。In the fourth invention, gold or silver is used as the adhesive in the third invention.
【００１７】第５の発明では、第１〜第４の発明におい
て、前記カバーの凹部の縁の周囲に樹脂製のダムを設け
ると共に、該ダムの内側に樹脂を塗布している。According to a fifth aspect of the present invention, in the first to fourth aspects, a resin dam is provided around an edge of the concave portion of the cover, and a resin is applied inside the dam.
【００１８】第６の発明では、第１〜第５の発明におい
て、前記カバーの表面に搭載位置決め用のマークを付し
ている。According to a sixth aspect, in the first to fifth aspects, a mark for positioning is provided on the surface of the cover.
【００１９】第７の発明は、半導体装置の製造方法にお
いて、次のような分割工程と、接着工程と、封止工程
と、研磨工程と、搭載工程とを順次行うようにしてい
る。According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, the following dividing step, bonding step, sealing step, polishing step, and mounting step are sequentially performed.
【００２０】分割工程は、複数の集積回路が形成された
半導体ウエハを切り出して半導体基板表面の回路形成面
上に集積回路と外部接続用の複数の電極が形成された半
導体チップに分割するものである。接着工程は、凹部を
有する金属製のカバーの内側に前記半導体チップの裏面
を接着するものである。封止工程は、前記カバーの凹部
に接着された前記半導体チップを覆うように該凹部に封
止樹脂を充填するものである。研磨工程は、前記充填し
た封止樹脂の表面を平らに研磨して前記半導体チップの
電極の表面を露呈させるものである。搭載工程は、前記
研磨工程で露呈させた前記半導体チップの電極の表面に
バンプ端子を搭載するものである。In the dividing step, a semiconductor wafer on which a plurality of integrated circuits are formed is cut out and divided into semiconductor chips on which a plurality of electrodes for external connection are formed on a circuit forming surface of a semiconductor substrate. is there. In the bonding step, the back surface of the semiconductor chip is bonded to the inside of a metal cover having a concave portion. In the sealing step, the recess is filled with a sealing resin so as to cover the semiconductor chip adhered to the recess of the cover. In the polishing step, the surface of the filled sealing resin is polished flat to expose the surfaces of the electrodes of the semiconductor chip. The mounting step includes mounting bump terminals on the surfaces of the electrodes of the semiconductor chip exposed in the polishing step.
【００２１】本発明によれば、以上のように半導体装置
を構成したので、半導体チップの周囲が金属製のカバー
と封止樹脂で保護され、Ｓｉ等の半導体基板が表面に露
出することがない。これにより、製造中や実装中に破損
するおそれのない半導体装置が得られる。According to the present invention, since the semiconductor device is configured as described above, the periphery of the semiconductor chip is protected by the metal cover and the sealing resin, and the semiconductor substrate such as Si is not exposed on the surface. . Thereby, a semiconductor device which is not likely to be damaged during manufacturing or mounting can be obtained.
【００２２】[0022]
【発明の実施の形態】（第１の実施形態）図１（ａ），
（ｂ）は、本発明の第１の実施形態を示す半導体装置の
概略の構成図であり、同図（ａ）は平面図、及び同図
（ｂ）は同図（ａ）のＡ−Ａ線における断面図である。
図１（ａ），（ｂ）において、図２中の要素と共通の要
素には共通の符号が付されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
2B is a schematic configuration diagram of the semiconductor device according to the first embodiment of the present invention, wherein FIG. 2A is a plan view, and FIG. 2B is an AA line of FIG. It is sectional drawing in a line.
1 (a) and 1 (b), elements common to those in FIG. 2 are denoted by common reference numerals.
【００２３】この半導体装置は、集積回路が形成された
半導体チップ１と、これを保護するための金属カバー８
及び封止樹脂９を有している。半導体チップ１の回路形
成面上には絶縁膜２が設けられ、集積回路の一部である
Ａｌ電極３から絶縁膜２上にＣｕ配線４が設けられてい
る。半導体チップ１の裏面は、Ａｇ（銀）等の導電性及
び熱伝導性を有する接着剤７で金属カバー８の内部底面
に固定されている。This semiconductor device has a semiconductor chip 1 on which an integrated circuit is formed and a metal cover 8 for protecting the semiconductor chip 1.
And a sealing resin 9. An insulating film 2 is provided on a circuit forming surface of the semiconductor chip 1, and a Cu wiring 4 is provided on the insulating film 2 from an Al electrode 3 which is a part of an integrated circuit. The back surface of the semiconductor chip 1 is fixed to the inner bottom surface of the metal cover 8 by a conductive and heat conductive adhesive 7 such as Ag (silver).
【００２４】金属カバー８は、厚さ０．１ｍｍ程度のＦ
ｅ（鉄）またはＣｕ板をプレス加工して、半導体チップ
１が丁度収まる大きさの深さ０．２ｍｍ程度の凹部８ａ
を設けると共に、その周囲にフランジ部８ｂを設けたも
のである。The metal cover 8 has a thickness of about 0.1 mm.
e (iron) or a Cu plate is pressed to form a recess 8a having a depth of about 0.2 mm and a size just enough to accommodate the semiconductor chip 1.
And a flange portion 8b is provided therearound.
【００２５】金属カバー８の凹部８ａには、半導体チッ
プ１の絶縁膜２及びＣｕ配線４を覆ってフランジ部８ｂ
と同一平面を形成するように封止樹脂９が充填されてい
る。また、封止樹脂９の表面に露出したＣｕ配線４の外
部接続箇所である端子表面４ａと、金属カバー８のフラ
ンジ部８ｂには、半田によるバンプ端子６が搭載されて
いる。更に、金属カバー８の表面、即ち封止樹脂９が充
填されていない方の面には、半導体チップ１に設けられ
たバンプ端子６に対応する位置に、搭載位置決め用のマ
ークとして溝穴８ｃが設けられている。In the recess 8 a of the metal cover 8, a flange 8 b covering the insulating film 2 and the Cu wiring 4 of the semiconductor chip 1 is formed.
The sealing resin 9 is filled so as to form the same plane as. In addition, bump terminals 6 made of solder are mounted on the terminal surface 4 a, which is an external connection portion of the Cu wiring 4 exposed on the surface of the sealing resin 9, and on the flange portion 8 b of the metal cover 8. Further, on the surface of the metal cover 8, that is, the surface not filled with the sealing resin 9, a slot 8 c is formed as a mounting positioning mark at a position corresponding to the bump terminal 6 provided on the semiconductor chip 1. Is provided.
【００２６】図３（ａ）〜（ｈ）は、図１の半導体装置
の製造方法の工程図である。以下、これらの図３（ａ）
〜（ｈ）を参照しつつ、図１の半導体装置の製造方法を
説明する。FIGS. 3A to 3H are process diagrams of the method for manufacturing the semiconductor device of FIG. Hereinafter, FIG.
The method of manufacturing the semiconductor device in FIG. 1 will be described with reference to FIGS.
【００２７】（ａ） 工程１ 半導体ウエハ１Ｗ上に複数の集積回路を形成し、絶縁膜
２、Ａｌ電極３及びＣｕ配線４を設ける。この時、保護
用の樹脂による封止は行わない。(A) Step 1 A plurality of integrated circuits are formed on a semiconductor wafer 1W, and an insulating film 2, an Al electrode 3, and a Cu wiring 4 are provided. At this time, sealing with a protective resin is not performed.
【００２８】（ｂ） 工程２ 高速回転する切削刃Ｃによって半導体ウエハ１Ｗを切断
して個々の半導体チップ１に分割する。(B) Step 2 The semiconductor wafer 1W is cut by the cutting blade C rotating at a high speed and divided into individual semiconductor chips 1.
【００２９】（ｃ） 工程３ １枚のＦｅまたはＣｕ板に、プレス加工によって複数の
凹部８ａを一括形成した金属カバー８Ｗを用意してお
き、これらの凹部８ａに接着剤７を用いて半導体チップ
１の裏面を固定する。(C) Step 3 A metal cover 8W in which a plurality of recesses 8a are collectively formed by press working on one Fe or Cu plate is prepared, and a semiconductor chip is formed in these recesses 8a using an adhesive 7. 1 is fixed on the back surface.
【００３０】（ｄ） 工程４ 金属カバー８Ｗの凹部８ａに封止樹脂９を充填し、半導
体チップ１の絶縁膜２とＣｕ配線４の表面を封止する。(D) Step 4 The recess 8a of the metal cover 8W is filled with a sealing resin 9 to seal the surface of the insulating film 2 of the semiconductor chip 1 and the surface of the Cu wiring 4.
【００３１】（ｅ） 工程５ 金属カバー８Ｗの凹部８ａに充填した封止樹脂９の表面
を、研磨刃で平らに研磨し、この金属カバー８Ｗのフラ
ンジ部８ｂとＣｕ配線４の端子表面４ａを露呈させる。(E) Step 5 The surface of the sealing resin 9 filled in the concave portion 8a of the metal cover 8W is polished flat with a polishing blade, and the flange portion 8b of the metal cover 8W and the terminal surface 4a of the Cu wiring 4 are polished. Expose.
【００３２】（ｆ） 工程６ 研磨した封止樹脂９の表面をビデオカメラ等によって読
み取り、端子表面４ａの位置を検出する。更に、検出し
た端子表面４ａの位置に対応する金属カバー８Ｗの表
面、即ち端子表面４ａの反対側に、レーザビーム等を照
射して搭載位置決め用の溝穴８ｃを形成する。(F) Step 6 The polished surface of the sealing resin 9 is read by a video camera or the like, and the position of the terminal surface 4a is detected. Further, the surface of the metal cover 8W corresponding to the detected position of the terminal surface 4a, that is, the opposite side of the terminal surface 4a is irradiated with a laser beam or the like to form a slot 8c for mounting positioning.
【００３３】（ｇ） 工程７ 端子表面４ａの上と、金属カバー８Ｗのフランジ部８ｂ
の所定の位置に、バンプ端子６を搭載する。(G) Step 7: On the terminal surface 4a and the flange portion 8b of the metal cover 8W
The bump terminal 6 is mounted at a predetermined position.
【００３４】（ｈ） 工程８ 金属カバー８Ｗのフランジ部８ｃを切削刃Ｃによって個
々の金属カバー８に切断する。これにより、図１の半導
体装置が完成する。(H) Step 8 The flange 8c of the metal cover 8W is cut into individual metal covers 8 by the cutting blade C. Thereby, the semiconductor device of FIG. 1 is completed.
【００３５】このように製造された半導体装置を回路基
板に組み込む時には、半導体チップ１の回路形成面を下
にして、回路基板の所定の位置にバンプ端子６が一致す
るように搭載する。この時、金属カバー８の表面に形成
された溝穴８ｃによってバンプ端子６の位置を検出し、
この金属カバー８の表面を真空チャックで吸引して回路
基板の所定の位置に搭載する。更に、半導体装置やその
他の回路部品等が搭載された回路基板をリフロー炉に入
れ、バンプ端子６の半田を溶融させて半導体装置や回路
部品等を回路基板に接続する。When the semiconductor device manufactured as described above is mounted on a circuit board, the semiconductor chip 1 is mounted with the circuit forming surface of the semiconductor chip 1 down so that the bump terminals 6 coincide with predetermined positions on the circuit board. At this time, the position of the bump terminal 6 is detected by the slot 8c formed on the surface of the metal cover 8,
The surface of the metal cover 8 is suctioned by a vacuum chuck and mounted on a predetermined position on a circuit board. Further, the circuit board on which the semiconductor device and other circuit components are mounted is put into a reflow furnace, and the solder of the bump terminals 6 is melted to connect the semiconductor device and the circuit components to the circuit board.
【００３６】以上のように、この第１の実施形態の半導
体装置は、次のような利点がある。 （ｉ） 半導体チップ１が金属カバー８と封止樹脂９で
覆われているので、損傷するおそれがない。As described above, the semiconductor device of the first embodiment has the following advantages. (I) Since the semiconductor chip 1 is covered with the metal cover 8 and the sealing resin 9, there is no possibility of damage.
【００３７】（ii） 半導体チップ１は、Ａｇ等の熱伝
導性の接着剤７で金属カバー８に接続されているので、
放熱効果が大きい。(Ii) Since the semiconductor chip 1 is connected to the metal cover 8 with a thermally conductive adhesive 7 such as Ag,
Great heat dissipation effect.
【００３８】（iii) 半導体チップ１は、電導性の接着
剤７で金属カバー８に接続され、かつこの金属カバー８
はバンプ端子６で回路基板に接続されるようになってい
るので、電磁的なシールド効果が得られる。(Iii) The semiconductor chip 1 is connected to the metal cover 8 with an electrically conductive adhesive 7 and the metal cover 8
Are connected to the circuit board by the bump terminals 6, so that an electromagnetic shielding effect can be obtained.
【００３９】（iv） 金属カバー８の表面に位置決め用
の溝穴８ｃが形成されているので、回路基板の正確な位
置に搭載することができる。(Iv) Since the positioning groove 8c is formed on the surface of the metal cover 8, it can be mounted at an accurate position on the circuit board.
【００４０】（ｖ） 金属カバー８のフランジ部８ｂに
もバンプ端子６が設けられているので、回路基板に強固
に実装することができる。(V) Since the bump terminals 6 are also provided on the flange portions 8b of the metal cover 8, they can be firmly mounted on the circuit board.
【００４１】（Vi） 半導体ウエハ１Ｗの表面を樹脂で
封止する前に切断して個々の半導体チップ１に分割する
ため、切削刃Ｃの目詰まりがなく、切断中に半導体チッ
プ１が欠けるおそれが少ない。(Vi) Since the surface of the semiconductor wafer 1W is cut before being sealed with resin and divided into individual semiconductor chips 1, there is no clogging of the cutting blade C, and the semiconductor chip 1 may be chipped during cutting. Less is.
【００４２】（vii) 個々の半導体チップ１に切断した
後、金属カバー８に収容して樹脂封止を行うようにして
いるので、不良半導体チップに対する無駄な製造コスト
を排除することができる。(Vii) Since each semiconductor chip 1 is cut and housed in the metal cover 8 and sealed with a resin, wasteful manufacturing costs for defective semiconductor chips can be eliminated.
【００４３】（第２の実施形態）図４は、本発明の第２
の実施形態を示す半導体装置の概略の構成図であり、図
１中の要素と共通の要素には共通の符号が付されてい
る。この半導体装置は、半導体チップ１表面のＡｌ電極
３上にＡｕ（金）バンプ端子１０が形成され、その面上
に半田によるバンプ端子６が形成された構造になってい
る。その他の構造は、図１と同様である。(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a semiconductor device according to the first embodiment, in which components common to those in FIG. 1 are denoted by common reference numerals. This semiconductor device has a structure in which Au (gold) bump terminals 10 are formed on Al electrodes 3 on the surface of a semiconductor chip 1, and bump terminals 6 made of solder are formed on the surface. Other structures are the same as those in FIG.
【００４４】この第２の実施形態の半導体装置は、前記
（ｉ）〜（vii)の利点に加えて、次の(viii)のような利
点がある。 (viii) バンプ端子６は、Ａｕバンプ端子１０と接合し
ているので、酸化膜がなく、接合不良が発生しない。The semiconductor device of the second embodiment has the following advantages (viii) in addition to the advantages (i) to (vii). (viii) Since the bump terminal 6 is bonded to the Au bump terminal 10, there is no oxide film and no bonding failure occurs.
【００４５】（第３の実施形態）図５は、本発明の第３
の実施形態を示す半導体装置の概略の構成図であり、図
１中の要素と共通の要素には共通の符号が付されてい
る。この半導体装置は、金属カバー８のフランジ部８ｂ
の周囲に沿って絶縁樹脂によるダム１１が設けられると
共に、このダム１１の内部の封止樹脂９の表面に酸化防
止用の樹脂１２が塗布された構造になっている。その他
の構造は、図１と同様である。(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a semiconductor device according to the first embodiment, in which components common to those in FIG. 1 are denoted by common reference numerals. This semiconductor device includes a flange portion 8 b of a metal cover 8.
A dam 11 made of an insulating resin is provided along the periphery of the sealing resin 9, and a resin 12 for preventing oxidation is applied to the surface of the sealing resin 9 inside the dam 11. Other structures are the same as those in FIG.
【００４６】以上のように、この第３の実施形態の半導
体装置は、前記（ｉ）〜（vii)の利点に加えて、次の
（ix），（ｘ）のような利点がある。As described above, the semiconductor device of the third embodiment has the following advantages (ix) and (x) in addition to the advantages (i) to (vii).
【００４７】（ix） バンプ端子６と端子表面４ａの接
続部が樹脂１２で覆われるので、この接続部の酸化によ
るバンプ端子６の剥がれが防止できる。(Ix) Since the connection between the bump terminal 6 and the terminal surface 4a is covered with the resin 12, peeling of the bump terminal 6 due to oxidation of this connection can be prevented.
【００４８】（ｘ） 半導体装置の実装面、即ちバンプ
端子６側に薄く塗布された樹脂１２を有しているので、
温度変化による熱膨張ストレスがこの樹脂１２の表面に
集中する。これにより、バンプ端子６とＣｕ配線４の端
子表面４ａの界面へのストレスが緩和され、バンプ端子
６が剥がれるおそれがなくなる。(X) Since the resin 12 is thinly applied on the mounting surface of the semiconductor device, that is, on the bump terminal 6 side,
Thermal expansion stress due to temperature change concentrates on the surface of the resin 12. Thereby, stress on the interface between the bump terminal 6 and the terminal surface 4a of the Cu wiring 4 is reduced, and the possibility that the bump terminal 6 is peeled off is eliminated.
【００４９】なお、本発明は、上記実施形態に限定され
ず、種々の変形が可能である。この変形例としては、例
えば、次の（Ａ）〜（Ｊ）のようなものがある。Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (A) to (J).
【００５０】（Ａ） 金属カバー８内に１個の半導体チ
ップ１を配置しているが、複数の半導体チップを配置し
ても良い。(A) Although one semiconductor chip 1 is arranged in the metal cover 8, a plurality of semiconductor chips may be arranged.
【００５１】（Ｂ） 金属カバー８の内部を封止樹脂９
で充填しているが、半導体チップ１の表面にのみ樹脂を
塗布するようにしても良い。(B) Enclose the inside of the metal cover 8 with the sealing resin 9
However, the resin may be applied only to the surface of the semiconductor chip 1.
【００５２】（Ｃ） 接着剤７、Ａｌ電極３、Ｃｕ配線
４、バンプ端子６、Ａｕバンプ端子１０等の材質は、例
示したものに限定されず、その機能を果たすものであれ
ばどのような材料でも同様に適用可能である。(C) The materials of the adhesive 7, the Al electrode 3, the Cu wiring 4, the bump terminal 6, the Au bump terminal 10 and the like are not limited to those exemplified above, and any material can be used as long as it fulfills its function. Materials are equally applicable.
【００５３】（Ｄ） 半導体チップ１と金属カバー８は
Ａｇの接着剤７で固定しているが、半導体チップ１の裏
面と金属カバー８の内部底面に予めＡｕめっきを施して
おき、加熱溶着するようにしても良い。(D) The semiconductor chip 1 and the metal cover 8 are fixed with an adhesive 7 made of Ag, but Au plating is applied to the back surface of the semiconductor chip 1 and the inner bottom surface of the metal cover 8 in advance, and heat welding is performed. You may do it.
【００５４】（Ｅ） 半導体チップ１の裏面を所定の電
位に接続する必要がない場合には、半導体チップ１と金
属カバー８を絶縁性の接着剤７で固定しても良い。(E) When it is not necessary to connect the back surface of the semiconductor chip 1 to a predetermined potential, the semiconductor chip 1 and the metal cover 8 may be fixed with an insulating adhesive 7.
【００５５】（Ｆ） 半導体チップ１の裏面を電気的に
接続する必要がなく、かつＣｕ配線４の端子表面４ａだ
けで回路基板に強固に接続できる場合には、金属カバー
８のフランジ部８ｂにバンプ端子６を設ける必要はな
い。また、金属カバー８にフランジ部８ｂを設ける必要
もない。(F) When the back surface of the semiconductor chip 1 does not need to be electrically connected and can be firmly connected to the circuit board only by the terminal surface 4 a of the Cu wiring 4, the connection to the flange 8 b of the metal cover 8 is made. There is no need to provide the bump terminals 6. Also, it is not necessary to provide the metal cover 8 with the flange portion 8b.
【００５６】（Ｇ） バンプ端子６の大きさや間隔等に
余裕があって、搭載位置がずれるおそれのない場合に
は、金属カバー８の表面に搭載位置決め用の溝穴８ｃを
設ける必要はない。(G) When there is a margin in the size, interval, and the like of the bump terminals 6 and there is no possibility that the mounting position is shifted, it is not necessary to provide the mounting cover groove 8 c on the surface of the metal cover 8.
【００５７】（Ｈ） 図３の工程３で、複数の凹部８ａ
を一括形成した金属カバー８Ｗに半導体チップ１を固定
して、樹脂封止や研磨等の一括処理を施した後、工程８
で個々の金属カバー８に切断分離している。大型の金属
カバー８を用いる場合等には、個別の金属カバー８に半
導体チップ１を固定しても良い。(H) In the step 3 of FIG.
After the semiconductor chip 1 is fixed to the metal cover 8W on which all the components are collectively formed and subjected to collective processing such as resin sealing and polishing, the process 8 is performed.
To separate each metal cover 8. When the large metal cover 8 is used, the semiconductor chip 1 may be fixed to the individual metal cover 8.
【００５８】（Ｉ） 図３の工程６で、金属カバー８の
表面にレーザビームを照射して、搭載位置決め用の溝穴
８ｃを設けているが、端子位置の認識ができるものであ
れば、インク等によるマークでも同様に適用可能であ
る。また、搭載位置を正確に示すことができるものであ
ればよく、すべてのバンプ端子６に対応して位置決め用
のマークを施す必要はない、(I) In step 6 of FIG. 3, the surface of the metal cover 8 is irradiated with a laser beam to form the mounting positioning groove 8c. If the terminal position can be recognized, The same applies to marks made with ink or the like. Also, it is only necessary that the mounting position can be accurately indicated, and it is not necessary to provide positioning marks corresponding to all the bump terminals 6.
【００５９】（Ｊ） 図５の半導体装置では、金属カバ
ー８のフランジ部８ｂの周囲に絶縁樹脂によるダム１１
を設けているが、金属カバー８を内側に変形させてダム
を形成するようにしても良い。(J) In the semiconductor device of FIG. 5, the dam 11 made of insulating resin is formed around the flange 8b of the metal cover 8.
However, the metal cover 8 may be deformed inward to form a dam.
【００６０】[0060]
【発明の効果】以上詳細に説明したように、第１の発明
によれば、半導体チップは金属製のカバーの凹部に収容
され、かつこの半導体チップの回路形成面が封止樹脂に
よって封止されている。これにより、Ｓｉ等の半導体基
板が表面に露出することがなく、実装中等に破損するお
それがない。As described above in detail, according to the first aspect, the semiconductor chip is housed in the concave portion of the metal cover, and the circuit forming surface of the semiconductor chip is sealed with the sealing resin. ing. Thereby, the semiconductor substrate of Si or the like is not exposed on the surface, and there is no possibility of being damaged during mounting or the like.
【００６１】第２の発明によれば、封止樹脂をカバーの
凹部の縁と同一の高さまで充填している。これにより、
半導体チップの周囲が完全にカバーと封止樹脂で覆わ
れ、破損のおそれが極めて小さくなる。According to the second aspect, the sealing resin is filled up to the same height as the edge of the concave portion of the cover. This allows
The periphery of the semiconductor chip is completely covered with the cover and the sealing resin, and the possibility of breakage is extremely reduced.
【００６２】第３の発明によれば、半導体チップと金属
製のカバーを導電性の接着剤で接続すると共に、カバー
の縁にも回路基板に固定するためのバンプを設けてい
る。これにより、半導体チップの基板面を所定の電位に
接続することができると共に、良好な放熱効果を得るこ
とができる。According to the third aspect of the present invention, the semiconductor chip and the metal cover are connected with a conductive adhesive, and the edge of the cover is provided with a bump for fixing to the circuit board. Thereby, the substrate surface of the semiconductor chip can be connected to a predetermined potential, and a good heat radiation effect can be obtained.
【００６３】第４の発明によれば、半導体チップを金属
製のカバーに接続するために、金または銀の接着剤を用
いている。これにより、半導体チップをカバーに、電気
的かつ機械的に確実に接続することができる。According to the fourth invention, a gold or silver adhesive is used to connect the semiconductor chip to the metal cover. Thus, the semiconductor chip can be reliably electrically and mechanically connected to the cover.
【００６４】第５の発明によれば、カバーの凹部の縁に
ダムを設け、このダムの内側に樹脂を塗布している。こ
れにより、バンプ端子と電極の接続部が樹脂で覆われる
ので、接続部の酸化による剥がれが防止される。更に、
半導体チップの外部接続用の電極とバンプ端子との間の
温度変化による熱膨張ストレスが樹脂で緩和され、バン
プ端子が熱膨張ストレスによって剥がれるおそれがなく
なる。According to the fifth aspect, a dam is provided at the edge of the concave portion of the cover, and a resin is applied inside the dam. As a result, the connection between the bump terminal and the electrode is covered with the resin, so that the connection is prevented from being peeled off by oxidation. Furthermore,
The thermal expansion stress due to the temperature change between the external connection electrode of the semiconductor chip and the bump terminal is reduced by the resin, and the bump terminal is not likely to be peeled off by the thermal expansion stress.
【００６５】第６の発明によれば、カバーの表面に搭載
位置決め用のマークを付している。これにより、半導体
装置を回路基板の正しい位置に搭載することができる。According to the sixth aspect, a mark for mounting positioning is provided on the surface of the cover. Thus, the semiconductor device can be mounted at a correct position on the circuit board.
【００６６】第７の発明によれば、分割工程において樹
脂で封止される前の半導体ウエハから半導体チップを切
り出すようにしている。これにより、切り出し用の切削
刃が樹脂で目詰まりを起こすことがなく、分割中に半導
体チップが欠けるおそれがない。更に、個々の半導体チ
ップに分割した後、封止処理を行うようにしているの
で、不良の半導体チップに対して樹脂封止を行うという
無駄を排除することができる。According to the seventh aspect, the semiconductor chips are cut out from the semiconductor wafer before being sealed with the resin in the dividing step. Thereby, the cutting blade for cutting does not become clogged with the resin, and there is no possibility that the semiconductor chip is chipped during the division. Furthermore, since the sealing process is performed after the semiconductor chips are divided into individual semiconductor chips, it is possible to eliminate the waste of performing resin sealing on defective semiconductor chips.
【図１】本発明の第１の実施形態を示す半導体装置の概
略の構成図である。FIG. 1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present invention.
【図２】従来の半導体装置の一例を示す概略の構成図で
ある。FIG. 2 is a schematic configuration diagram illustrating an example of a conventional semiconductor device.
【図３】図１の半導体装置の製造方法の工程図である。FIG. 3 is a process chart of the method for manufacturing the semiconductor device of FIG. 1;
【図４】本発明の第２の実施形態を示す半導体装置の概
略の構成図である。FIG. 4 is a schematic configuration diagram of a semiconductor device according to a second embodiment of the present invention.
【図５】本発明の第３の実施形態を示す半導体装置の概
略の構成図である。FIG. 5 is a schematic configuration diagram of a semiconductor device according to a third embodiment of the present invention.
１ 半導体チップ ２ 絶縁膜 ３ Ａｌ電極 ４ Ｃｕ配線 ４ａ 端子表面 ６ バンプ端子 ７ 接着剤 ８ 金属ケース ９ 封止樹脂 １０ Ａｕバンプ端子 １１ ダム １２ 樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Insulating film 3 Al electrode 4 Cu wiring 4a Terminal surface 6 Bump terminal 7 Adhesive 8 Metal case 9 Sealing resin 10 Au bump terminal 11 Dam 12 Resin
Claims (7)
路と外部接続用の複数の電極が形成された半導体チップ
と、 前記半導体チップ全体を収容できる深さの凹部を有する
金属製のカバーと、 前記カバーの凹部の内部底面に前記半導体チップの裏面
を固定する接着剤と、 前記カバー内に固定された前記半導体チップの回路形成
面を封止する封止樹脂と、 加熱溶着によって回路基板に電気的かつ機械的に接続す
るために前記半導体チップの各電極上に形成されたバン
プ端子とを、 備えたことを特徴とする半導体装置。1. A semiconductor chip having a plurality of electrodes for external connection to an integrated circuit formed on a circuit forming surface on a surface of a semiconductor substrate; and a metal cover having a concave portion having a depth capable of accommodating the entire semiconductor chip. An adhesive for fixing the back surface of the semiconductor chip to the inner bottom surface of the concave portion of the cover; a sealing resin for sealing a circuit forming surface of the semiconductor chip fixed in the cover; And a bump terminal formed on each electrode of the semiconductor chip for electrical and mechanical connection.
同一の高さまで充填して前記半導体チップの回路形成面
上を封止するように形成したことを特徴とする請求項１
記載の半導体装置。2. The semiconductor device according to claim 1, wherein the sealing resin is filled up to the same height as the edge of the concave portion of the cover to seal the circuit forming surface of the semiconductor chip.
13. The semiconductor device according to claim 1.
に固定するために該カバーの凹部の縁に前記バンプ端子
と同様のバンプを設けると共に、前記接着剤は導電性を
有するものを用いたことを特徴とする請求項２記載の半
導体装置。3. A bump similar to the bump terminal is provided on an edge of a concave portion of the cover in order to fix the cover to the circuit board by heat welding, and the adhesive has conductivity. 3. The semiconductor device according to claim 2, wherein:
徴とする請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein said adhesive is gold or silver.
ダムを設けると共に、該ダムの内側に樹脂を塗布したこ
とを特徴とする請求項１乃至４のいずれか１つに記載し
た半導体装置。5. The semiconductor according to claim 1, wherein a resin dam is provided around an edge of the concave portion of the cover, and a resin is applied to the inside of the dam. apparatus.
ークを付したことを特徴とする請求項１乃至５のいずれ
か１つに記載した半導体装置。6. The semiconductor device according to claim 1, wherein a mark for mounting positioning is provided on a surface of said cover.
ハを切り出して半導体基板表面の回路形成面上に集積回
路と外部接続用の複数の電極が形成された半導体チップ
に分割する分割工程と凹部を有する金属製のカバーの内
側に前記半導体チップの裏面を接着する接着工程と、 前記カバーの凹部に接着された前記半導体チップを覆う
ように該凹部に封止樹脂を充填する封止工程と、 前記充填した封止樹脂の表面を平らに研磨して前記半導
体チップの電極の表面を露呈させる研磨工程と、 前記研磨工程で露呈させた前記半導体チップの電極の表
面にバンプ端子を搭載する搭載工程とを、 順次行うことを特徴とする半導体装置の製造方法。7. A dividing step for cutting out a semiconductor wafer on which a plurality of integrated circuits are formed and dividing the semiconductor wafer into a semiconductor chip on which a plurality of electrodes for external connection are formed on a circuit forming surface of a semiconductor substrate. A bonding step of bonding the back surface of the semiconductor chip to the inside of a metal cover having: and a sealing step of filling a sealing resin into the recess to cover the semiconductor chip bonded to the recess of the cover, A polishing step of flattening the surface of the filled sealing resin to expose the surface of the electrode of the semiconductor chip, and a mounting step of mounting a bump terminal on the surface of the electrode of the semiconductor chip exposed in the polishing step Are sequentially performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000297838A JP3466145B2 (en) | 2000-09-29 | 2000-09-29 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000297838A JP3466145B2 (en) | 2000-09-29 | 2000-09-29 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002110862A true JP2002110862A (en) | 2002-04-12 |
| JP3466145B2 JP3466145B2 (en) | 2003-11-10 |
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ID=18779886
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000297838A Expired - Fee Related JP3466145B2 (en) | 2000-09-29 | 2000-09-29 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
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| JP (1) | JP3466145B2 (en) |
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| WO2005001929A1 (en) * | 2003-06-30 | 2005-01-06 | Robert Bosch Gmbh | Structural unit comprising a tub-type housing part and casting material arranged therein |
| JP2005116715A (en) * | 2003-10-07 | 2005-04-28 | Casio Comput Co Ltd | Semiconductor device and its manufacturing method |
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