WO1999009592A1 - Flip-chip semiconductor package and method for manufacturing the same - Google Patents

Flip-chip semiconductor package and method for manufacturing the same Download PDF

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Publication number
WO1999009592A1
WO1999009592A1 PCT/JP1998/003588 JP9803588W WO9909592A1 WO 1999009592 A1 WO1999009592 A1 WO 1999009592A1 JP 9803588 W JP9803588 W JP 9803588W WO 9909592 A1 WO9909592 A1 WO 9909592A1
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WIPO (PCT)
Prior art keywords
chip
flip
semiconductor package
chip semiconductor
manufacturing
Prior art date
Application number
PCT/JP1998/003588
Other languages
French (fr)
Japanese (ja)
Inventor
Yoshihiro Ishida
Kiyoshi Shimizu
Shuichi Ishiwata
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Publication of WO1999009592A1 publication Critical patent/WO1999009592A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a small and thin flip-chip semiconductor package in which an IC chip is mounted on a circuit board by flip-chip bonding, and a method of manufacturing the same.
  • FIG. 5 and FIG. 6 as an example of a conventional method of manufacturing a CSP flip-chip semiconductor package, a flip-chip BGA (ball 'Dallid' array) in which solder ball electrodes are formed on a circuit board. ) Is outlined below.
  • a top view is shown on the right side of the drawing, and AA of the top view is shown on the left side of each top view.
  • a cross-sectional view at the cut along the line is shown.
  • 5 and 6 show an example in which four circuit boards 1 are taken for convenience.
  • circuit board forming process ((A) in FIG. 5), an IC chip mounting process ((B) in FIG. 5), and a resin sealing process ((C in FIG. 5)).
  • a reference member attaching step (FIG. 6 (A)
  • a dicing step (FIG. 6 (B)
  • an electrode forming step (FIG. 6 (C)).
  • a through hole (not shown) is formed in the collective circuit board 100 on both sides which is copper-clad.
  • a copper plating layer is formed on both surfaces of the collective circuit board 100 by electroless copper plating and electrolytic copper plating. Further, the copper plating layer is laminated with a plating resist, and the plating resist is sequentially exposed and developed to form a pattern mask. Thereafter, the copper plating layer is subjected to pattern etching using an etchant through the pattern mask. By this pattern etching, the collective circuit board
  • a plurality of IC connection electrodes (bonding patterns) 3 are arranged on the upper surface of the substrate 100, and an external connection electrode 4 which is a pad electrode arranged in a matrix is formed on the bottom surface.
  • a solder resist process is performed to form a resist film on the bottom surface side of the collective circuit board 100.
  • the resist film has an opening exposing the external connection electrode 4 which is a solderable region.
  • the bottom surface of the integrated circuit substrate 100 becomes flat. In this way, an integrated circuit board 100 having a large number of solderable regions of the same shape arranged in a matrix on the bottom surface is completed (FIG. 5 (A)).
  • solder bumps 5 are formed on the pad electrode surfaces of an IC wafer (not shown).
  • the method for forming the solder bump 5 include a method such as a stud bump method, a ball bump method and a plating bump method.
  • the bump method is effective in reducing the size of an IC chip because bumps can be formed in a narrow arrangement between pad electrodes.
  • the IC wafer on which the solder bumps are formed is cut into a predetermined chip size while being adhered to the adhesive tape to form an IC chip 6.
  • the IC wafer is cut in the X and Y directions by a full cutting method using a device such as a dicing saw. Then, the individual IC chips 6 on the adhesive tape are divided into single pieces.
  • a flux (not shown) is placed on a predetermined position on the solder bumps of the divided IC chip 6 or on the IC connection electrode 3 formed on the upper surface side of the above-mentioned integrated circuit board 100. Is applied. Thereafter, one IC chip 6 is mounted for each circuit board 1 on the main surface of the collective circuit board 100. When placing the IC The surface of the chip 6 on which the solder bumps 5 are formed is opposed to the upper surface of the integrated circuit board 100, and the solder bumps 5 are positioned on the IC connection electrodes 3. Subsequently, solder reflow is performed to electrically connect the IC connection electrode 3 and the IC chip 6 respectively. In this way, the IC chip 6 is mounted (flip chip mounting) on the collective circuit board 100 (FIG. 5, (B)).
  • a plurality of IC chips 6 are integrally formed by performing side-botting over a plurality of adjacent IC chips 6 using a thermosetting encapsulating resin 7. Resin sealing. As a result, as shown in FIG. 5 (C), the IC chip 6 is fixed face-down on the individual circuit boards 1 of the collective circuit board 100 in a sealed state.
  • the flat bottom surface of the collective circuit board 100 on which the IC chip 6 is mounted is attached to the reference member 8 by a fixing means such as an adhesive or an adhesive tape.
  • the assembled circuit board 100 and the reference member 8 are securely fixed because the attachment surfaces are flat to each other (FIG. 6 (A)).
  • the collective circuit board 100 is cut along the X- and Y-direction cut lines 2 formed on the collective circuit board 100, respectively. Cutting is performed by first-class cutting means, and the cut circuit board 1 is further divided into individual circuit boards 1.
  • a dicing machine “DFD-640 (trade name)” manufactured by Disco Co., Ltd. was used for dicing, and a 0.1 mm wide dicing blade “NBC” was used as the dicing blade.
  • NBC 0.1 mm wide dicing blade
  • the adhesive or the like is dissolved with a dissolving solution or the like, and the circuit board 1 is peeled from the reference member 8.
  • solder balls are attached to the positions of the external connection electrodes 4 formed on the lower surface side of each circuit board 1. Subsequently, the solder balls are reflowed to form solder ball electrodes 9 as shown in FIG. 6 (C).
  • the melting point of the solder ball is set lower than the melting point of the solder bump 5 so that the solder bump 5 is not melted by the reflow when the solder ball electrode 9 is formed. Therefore, the solder bump 5 has a composition of Pb: 90% and Sn: 10% having a melting point of half of 250 ° C.
  • Pb 40%, melting point of S n 60% of the composition using a solder 1 80 ° C c:
  • FIG. 7 shows a top view of the flip chip BGA10.
  • the side surface of the IC chip 6 is sealed with a sealing resin 7 protruding from directly below the IC chip 6.
  • the portion of the sealing resin 7 protruding to the side is called a fillet.
  • FIG. 8 shows a cross-sectional view taken along a line AA shown in FIG.
  • FIG. 9 shows a cross-sectional view taken along a line BB shown in FIG.
  • the height of the fillet varies depending on the state of the IC chip 6. The reason is that it is difficult to accurately control the height of the fillet during resin sealing. For this reason, as shown in FIG. 9, a part 7 b of the fillet is usually attached to the upper surface of the IC chip 6. If the fillet adheres to the upper surface of the C chip 6, the thickness of the semiconductor package 10 becomes larger.
  • the IC chip is thinned in a wafer state, for example, to a thickness of 0.4 mm, a solder bump for flip chip bonding is attached to the IC chip.
  • the wafer is easily broken.
  • the wafer is easily broken when the wafer is attached to the dicing tape.
  • it has been difficult to reduce the thickness of the IC chip to a certain thickness or less in a wafer state, for example, a thickness of 0.635 mm to 0.4 mm or less. Therefore, it has been difficult to reduce the thickness of the flip-chip semiconductor package to a certain thickness or less, for example, 1 mm or less.
  • the fillet adhering to the upper surface of the IC chip it forces s Atsuta which causes lowering of the reliability ⁇ fe semiconductor Bakkeji.
  • the flip-chip semiconductor package and the method of manufacturing the same provide a thin and highly reliable flip-chip semiconductor package suitable for mounting on a small portable device or the like and a method of manufacturing the same.
  • the lower surface of the IC chip is mounted on the main surface of the circuit board by flip-chip bonding, and the gap between the circuit board and the IC chip is formed.
  • the height of the upper surface of the IC chip with respect to the main surface of the circuit board and the side of the IC chip protruding from the gap.
  • the height of the highest portion of the sealing resin substantially coincides with the height of the sealing resin.
  • the upper surface of the IC chip is a ground surface. Therefore, if a fillet is attached to the upper surface of the IC chip, it is removed by grinding. Therefore, the sealing resin does not adhere to the upper surface of the polished IC chip.
  • the method of manufacturing a flip chip semiconductor package of the present invention Mounting the lower surface of the IC chip on the main surface of the integrated circuit board, which is divided into multiple circuit boards by flip-chip bonding, and sealing the gap between the integrated circuit board and the IC chip and the side surface of the IC chip
  • the method includes a sealing step of sealing with a resin, and a grinding step of grinding the upper surface of the Ic chip after the sealing step.
  • the height of the upper surface of the IC chip with respect to the main surface of the circuit board is substantially equal to the height of the highest portion of the sealing resin that seals the side surface of the IC chip. Let it.
  • the Ic chip can be made thinner. As a result, the thickness of the flip chip semiconductor package can be reduced.
  • the fillet can be removed by grinding to flatten the upper surface of the IC chip.
  • dimensional control of the fillet during resin sealing can be eased.
  • the upper surface of the IC chip can be flattened, the upper surface of the IC chip can be evenly brought into contact with the planar electrode when measuring the electrical characteristics of the flip-chip semiconductor package. For this reason, accurate measurement of electrical characteristics can be performed, and the reliability of the semiconductor package can be improved.
  • the upper surface of each IC chip can be ground at once. As a result, productivity can be improved. Further, the thickness of each IC chip can be made uniform. As a result, the thickness of each flip-chip semiconductor package can be made uniform. In addition, since the grinding is performed in a collective package state, the occurrence of warpage of the flip-chip semiconductor package can be suppressed. Further, it is preferable that the highest part of the sealing resin is a flat surface, and more preferably, the flat surface of the sealing resin surrounds the periphery of the upper surface of the IC chip. Also, it is desirable that the upper surface of the IC chip and the flat surface of the sealing resin are ground surfaces on the same plane.
  • a flat surface of the sealing resin can be used as an upper surface of the flip-chip semiconductor package in addition to the upper surface of the IC chip.
  • the marking area of the flip-chip semiconductor package can be made wider. Therefore, marking can be easily performed. Also, since the area of the top surface of the package is large, the package can be easily picked up by vacuum suction. In addition, when the knockage is fixed on the upper surface, the package can be more reliably fixed because the fixing area is large.
  • Adhesion can be improved as compared with the case where there is a step at the boundary between the upper surface of the substrate and the flat surface of the sealing resin.
  • the height of the ground surface with respect to the main surface of the circuit board is desirably higher than the height of the active element surface of the IC chip.
  • the function of the Ic chip can be prevented from being adversely affected by the grinding of the upper surface.
  • the upper surface of the IC chip and the flat surface of the sealing resin are coated with a protective film.
  • the protective film By providing the protective film in this way, the reliability of the semiconductor package can be improved. Further, by providing the protective coating, the stress applied from the sealing resin to the IC chip can be reduced. As a result, it is possible to avoid adverse effects due to stress on the IC chip, for example, damage to the IC chip. Therefore, the reliability of the flip-chip semiconductor package can be improved.
  • the protective coating covers the boundary between the upper surface of the Ic chip and the flat surface of the sealing resin. If the boundary line is coated with the protective film, the reliability of the semiconductor package can be further improved. Further, it is preferable that the material of the protective film is different from the material of the sealing resin. Thus, providing a protective film of a material different from the material of the sealing resin provides better adhesion of the protective film to the sealing resin than providing the same material as the sealing resin on the surface of the cured sealing resin. Can be improved.
  • FIG. 1 is a cross-sectional view for explaining a method of manufacturing a flip-chip semiconductor package according to a first embodiment of the present invention.
  • FIG. 2 is a top view illustrating the structure of the flip-chip semiconductor package according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the cutout along the line CC in FIG.
  • FIG. 4 relates to a flip-chip semiconductor package according to a second embodiment of the present invention.
  • -It is a sectional view for explaining the structure of the die:
  • FIG. 5 are process diagrams for explaining a conventional method of manufacturing a flip chip semiconductor package
  • ( ⁇ ) is an explanatory diagram of a circuit board forming process
  • (B) is FIG. 4 is an explanatory view of an IC mounting step
  • (C) is an explanatory view of a resin sealing step.
  • a top view is shown on the right side of the drawing, and a cross-sectional view taken along a line AA of the top view is shown on the left side of each top view.
  • the illustration of the IC connection electrode 3 and the external connection electrode 4 is omitted.
  • FIG. 6 are process drawings following (C) of FIG. 5, (A) is an explanatory diagram of an electrode forming process, and (B) is an explanatory diagram of an attaching process. It is a figure and (C) is explanatory drawing of a cutting process.
  • a top view is shown on the right side of the drawing, and a cross-sectional view taken along a line AA of the top view is shown on the left side of each top view.
  • the electrodes 3 for IC connection and Illustration of the external connection electrode 4 is omitted.
  • ⁇ Fig. 7 is a top view of the flip chip semiconductor package.
  • FIG. 8 is a cross-sectional view taken along a line AA in FIG.
  • FIG. 9 is a cross-sectional view taken along a cut line BB in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • the steps up to the sealing step are performed in the same steps as the conventional steps described above. Therefore, description of these steps is omitted.
  • the solder ball electrode 9 is formed on the back surface of the collective circuit board 100 in the same manner as in the conventional example.
  • FIG. 1 is a cross-sectional view for explaining a grinding step.
  • the same components as those in the above-described conventional example are denoted by the same reference numerals.
  • FIG. 1 shows a state in which the solder ball electrodes 9 are formed.
  • the shape of the ground portion of the IC chip 6 and the sealing tree 7 is indicated by a dashed line.
  • the upper surface 6a of the IC chip 6 is ground by a grinding means such as grinding, for example, while keeping the package state.
  • a grinding means such as grinding, for example, while keeping the package state.
  • the height of the upper surface 6c of the IC chip 6 after the grinding is higher than the height of the active element surface (IC circuit forming surface) (not shown) of the IC chip 6. The reason is I This is to prevent the function of the C chip 6 from being adversely affected by the grinding.
  • the thickness of the IC chip 6 becomes from ti to ti as shown in FIG. Then, the thickness t 0 of the semiconductor package 2 0, the thickness ti of the IC chip after grinding, the thickness t 2 of the solder bumps 5, and the thickness t 3 of the circuit board 1, the thickness of the solder ball electrodes 9 is the sum of the t 4.
  • T 1 0 by grinding the thickness of the IC chip 6.
  • the sealing resin does not adhere to the upper surface 6c of the IC chip 6 after the grinding.
  • the upper surface 6c of the IC chip 6 after the grinding is flattened.
  • the dimensional control of the fillet can be eased.
  • the upper surface of the IC chip can be evenly brought into contact with the planar electrode. For this reason, therefore c can measure the precise electrical characteristics, thereby improving the reliability of the semiconductor package.
  • each IC chip 6 can be ground at once, and the thickness of each IC chip 6 can be made uniform. For this reason, productivity can be improved.
  • grinding is performed in a state of being sealed with a resin, occurrence of warpage of the IC chip 6 can be suppressed.
  • FIG. 2 shows the top surface of the flip chip semiconductor package 20 cut out by dicing.
  • FIG. 3 is a cross-sectional view taken along a line C-C in FIG.
  • the sealing resin on the side surface of the IC chip 6 is ground simultaneously with the IC chip 6.
  • the highest part of the sealing resin 7 becomes the flat surface 7a.
  • this flat surface 7a surrounds the periphery of the upper surface 6c of the IC chip 6.
  • the upper surface 6c of the IC chip 6 after cutting and the flat surface 7a of the sealing tree 7 are ground surfaces 6b on the same plane. .
  • the height of the upper surface 6 c of the IC chip 6 with respect to the main surface 1 a of the circuit board 1 and the flat surface 7 of the highest part of the sealing resin sealing the side surface of the IC chip 6 The height of a is practically the same.
  • the flat surface 7a of the sealing resin 7 By forming the flat surface 7a of the sealing resin 7, the flat surface 7a of the sealing resin 7 can be used as the upper surface of the flip chip semiconductor package in addition to the upper surface 6c of the IC chip 6. it can. As a result, the marking area of the flip chip semiconductor package 20 can be made wider. For this reason, marking can be easily performed.
  • the contents to be marked include, for example, the package manufacturer name, manufacturing date, and serial number.
  • the flip-chip semiconductor package 20 can be easily picked up by vacuum suction.
  • the package 20 when the package 20 is fixed on the upper surfaces 6c and 7a, a large fixing area can be secured. Therefore, the package can be fixed more reliably.
  • fixing with the upper surfaces 6c and 7a for example, there is a case where dicing is performed while fixing the IC chip 6 side in an assembled package state.
  • the upper surface 6c of the IC chip 6 and the flat surface 7a of the sealing resin 7 are coated with the protective cover 12 in the coating step.
  • This protective film 12 covers the boundary 11 between the upper surface 6 c of the IC chip 6 and the flat surface 7 a of the sealing resin 7.
  • the reliability of the semiconductor package 20a can be improved.
  • coating on the boundary 11 prevents the occurrence of a gap between the IC chip 6 and the sealing resin 7 at the boundary 11, thereby improving reliability. It can be further improved.
  • the protective film 12 the stress applied from the sealing resin 7 to the IC chip 6 can be reduced. As a result, it is possible to avoid adverse effects due to stress on the IC chip 6, for example, damage to the IC chip. For this reason, the word order i of the flip chip semiconductor package 20a can be improved.
  • JCR junction coating range
  • marking is performed by shaving the protected layer 12 with a laser beam.
  • marking is performed using a laser beam
  • the contents of the marking can be changed more easily than when marking is performed by printing.
  • the protective coating # 2 is opaque. Therefore, it is possible to improve the contrast between the opaque protective coating 12 and the chipped portion where the upper surface 6 ′ of the IC chip 6 is exposed: As a result, the visibility of the marking is improved. Can be up.
  • the grinding step is performed before each flip-chip semiconductor package is cut out by dicing.
  • the grinding step may be performed after the dicing step.
  • the flip-chip semiconductor package according to the present invention and the method for manufacturing the same are provided as a flip-chip semiconductor package mounted on a camera-integrated VTR, a small portable device, or the like and having excellent reliability and productivity and a method for manufacturing the same. It is suitable.

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Abstract

An IC chip (6) is flip-chip bonded to a major surface of a collective circuit board (100) and encapsulated with resin and then the upper surface (6a) of the IC chip (6) is ground in a state of a collective package. The upper surface (6a) of the IC chip is made flush with the flat surface (7a) of the highest part of the encapsulating resin. The semiconductor package can be thinned and the area of the upper surface thereof, as a marking region, can be made wider than the area of only the upper surface of the IC chip.

Description

明 細 書 ' フリップチップ半導体パッケージおよびその製造方法 技術分野  Description '' Flip chip semiconductor package and its manufacturing method
本発明は、 回路基板上に I Cチップがフリップチップボンディングにより実装 された、 小型かつ薄型のフリッブチップ半導体パッケージおよびその製造方法に 関するものである。 背景技術  The present invention relates to a small and thin flip-chip semiconductor package in which an IC chip is mounted on a circuit board by flip-chip bonding, and a method of manufacturing the same. Background art
フリップチップ半導体パッケージの小型化、 高密度化に伴い、 ベア ·チップを 直接フェイスダウンで基板上に実装するフリップチップボンディングが開発され ている。 さらに近年、 カメラ一体型 V T Rや携帯電話等のベア 'チップとほぼ同 じ寸法の小型パッケージ、 いわゆる c s p (チップサイズ Zスケール ·パッケ一 ジ） を搭載した携帯機器が相次いで登場してきている。 このような事情から、 C S Pに対する市場要求が本格化し、 このため、 最近は C S Pの開発が急速に進ん でいる。  With the miniaturization and higher density of flip-chip semiconductor packages, flip-chip bonding, in which bare chips are directly mounted face down on a substrate, has been developed. Furthermore, in recent years, portable devices equipped with a so-called csp (chip size Z scale package), which is a small package having almost the same dimensions as a bare chip such as a camera-integrated VTR and a mobile phone, have been appearing one after another. Under these circumstances, the market demand for the CSP has been in full swing, and the development of the CSP has recently been progressing rapidly.
ここで、 第 5図および第 6図を参照して、 従来の、 C S Pのフリップチップ半 導体パッケージの製造方法一例として、 回路基板に半田ボール電極が形成された フリップチップ B G A (ボール 'ダリッド'アレイ） の製造方法について概説する。 第 5図の （A) 〜 （C) および第 6図の （A) 〜 （C) においては、 図面の右側 に上面図をそれぞれ示し、 各上面図の左側にその上面図の A— Aに沿った切り口 における断面図をそれぞれ示す。 なお、第 5図および第 6図においては、便宜上、 回路基板 1を 4個取りする例を示す。  Here, referring to FIG. 5 and FIG. 6, as an example of a conventional method of manufacturing a CSP flip-chip semiconductor package, a flip-chip BGA (ball 'Dallid' array) in which solder ball electrodes are formed on a circuit board. ) Is outlined below. In (A) to (C) of FIG. 5 and (A) to (C) of FIG. 6, a top view is shown on the right side of the drawing, and AA of the top view is shown on the left side of each top view. A cross-sectional view at the cut along the line is shown. 5 and 6 show an example in which four circuit boards 1 are taken for convenience.
従来のフリップチップ半導体パッケージの製造工程は、 回路基板形成工程 （第 5図の （A) )、 I Cチップ実装工程 （第 5図の （B ) )、 樹脂封止工程 （第 5図の ( C) )、基準部材張り付け工程（第 6図の（ A) )、ダイシング工程（第 6図の（ B ) ) および電極形成工程 （第 6図の （C) ) とを含む。  Conventional flip-chip semiconductor package manufacturing processes include a circuit board forming process ((A) in FIG. 5), an IC chip mounting process ((B) in FIG. 5), and a resin sealing process ((C in FIG. 5)). )), A reference member attaching step (FIG. 6 (A)), a dicing step (FIG. 6 (B)), and an electrode forming step (FIG. 6 (C)).
フリップチップ半導体パッケージの製造に当たり、 まず、 回路基板形成工程に おいて、 両面が銅張りされた集合回路基板 1 o 0にスルーホール （図示せず） を 形成する。 In manufacturing flip-chip semiconductor packages, first, in the circuit board formation process Then, a through hole (not shown) is formed in the collective circuit board 100 on both sides which is copper-clad.
次に、 この集合回路基板 1 0 0の両面に、 無電解銅メツキおよび電解銅メツキ により銅メツキ層を形成する。 さらに、 銅メツキ層をメツキレジストでラミネー トし、 このメツキレジストを順次に露光および現像してパターンマスクを形成す る。 その後、 このパターンマスクを介して銅メツキ層に対してエッチング液を用 いたパターンエッチングを行う。 このパターンエッチングにより、 集合回路基板 Next, a copper plating layer is formed on both surfaces of the collective circuit board 100 by electroless copper plating and electrolytic copper plating. Further, the copper plating layer is laminated with a plating resist, and the plating resist is sequentially exposed and developed to form a pattern mask. Thereafter, the copper plating layer is subjected to pattern etching using an etchant through the pattern mask. By this pattern etching, the collective circuit board
1 0 0の上面側には複数個分配列した I C接続用電極 （ボンディングパタン） 3 を、 また、 底面側にはマトリックス状に配置されたパッド電極である外部接続用 電極 4をそれぞれ形成する。 A plurality of IC connection electrodes (bonding patterns) 3 are arranged on the upper surface of the substrate 100, and an external connection electrode 4 which is a pad electrode arranged in a matrix is formed on the bottom surface.
続いて、 ソルダーレジスト処理を行って、 集合回路基板 1 0 0の底面側にレジ ス ト膜を形成する。 このレジスト膜は、 半田付け可能な領域である外部接続用電 極 4を露出させた開口部を有する。 このレジスト膜を形成することにより、 集合 回路基板 1 0 0の底面は平坦となる。 このようにして、 底面に多数の同一形状の 半田付け可能な領域がマトリックス状に配置された、 集合回路基板 1 0 0が完成 する （第 5図の （A) )。  Subsequently, a solder resist process is performed to form a resist film on the bottom surface side of the collective circuit board 100. The resist film has an opening exposing the external connection electrode 4 which is a solderable region. By forming this resist film, the bottom surface of the integrated circuit substrate 100 becomes flat. In this way, an integrated circuit board 100 having a large number of solderable regions of the same shape arranged in a matrix on the bottom surface is completed (FIG. 5 (A)).
次に、 I Cチップ実装工程では、 まず、 I Cウェハ （図示せず） のパッド電極 面に半田バンプ 5を形成する。 この半田バンプ 5の形成方法には、 例えば、 スタ ッドバンプ方式、 ボ一ルバンプ方式およびメツキバンプ方式等の方法がある。 こ れらの方法のうち、 メツキバンプ方式は、 パッド電極間の狭い配列でバンプを形 成することが可能なため、 I Cチップの小型化に有効である。  Next, in the IC chip mounting step, first, solder bumps 5 are formed on the pad electrode surfaces of an IC wafer (not shown). Examples of the method for forming the solder bump 5 include a method such as a stud bump method, a ball bump method and a plating bump method. Among these methods, the bump method is effective in reducing the size of an IC chip because bumps can be formed in a narrow arrangement between pad electrodes.
続いて、 半田バンプを形成した I Cウェハを、 粘着テープに貼着した状態で所 定のチップサイズに切断して、 I Cチップ 6を形成する。 切断にあたっては、 ダ イシングソ一等の装置を用いて I Cウェハをフルカツト方式で X、 Y方向に切削 する。 その後、 粘着テープ上の個々の I Cチップ 6を単体に分割する。  Subsequently, the IC wafer on which the solder bumps are formed is cut into a predetermined chip size while being adhered to the adhesive tape to form an IC chip 6. When cutting, the IC wafer is cut in the X and Y directions by a full cutting method using a device such as a dicing saw. Then, the individual IC chips 6 on the adhesive tape are divided into single pieces.
続いて、 この分割された I Cチップ 6の半田バンプ上または前述した集合回路 基板 1 0 0の上面側に形成された I C接続用電極 3上のいずれかの所定位置に、 フラックス （図示せず） を塗布する。 その後、集合回路基板 1 0 0の主表面上に、 回路基板 1ごとに I Cチップ 6を一個づっ搭載する。 載置にあたっては、 I Cチ ップ 6の半田バンプ 5が形成された面側を集合回路基板 1 0 0の上面側と対向さ せ、 かつ、 半田バンプ 5を I C接続用電極 3上に位置させる。 続いて、 半田リフ ローを行って、 I C接続用電極 3とこの I Cチップ 6とをそれぞれ電気的に接続 する。 このようにして、 集合回路基板 1 0 0上に、 I Cチップ 6の実装 （フリツ プチップ実装） を行う （第 5図の （B ) )。 Subsequently, a flux (not shown) is placed on a predetermined position on the solder bumps of the divided IC chip 6 or on the IC connection electrode 3 formed on the upper surface side of the above-mentioned integrated circuit board 100. Is applied. Thereafter, one IC chip 6 is mounted for each circuit board 1 on the main surface of the collective circuit board 100. When placing the IC The surface of the chip 6 on which the solder bumps 5 are formed is opposed to the upper surface of the integrated circuit board 100, and the solder bumps 5 are positioned on the IC connection electrodes 3. Subsequently, solder reflow is performed to electrically connect the IC connection electrode 3 and the IC chip 6 respectively. In this way, the IC chip 6 is mounted (flip chip mounting) on the collective circuit board 100 (FIG. 5, (B)).
次に、 封止工程では、 熱硬化性の封止樹脂 7を用いて、 隣接する複数個の I C チップ 6にまたがつたサイドボッティングを行うことにより、 複数個の I Cチッ プ 6を一体的に樹脂封止する。 これにより、 I Cチップ 6は、 第 5図の （C) に 示すように、 フェイスダウンで集合回路基板 1 0 0の個々の回路基板 1上に封止 された状態で固定される c  Next, in the encapsulation step, a plurality of IC chips 6 are integrally formed by performing side-botting over a plurality of adjacent IC chips 6 using a thermosetting encapsulating resin 7. Resin sealing. As a result, as shown in FIG. 5 (C), the IC chip 6 is fixed face-down on the individual circuit boards 1 of the collective circuit board 100 in a sealed state.
次に、 基準部材張り付け工程では、 I Cチップ 6を実装した集合回路基板 1 0 0の平坦な底面を、 基準部材 8上に接着剤または粘着テープなどの固定手段で張 り付ける。 集合回路基板 1 0 0と基準部材 8とは、 張り付け面が互いに平坦なた め、 確実に固定される （第 6図の （A) )。  Next, in the reference member attaching step, the flat bottom surface of the collective circuit board 100 on which the IC chip 6 is mounted is attached to the reference member 8 by a fixing means such as an adhesive or an adhesive tape. The assembled circuit board 100 and the reference member 8 are securely fixed because the attachment surfaces are flat to each other (FIG. 6 (A)).
次に、 ダイシング工程では、 第 6図の （B ) に示すように、 集合回路基板 1 0 0を、 この集合回路基板 1 0 0に形成した X方向および Y方向のカツトライン 2 にそれぞれ沿ってダイシングソ一等の切削手段で切削し、 さらに切削された回路 基板 1を個々の回路基板 1に分割する。 ここでは、 ダイシングに当たり、 株式会 社ディスコ製のダイシング機 「D F D— 6 4 0 (商品名）」 を使用し、 また、 ダ ィシングブレードとしては、 幅 0 . 1 mmのダイシングブレ一ド 「N B C— Z B 1 0 9 0 S 3 (商品名）」 を使用する。  Next, in the dicing step, as shown in FIG. 6 (B), the collective circuit board 100 is cut along the X- and Y-direction cut lines 2 formed on the collective circuit board 100, respectively. Cutting is performed by first-class cutting means, and the cut circuit board 1 is further divided into individual circuit boards 1. Here, a dicing machine “DFD-640 (trade name)” manufactured by Disco Co., Ltd. was used for dicing, and a 0.1 mm wide dicing blade “NBC” was used as the dicing blade. — ZB 1 0 9 0 S 3 (brand name) ”.
その後、 溶解液等により接着剤等を溶解して、 回路基板 1を基準部材 8から剥 離する。  Thereafter, the adhesive or the like is dissolved with a dissolving solution or the like, and the circuit board 1 is peeled from the reference member 8.
次に、 電極形成工程では、 まず、 個々の回路基板 1の下面側に形成された外部 接続用電極 4の配置位置に、 それぞれ半田ボールを付ける。 続いて、 半田ボール をリフローして、 第 6図の （C) 示すように、 半田ボール電極 9を形成する。 なお、 半田ボール電極 9を形成する際のリフローにより半田バンプ 5が融けな いように、半田ボールの融点は、 半田バンプ 5の融点よりも低くする。そのため、 半田バンプ 5には、 P b ： 9 0 %、 S n ： 1 0 %の組成の融点が 2 5 0 °Cの半 田を使用し、 一方、 半田ボールには、 Pb ： 40%、 S n 60 %の組成の融点が 1 80°Cの半田を使用する c: Next, in the electrode forming step, first, solder balls are attached to the positions of the external connection electrodes 4 formed on the lower surface side of each circuit board 1. Subsequently, the solder balls are reflowed to form solder ball electrodes 9 as shown in FIG. 6 (C). Note that the melting point of the solder ball is set lower than the melting point of the solder bump 5 so that the solder bump 5 is not melted by the reflow when the solder ball electrode 9 is formed. Therefore, the solder bump 5 has a composition of Pb: 90% and Sn: 10% having a melting point of half of 250 ° C. Using the field, whereas, in the solder balls, Pb: 40%, melting point of S n 60% of the composition using a solder 1 80 ° C c:
以上の工程を経て個々のフリップチップ半導体パッケージの一例としてのフリ ップチップ B G A (ボール 'グリッド 'アレイ） 1 ()を完成する。  Through the above steps, a flip chip BGA (ball 'grid' array) 1 () as an example of an individual flip chip semiconductor package is completed.
次に、 図 7に、 フリップチップ BGA10の上面図を示す。 図 7に示すように、 I Cチップ 6の側面は、 I Cチップ 6の直下からはみ出した封止樹脂 7によって 封止されている。 側面へはみ出した部分の封止樹脂 7をフィレットと称する。 次に、 図 8に、 図 7に示す A— Aに沿った切り口における断面図を示す。 図 8 に示すように、 I Cチップ 6の厚さは T\= 0. 4 mmであり、 封止高さ、 すな わち、 半田バンプの厚さは T2=0. 05mmであり、 回路基板 1の厚さは T3 = (). 28mmであり、 半田ボ一ル 9の厚さは丁4 = 0. 4mmである。 したが つて、 半導体パッケージ 10の厚さは、 T。 = T】 +T2 + T3 + T4= 1. 1 3m mとなる。 すなわち、 従来の半導体パッケージ 10の厚さは、 1mmを超えてし まう。 Next, FIG. 7 shows a top view of the flip chip BGA10. As shown in FIG. 7, the side surface of the IC chip 6 is sealed with a sealing resin 7 protruding from directly below the IC chip 6. The portion of the sealing resin 7 protruding to the side is called a fillet. Next, FIG. 8 shows a cross-sectional view taken along a line AA shown in FIG. As shown in FIG. 8, the thickness of the IC chip 6 is T = 0.4 mm, the sealing height, that is, the thickness of the solder bump is T 2 = 0.05 mm, and the circuit The thickness of the substrate 1 is T 3 = (). 28 mm, and the thickness of the solder ball 9 is T 4 = 0.4 mm. Therefore, the thickness of the semiconductor package 10 is T. = T] + T 2 + T 3 + T 4 = 1.13 mm. That is, the thickness of the conventional semiconductor package 10 exceeds 1 mm.
また、 図 9に、 図 7に示す B— Bに沿った切り口における断面図を示す。 図 8 および図 9に示すように、 I Cチップ 6の各侧而によって、 フィレッ トの高さは ばらついている。 その理由は、 樹脂封止の際に、 フィレツ 卜の高さを正確に制御 することが困難なためである。 このため、 図 9に示すように、 通常、 フィレット の一部分 7 bは、 I Cチップ 6の上面に付 する。 】 Cチップ 6の上面にフィレ ットが付着すれば、 半導体パッケージ 10の厚さは一層厚くなる。  FIG. 9 shows a cross-sectional view taken along a line BB shown in FIG. As shown in FIGS. 8 and 9, the height of the fillet varies depending on the state of the IC chip 6. The reason is that it is difficult to accurately control the height of the fillet during resin sealing. For this reason, as shown in FIG. 9, a part 7 b of the fillet is usually attached to the upper surface of the IC chip 6. If the fillet adheres to the upper surface of the C chip 6, the thickness of the semiconductor package 10 becomes larger.
ところで、近年、小型携帯用機器に一層の小型化が要求されている。その結果、 この小型携帯用機器に搭載されるフリツプチップ半導体パッケージに対しても、 より一層の小型化および薄型化が要求されている。 フリップチップ半導体パッケ 一ジの厚さを例えば 1 mm以下にすることが要求されている。  By the way, in recent years, further miniaturization of small portable devices has been demanded. As a result, even smaller and thinner flip-chip semiconductor packages mounted on such small portable devices are required. Flip-chip semiconductor packages are required to have a thickness of, for example, 1 mm or less.
ところが、 フリップチップ半導体パッケージを薄型化するために、 半田ボール 電極、 回路基板および半田バンプの厚さをこれ以上薄くすることは困難である。 そこで、 I Cチップを薄型化することが考えられる。  However, it is difficult to further reduce the thickness of the solder ball electrode, the circuit board and the solder bump in order to make the flip chip semiconductor package thinner. Therefore, it is conceivable to reduce the thickness of the IC chip.
しかしながら、 I Cチップをウェハーの状態で薄くすると、 例えば 0. 4mm の厚さまで薄くすると、 I Cチップにフリップチップボンディング用の半田バン プを形成する際に、 ウェハーが割れやすくなる。 また、 ウェハーをさらに薄くす ると、 ウェハーをダイシングテープに貼着する際に、 ウェハーが割れ易くなる。 このため、 I Cチップをウェハー状態で一定の厚さ以下、 例えば、 0 . 6 3 5 m m〜0 . 4 mmの厚さ以下に薄型化することは困難であった。 したがって、 フリ ップチップ半導体パッケージを一定の厚さ以下、 例えば 1 mmの厚さ以下に薄型 化することは困難であった。 However, if the IC chip is thinned in a wafer state, for example, to a thickness of 0.4 mm, a solder bump for flip chip bonding is attached to the IC chip. When forming a wafer, the wafer is easily broken. Further, when the wafer is further thinned, the wafer is easily broken when the wafer is attached to the dicing tape. For this reason, it has been difficult to reduce the thickness of the IC chip to a certain thickness or less in a wafer state, for example, a thickness of 0.635 mm to 0.4 mm or less. Therefore, it has been difficult to reduce the thickness of the flip-chip semiconductor package to a certain thickness or less, for example, 1 mm or less.
また、 I Cチップの上面の一部分にフィレツ 卜が付着すると、 フリップチップ 半導体パッケージの厚さが厚くなるだけでなく、 I Cチップの上面に段差ができ る。 その結果、 フリップチップ半導体パッケージの電気特性の測定を行う際に、 I Cチップの上面を平面電極に均等に接触させること困難となる。 このため、 正 確な電気特性の測定を行うことが困難となる。 したがって、 I Cチップの上面に 付着したフィレットは、 半導体バッケージの信頼 ^feを低下させる原因となること 力 sあつた。 Also, if the fillet adheres to a part of the upper surface of the IC chip, not only does the thickness of the flip chip semiconductor package increase, but also a step is formed on the upper surface of the IC chip. As a result, when measuring the electrical characteristics of the flip-chip semiconductor package, it is difficult to evenly contact the top surface of the IC chip with the planar electrode. For this reason, it is difficult to measure the electrical characteristics accurately. Accordingly, the fillet adhering to the upper surface of the IC chip, it forces s Atsuta which causes lowering of the reliability ^ fe semiconductor Bakkeji.
したがって、 本発明に係るフリップチップ半導体パッケージおよびその製造方 法は、 上述の問題にかんがみ、 小型携帯機器等に搭載して好適な、 信頼性に優れ た薄型のフリップチップ半導体パッケージおよびその製造方法の提供を目的とす  Accordingly, in view of the above-described problems, the flip-chip semiconductor package and the method of manufacturing the same according to the present invention provide a thin and highly reliable flip-chip semiconductor package suitable for mounting on a small portable device or the like and a method of manufacturing the same. To provide
発明の開示 Disclosure of the invention
この発明のフリップチップ半導体パッケージ （以下、 単に 「パッケージ」 とも 略称する。） によれば、 回路基板の主表面に I Cチップの下面をフリップチップ ボンディングにより実装し、 この回路基板と I Cチップとの空隙に封止樹脂を注 入して、 当該空隙を封止したフリップチップ半導体パッケージにおいて、 回路基 板の主表面を基準とした、 I Cチップの上面の高さと、 空隙から I Cチップの側 面にはみ出した封止樹脂の最高部の高さとが実質的に一致した構成としてある。 また、 I Cチップの上面は、 研削面としてある。 このため、 I Cチップの上面 に、 フィレットが付着している場合には研削により除去される。 したがって、 研 削後の I Cチップの上面には、 封止樹脂は付着していない。  According to the flip-chip semiconductor package of the present invention (hereinafter simply referred to as “package”), the lower surface of the IC chip is mounted on the main surface of the circuit board by flip-chip bonding, and the gap between the circuit board and the IC chip is formed. In the flip-chip semiconductor package in which the gap is sealed, the height of the upper surface of the IC chip with respect to the main surface of the circuit board and the side of the IC chip protruding from the gap. The height of the highest portion of the sealing resin substantially coincides with the height of the sealing resin. The upper surface of the IC chip is a ground surface. Therefore, if a fillet is attached to the upper surface of the IC chip, it is removed by grinding. Therefore, the sealing resin does not adhere to the upper surface of the polished IC chip.
また、 この発明のフリップチップ半導体パッケージの製造方法によれば、 切断 により複数個の回路基板に分けられる集合回路基板の主表面に I Cチップの下面 をフリップチップボンディングにより実装する実装工程と、 この集合回路基板と I Cチップとの空隙および当該 I Cチップの側面を封止樹脂により封止する封止 工程と、 封止工程の後に、 I cチップの上面を研削する研削工程とを含む方法と してある。 According to the method of manufacturing a flip chip semiconductor package of the present invention, Mounting the lower surface of the IC chip on the main surface of the integrated circuit board, which is divided into multiple circuit boards by flip-chip bonding, and sealing the gap between the integrated circuit board and the IC chip and the side surface of the IC chip The method includes a sealing step of sealing with a resin, and a grinding step of grinding the upper surface of the Ic chip after the sealing step.
また研削工程において、 前記回路基板の主表面を基準とした、 前記 I Cチップ の上面の高さと、 前記 I Cチップの側面を封止した前記封止樹脂の最高部の高さ とを実質的に一致させる。  In the grinding step, the height of the upper surface of the IC chip with respect to the main surface of the circuit board is substantially equal to the height of the highest portion of the sealing resin that seals the side surface of the IC chip. Let it.
このように、 I cチップの上面を研削して、 この上面の高さと封止樹脂の最高 部の高さとを実質的に一致させることにより、 I cチップを薄型化できる。 その 結果、 フリップチップ半導体パッケージを薄型化することができる。  In this way, by grinding the upper surface of the Ic chip and making the height of the upper surface substantially equal to the height of the highest portion of the sealing resin, the Ic chip can be made thinner. As a result, the thickness of the flip chip semiconductor package can be reduced.
また、 樹脂封止の際に I Cチップの上面にフィレツトが付着して段差が生じて も、 研削によりこのフィレットを除去して、 I cチップの上面を平坦化すること ができる。 その結果、 樹脂封止の際にフィレットの寸法管理を緩和することがで きる。 その上、 I cチップの上面を平坦化できるので、 フリップチップ半導体パ ッケージの電気特性の測定を行う際に、 I Cチップの上面を平面電極に均等に接 触させることができる。 このため、 正確な電気特性の測定を行うことができるの で、 半導体パッケージの信頼性を向上させることができる。  Further, even if a fillet adheres to the upper surface of the IC chip at the time of resin sealing and a step is generated, the fillet can be removed by grinding to flatten the upper surface of the IC chip. As a result, dimensional control of the fillet during resin sealing can be eased. In addition, since the upper surface of the IC chip can be flattened, the upper surface of the IC chip can be evenly brought into contact with the planar electrode when measuring the electrical characteristics of the flip-chip semiconductor package. For this reason, accurate measurement of electrical characteristics can be performed, and the reliability of the semiconductor package can be improved.
その上、 樹脂封止後に I Cチップの上面を研削するので、 製造過程において I cチップが割れるおそれが小さい。 このため、生産性を向上させることができる。 また、 I Cチップが割れるおそれが小さければ、 歩留まりを向上させることがで きる。 このため、 製造コストを低下して安価なフリップチップ半導体パッケージ を提供することができる  In addition, since the upper surface of the IC chip is ground after resin sealing, the risk of the IC chip breaking during the manufacturing process is small. For this reason, productivity can be improved. Also, if the risk of breaking the IC chip is small, the yield can be improved. Therefore, it is possible to provide an inexpensive flip-chip semiconductor package with reduced manufacturing cost.
また、 切断工程の前の集合パッケージの状態で、 各 I Cチップの上面を研削す れば、 各 I Cチップの上面を一度に研削することができる。 その結果、 生産性を 向上させることができる。また、各 I cチップの厚さを均一にすることができる。 その結果、各フリツプチップ半導体パッケージの厚さを均一にすることができる。 また、 集合パッケージ状態で研削を行うので、 フリップチップ半導体パッケージ の反りの発生を抑制できる。 また、 封止樹脂の最高部を平坦面とすると良く、 より好ましくは、 封止樹脂の 平坦面が、前記 I Cチップの上面の周囲を取り囲んでいることが望ましい。また、 I Cチップの上面と、 封止樹脂の平坦面とが、 同一平面上の研削面であることが 望ましい。 Also, by grinding the upper surface of each IC chip in the state of the collective package before the cutting process, the upper surface of each IC chip can be ground at once. As a result, productivity can be improved. Further, the thickness of each IC chip can be made uniform. As a result, the thickness of each flip-chip semiconductor package can be made uniform. In addition, since the grinding is performed in a collective package state, the occurrence of warpage of the flip-chip semiconductor package can be suppressed. Further, it is preferable that the highest part of the sealing resin is a flat surface, and more preferably, the flat surface of the sealing resin surrounds the periphery of the upper surface of the IC chip. Also, it is desirable that the upper surface of the IC chip and the flat surface of the sealing resin are ground surfaces on the same plane.
このようにすれば、 フリツプチップ半導体パッケージの上面として、 I Cチッ プの上面に加えて、 封止樹脂の平坦面も利用することができる。 その結果、 フリ ップチップ半導体パッケージのマ一キング領域をより広く取ることができる。 こ のため、 マ一キングを容易に行うことができる。 また、 パッケージの上面の面積 が広いので、 パッケージを真空吸着により容易にピックアップできる。 また、 ノ ッケージをその上面で固定する場合には、 固定面積が広いため、 パッケージをよ り確実に固定することができる。  In this way, a flat surface of the sealing resin can be used as an upper surface of the flip-chip semiconductor package in addition to the upper surface of the IC chip. As a result, the marking area of the flip-chip semiconductor package can be made wider. Therefore, marking can be easily performed. Also, since the area of the top surface of the package is large, the package can be easily picked up by vacuum suction. In addition, when the knockage is fixed on the upper surface, the package can be more reliably fixed because the fixing area is large.
また、 I Cチップの上面と封止樹脂の平坦面とが、 同一平面上の研削面であれ ば、 I Cチップの上面および封止樹脂の平坦面上に、 保護被膜を形成する際に、 I Cチップの上面と封止樹脂の平坦面との境界に段差がある場合よりも密着性を 向上させることができる。  If the upper surface of the IC chip and the flat surface of the encapsulating resin are ground surfaces on the same plane, when forming the protective film on the upper surface of the IC chip and the flat surface of the encapsulating resin, Adhesion can be improved as compared with the case where there is a step at the boundary between the upper surface of the substrate and the flat surface of the sealing resin.
また、 回路基板の主表面を基準とした、 研削面の高さは、 前記 I Cチップの能 動素子面の高さよりも高いことが望ましい。 このように、 研削面の高さを能動素 子面の高さよりも高くすれば、 I cチップの機能が上面の研削により悪影響を受 けることを回避できる。  Further, the height of the ground surface with respect to the main surface of the circuit board is desirably higher than the height of the active element surface of the IC chip. Thus, if the height of the ground surface is made higher than the height of the active device surface, the function of the Ic chip can be prevented from being adversely affected by the grinding of the upper surface.
また、 I Cチップの上面および封止樹脂の平坦面が、 保護被膜によりコ一ティ ングされることが望ましい。 このように保護被膜を設ければ、 半導体パッケージ の信頼性を向上させることができる。 さらに、 保護被膜を設けることにより、 封 止樹脂から I Cチップへ印加される応力を緩和することができる。 その結果、 I Cチップに対する応力による悪影響、 例えば、 I cチップの破損を回避すること ができる。 このため、 フリツプチップ半導体パッケージの信頼性を向上させるこ とができる。  In addition, it is desirable that the upper surface of the IC chip and the flat surface of the sealing resin are coated with a protective film. By providing the protective film in this way, the reliability of the semiconductor package can be improved. Further, by providing the protective coating, the stress applied from the sealing resin to the IC chip can be reduced. As a result, it is possible to avoid adverse effects due to stress on the IC chip, for example, damage to the IC chip. Therefore, the reliability of the flip-chip semiconductor package can be improved.
また、 保護被膜が、 I cチップの上面と封止樹脂の平坦面との境界線上を覆う ことが望ましい。 このように境界線上が保護被膜によりコ一ティングされていれ ば、 半導体パッケージの信頼性を一層向上させることができる。 また、 保護被膜の材料を、 封止樹脂の材料とは異なることが好ましい。 このよ うに、 封止樹脂の材料と異なる材料の保護被膜を設ければ、 硬化した封止樹脂の 表面に、 封止樹脂と同一材料を設ける場合よりも、 封止樹脂に対する保護被膜の 密着性を向上させることができる。 Further, it is desirable that the protective coating covers the boundary between the upper surface of the Ic chip and the flat surface of the sealing resin. If the boundary line is coated with the protective film, the reliability of the semiconductor package can be further improved. Further, it is preferable that the material of the protective film is different from the material of the sealing resin. Thus, providing a protective film of a material different from the material of the sealing resin provides better adhesion of the protective film to the sealing resin than providing the same material as the sealing resin on the surface of the cured sealing resin. Can be improved.
また、 保護被膜をレーザ光線により削ることにより、 マ一キングを行うこと力 S 望ましい。 このように、 保護被膜にレーザ光線によりマーキングを行えば、 印刷 によりマーキングを行う場合に比べて、 マーキング內容を容易に変更することが できる。 図面の簡単な説明  Also, it is desirable to perform masking by shaving the protective film with a laser beam. As described above, when marking is performed on the protective film with a laser beam, the marking content can be changed more easily than when marking is performed by printing. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の第 1の実施の形態に係わり、 フリツプチップ半導体パッケ —ジの製造方法を説明するための断面図である，  FIG. 1 is a cross-sectional view for explaining a method of manufacturing a flip-chip semiconductor package according to a first embodiment of the present invention.
第 2図は、 本発明の第 1の実施の形態に係わり、 フリツプチップ半導体パッケ ージの構造を説明するための上面図である  FIG. 2 is a top view illustrating the structure of the flip-chip semiconductor package according to the first embodiment of the present invention.
第 3図は、 第 2図の C— Cに沿った切り口におけろ断面図である。  FIG. 3 is a cross-sectional view of the cutout along the line CC in FIG.
第 4図は、 本発明の第 2の実施の形態に係わり、 フリップチップ半導体パッケ FIG. 4 relates to a flip-chip semiconductor package according to a second embodiment of the present invention.
—ジの構造を説明するための断面図である:. -It is a sectional view for explaining the structure of the die:
第 5図の （A) 〜 （C) は、 従来のフリ ツフチップ半導体パッケージの製造方 法の説明に供する工程図であり、 （ Λ ) は、 回路基板形成工程の説明図であり、 ( B ) は、 I C実装工程の説明図であり、 （C ) は、 樹脂封止工程の説明図であ る。 （A) 〜 （C) においては、 図面の右側に上面図をそれぞれ示し、 各上面図 の左側にその上面図の A— Aに沿った切り口における断面図をそれぞれ示す。 ま た、 （B ) および （C) においては、 I C接続用電極 3および外部接続用電極 4 の図示を省略する。  (A) to (C) of FIG. 5 are process diagrams for explaining a conventional method of manufacturing a flip chip semiconductor package, (説明) is an explanatory diagram of a circuit board forming process, and (B) is FIG. 4 is an explanatory view of an IC mounting step, and (C) is an explanatory view of a resin sealing step. In (A) to (C), a top view is shown on the right side of the drawing, and a cross-sectional view taken along a line AA of the top view is shown on the left side of each top view. In (B) and (C), the illustration of the IC connection electrode 3 and the external connection electrode 4 is omitted.
第 6図の （A) 〜 （C) は、 第 5図の （C ) に続く工程図であり、 （A) は、 電極形成工程の説明図であり、 （B ) は、張り付け工程の説明図であり、 （C ) は、 切断工程の説明図である。 （A) 〜 （C) においては、 図面の右側に上面図をそ れぞれ示し、 各上面図の左側にその上面図の A— Aに沿った切り口における断面 図をそれぞれ示す。 なお、 （A) 〜 （C) においては、 I C接続用電極 3および 外部接続用電極 4の図示を省略する。 · 第 7図は、 フリップチップ半導体パッケージの上面図である。 (A) to (C) of FIG. 6 are process drawings following (C) of FIG. 5, (A) is an explanatory diagram of an electrode forming process, and (B) is an explanatory diagram of an attaching process. It is a figure and (C) is explanatory drawing of a cutting process. In (A) to (C), a top view is shown on the right side of the drawing, and a cross-sectional view taken along a line AA of the top view is shown on the left side of each top view. In (A) to (C), the electrodes 3 for IC connection and Illustration of the external connection electrode 4 is omitted. · Fig. 7 is a top view of the flip chip semiconductor package.
第 8図は、 第 7図の A— Aに沿った切り口における断面図である。  FIG. 8 is a cross-sectional view taken along a line AA in FIG.
第 9図は、 第 7図の B— Bに沿った切り口における断面図である。 発明を実施するための最良の形態  FIG. 9 is a cross-sectional view taken along a cut line BB in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態について図面を参照して説明する。 なお、 参照する 図面は、 この発明が理解できる程度に、 各構成成分の大きさ、 形状および配置関 係を概略的に示してあるに過ぎない。 したがって、 この発明は図示例にのみ限定 されるものではなレ、。  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings referred to merely schematically show the size, shape, and arrangement of each component so that the present invention can be understood. Therefore, the present invention is not limited to the illustrated example.
以下の各実施の形態におけるフリップチップ半導体パッケージの製造方法にお いても、封止工程までの工程は、先に説明した従来の工程と同様の工程にて行う。 したがって、 これらの工程の説明を省略する。  Also in the manufacturing method of the flip chip semiconductor package in each of the following embodiments, the steps up to the sealing step are performed in the same steps as the conventional steps described above. Therefore, description of these steps is omitted.
[第 1の実施の形態]  [First Embodiment]
第 1の実施の形態においては、 切断により複数偶の回路基板に分けられる集合 回路基板の主表面に I Cチップの下面をフリップチップボンディングにより実装 する実装工程と、 この集合回路基板と該 I Cチップとの空隙および当該 I Cチッ プの側面を封止樹脂により封止する封止工程の後、 研削工程を行う。  In the first embodiment, a mounting step of mounting the lower surface of an IC chip by flip-chip bonding on a main surface of an integrated circuit board which is divided into a plurality of even circuit boards by cutting; After the sealing step of sealing the gap and the side surface of the IC chip with a sealing resin, a grinding step is performed.
そして、 研削工程後、 従来例と同様にして、 集合回路基板 1 0 0の裏面に、 半 田ボール電極 9を形成する。  After the grinding step, the solder ball electrode 9 is formed on the back surface of the collective circuit board 100 in the same manner as in the conventional example.
ここで、 第 1図を参照して、 研削工程について説明する。 第 1図は、 研削工程 を説明するための断面図である。 なお、 第 1図においては、 上述した従来例と同 一の構成成分には、 同一の符号を付して示す。 また、 第 1図には、 半田ボール電 極 9を形成した状態を示す。 また、 第 1図において、 I Cチップ 6および封止樹 月旨 7のうち、 研削された部分の形状を一点鎖線で示す。  Here, the grinding process will be described with reference to FIG. FIG. 1 is a cross-sectional view for explaining a grinding step. In FIG. 1, the same components as those in the above-described conventional example are denoted by the same reference numerals. FIG. 1 shows a state in which the solder ball electrodes 9 are formed. In FIG. 1, the shape of the ground portion of the IC chip 6 and the sealing tree 7 is indicated by a dashed line.
この研削工程においては、 集合パッケージ状態のまま、 I Cチップ 6の上面 6 aを、 例えばグライディングなどの研削手段により、 研削する。 研削にあたって は、 研削後の I Cチップ 6の上面 6 cの高さが、 I Cチップ 6の能動素子面 （I C回路形成面） （図示せず） の高さよりも高くなるようにする。 その理由は、 I Cチップ 6の機能が研削により悪影響を受けることを回避するためである。 In this grinding step, the upper surface 6a of the IC chip 6 is ground by a grinding means such as grinding, for example, while keeping the package state. In the grinding, the height of the upper surface 6c of the IC chip 6 after the grinding is higher than the height of the active element surface (IC circuit forming surface) (not shown) of the IC chip 6. The reason is I This is to prevent the function of the C chip 6 from being adversely affected by the grinding.
研削の結果、 I Cチップ 6の厚さは、 第 1図に示すように から t iとなる。 そして、 半導体パッケージ 2 0の厚さ t 0は、 研削後の I Cチップの厚さ t iと、 半田バンプ 5の厚さ t 2と、 回路基板 1の厚さ t 3と、 半田ボール電極 9の厚さ t 4との和となる。 As a result of the grinding, the thickness of the IC chip 6 becomes from ti to ti as shown in FIG. Then, the thickness t 0 of the semiconductor package 2 0, the thickness ti of the IC chip after grinding, the thickness t 2 of the solder bumps 5, and the thickness t 3 of the circuit board 1, the thickness of the solder ball electrodes 9 is the sum of the t 4.
I Cチップ 6の厚さを研削により Τ 1 = 0 . 5 m mから例えば t = 0 . 2 m mまで 0 . 3 mm薄くした場合、 他の部分の厚さがそれぞれ従来例と同じ t 2 = 0 . 0 5 mm, t 3 = 0 . 2 8 mm, t 4 = 0 . 4 mmならば、 フリップチップ 半導体パッケージ 2 0の厚さは、 t。= 0 . 9 3 mmとなる。 したがって、 フリ ップチップ半導体パッケージ 2 0の厚さを 1 mm以下とすることができる。 なお、 封止工程において I Cチップ 6の上面 6 aにフィレツトが付着しても、 研削により除去される。 このため、 研削後の I Cチップ 6の上面 6 cには、 封止 樹脂は付着していない。 したがって、 研削後の I Cチップ 6の上面 6 cは、 平坦 化されている。 その結果、 封止工程において、 フィレットの寸法管理を緩和する ことができる。 その上、 フリップチップ半導体パッケージの電気特性の測定を行 う際に、 I Cチップの上面を平面電極に均等に接触させることができる。 このた め、 正確な電気特性の測定を行うことができる c したがって、 半導体パッケージ の信頼性を向上させることができる。 T 1 = 0 by grinding the thickness of the IC chip 6. 0 5 mm for example up to t = 0. 2 mm. 3 mm when the thickness, the same t 2 = 0 and conventional thickness of other portions, respectively. If 0 5 mm, t 3 = 0.28 mm, t 4 = 0.4 mm, the thickness of the flip-chip semiconductor package 20 is t. = 0.93 mm. Therefore, the thickness of the flip-chip semiconductor package 20 can be reduced to 1 mm or less. In addition, even if a fillet adheres to the upper surface 6a of the IC chip 6 in the sealing step, it is removed by grinding. Therefore, the sealing resin does not adhere to the upper surface 6c of the IC chip 6 after the grinding. Therefore, the upper surface 6c of the IC chip 6 after the grinding is flattened. As a result, in the sealing step, the dimensional control of the fillet can be eased. In addition, when measuring the electrical characteristics of the flip-chip semiconductor package, the upper surface of the IC chip can be evenly brought into contact with the planar electrode. For this reason, therefore c can measure the precise electrical characteristics, thereby improving the reliability of the semiconductor package.
また、 この実施の形態では、 集合パッケージの状態で、 研削を行うので、 各 I Cチップ 6を一度に研削できるとともに、 各 I Cチップ 6の厚さを均一にするこ とができる。 このため、 生産性を向上させることができる。 また、 樹脂封止され た状態で研削するので、 I Cチップ 6の反りの発生を抑制できる。  In this embodiment, since the grinding is performed in the state of the collective package, each IC chip 6 can be ground at once, and the thickness of each IC chip 6 can be made uniform. For this reason, productivity can be improved. In addition, since grinding is performed in a state of being sealed with a resin, occurrence of warpage of the IC chip 6 can be suppressed.
次に、 研削工程後、 半田ボール電極 9を形成した集合回路基板 1 0 0を、 上述 した従来例と同様にして、 ダイシングにより切断する。 第 2図に、 ダイシングに より切り出されたフリップチップ半導体パッケージ 2 0の上面を示す。 また、 第 3図に、 第 2図の C一 Cに沿った切り口における断面図を示す。  Next, after the grinding step, the collective circuit board 100 on which the solder ball electrodes 9 are formed is cut by dicing in the same manner as in the above-described conventional example. FIG. 2 shows the top surface of the flip chip semiconductor package 20 cut out by dicing. FIG. 3 is a cross-sectional view taken along a line C-C in FIG.
この実施の形態では、 I Cチップ 6の側面の封止樹脂も I Cチップ 6と同時に 研削される。 その結果、 封止樹脂 7の最高部は平坦面 7 aとなる。 そして、 第 2 図に示すように、 この平坦面 7 aは、 I Cチップ 6の上面 6 cの周囲を取り囲ん でいる。 - その上、 第 3図に示すように、 I Cチップ 6の切削後の上面 6 cと、 封止樹月旨 7の平坦面 7 aとは、 同一平面上の研削面 6 bとなっている。 したがって、 研削 の結果、 回路基板 1の主表面 1 aを基準とした、 I Cチップ 6の上面 6 cの高さ と、 I Cチップ 6の側面を封止した封止樹脂の最高部の平坦面 7 aの高さとが実 質的に一致する。 In this embodiment, the sealing resin on the side surface of the IC chip 6 is ground simultaneously with the IC chip 6. As a result, the highest part of the sealing resin 7 becomes the flat surface 7a. Then, as shown in FIG. 2, this flat surface 7a surrounds the periphery of the upper surface 6c of the IC chip 6. In. -In addition, as shown in Fig. 3, the upper surface 6c of the IC chip 6 after cutting and the flat surface 7a of the sealing tree 7 are ground surfaces 6b on the same plane. . Therefore, as a result of the grinding, the height of the upper surface 6 c of the IC chip 6 with respect to the main surface 1 a of the circuit board 1 and the flat surface 7 of the highest part of the sealing resin sealing the side surface of the IC chip 6 The height of a is practically the same.
このように、 封止樹脂 7の平坦面 7 aを形成すれば、 フリツプチップ半導体パ ッケージの上面として、 I Cチップ 6の上面 6 cに加えて封止樹脂 7の平坦面 7 aも利用することができる。 その結果、 フリップチップ半導体パッケージ 2 0の マーキング領域をより広く取ることができる。 このため、 マーキングを容易に行 うことができる。  By forming the flat surface 7a of the sealing resin 7, the flat surface 7a of the sealing resin 7 can be used as the upper surface of the flip chip semiconductor package in addition to the upper surface 6c of the IC chip 6. it can. As a result, the marking area of the flip chip semiconductor package 20 can be made wider. For this reason, marking can be easily performed.
なお、 マーキングされる内容としては、 例えば、 パッケージのメーカ名、 製造 日、 製造番号が挙げられる。  The contents to be marked include, for example, the package manufacturer name, manufacturing date, and serial number.
また、 パッケージの上面 6 cおよび 7 aの面積が広いので、 フリップチップ半 導体パッケージ 2 0を真空吸着により容易にピックァップできる。  Further, since the area of the upper surface 6c and 7a of the package is large, the flip-chip semiconductor package 20 can be easily picked up by vacuum suction.
また、 パッケージ 2 0をその上面 6 cおよび 7 aで固定する場合には、 固定面 積を広く取ることができる。 このため、 パッケージをより確実に固定することが できる。 上面 6 cおよび 7 aで固定する場合としては、 例えば、 集合パッケージ 状態の I Cチップ 6側を固定してダイシングを行う場合が挙げられる。  Also, when the package 20 is fixed on the upper surfaces 6c and 7a, a large fixing area can be secured. Therefore, the package can be fixed more reliably. As a case of fixing with the upper surfaces 6c and 7a, for example, there is a case where dicing is performed while fixing the IC chip 6 side in an assembled package state.
[第 2の実施の形態] [Second embodiment]
次に、 第 4図を参照して、 第 2の実施の形態について説明する。  Next, a second embodiment will be described with reference to FIG.
第 2の実施の形態では、 研削工程後、 コーティング工程において、 I Cチップ 6の上面 6 cおよび封止樹脂 7の平坦面 7 aを、 保護被 H莫 1 2によりコーティン グする。 この保護被膜 1 2は、 I Cチップ 6の上面 6 cと封止樹脂 7の平坦面 7 aとの境界線 1 1上を覆うようにする。  In the second embodiment, after the grinding step, the upper surface 6c of the IC chip 6 and the flat surface 7a of the sealing resin 7 are coated with the protective cover 12 in the coating step. This protective film 12 covers the boundary 11 between the upper surface 6 c of the IC chip 6 and the flat surface 7 a of the sealing resin 7.
このように保護被膜 1 2を設ければ、 半導体パッケージ 2 0 aの信頼性を向上 させることができる。 特に、 境界線 1 1上をコ一ティングすることにより、 境界 線 1 1における I Cチップ 6と封止樹脂 7との隙間の発生を防止して、 信頼性を 一層向上させることができる。 さらに、 保護被膜 1 2を設けることにより、 封止 樹脂 7から I Cチップ 6へ印加される応力を緩和することができる。 その結果、 I Cチップ 6に対する応力による悪影響、 例えば、 I Cチップの破損を回避する ことができる。 このため、 フリップチップ半導体バッケージ 2 0 aの ί言頼 ¾iを向 上させることができる。 By providing the protective film 12 in this manner, the reliability of the semiconductor package 20a can be improved. In particular, coating on the boundary 11 prevents the occurrence of a gap between the IC chip 6 and the sealing resin 7 at the boundary 11, thereby improving reliability. It can be further improved. Further, by providing the protective film 12, the stress applied from the sealing resin 7 to the IC chip 6 can be reduced. As a result, it is possible to avoid adverse effects due to stress on the IC chip 6, for example, damage to the IC chip. For this reason, the word order i of the flip chip semiconductor package 20a can be improved.
また、 保護被膜 1 2の材料として、 封止樹胎 7の材料とは異なるジャンクショ ンコーティングレンジ （J C R) を用いる。 このため、 硬化した封止樹脂 7 aの 表面に対しする保護被膜 1 2の密着性を向上させることができる。 その結果、 保 護被膜 1 2の剥離を防止することができる  Further, a junction coating range (JCR) different from the material of the sealing tree 7 is used as the material of the protective coating 12. Therefore, the adhesion of the protective film 12 to the surface of the cured sealing resin 7a can be improved. As a result, peeling of the protective film 12 can be prevented.
次に、 第 2の実施の形態では、 この保護被 li½ 1 2をレーザ光線により削ること により、 マーキングを行う。 レーザ光線によりマーキングを行えば、 印刷により マーキングを行う場合に比べて、マーキング内容を容易に変更することができる。 これに対して、 印刷によりマーキングを行う場合には、 印刷内容を変更するた びに、 印刷用の版を変更する必要があつた。  Next, in the second embodiment, marking is performed by shaving the protected layer 12 with a laser beam. When marking is performed using a laser beam, the contents of the marking can be changed more easily than when marking is performed by printing. On the other hand, in the case of marking by printing, it was necessary to change the printing plate each time the print content was changed.
さらに、 この実施の形態では、 保護被膜〗 2を不透明とする。 このため、 不透 明な保護被膜 1 2の部分と、 I Cチッァ 6の上面 6 し'が露出した削られた部分と のコントラストを向上させることができる:： その結果、 マーキングの視認性を向 上させることができる。  Further, in this embodiment, the protective coating # 2 is opaque. Therefore, it is possible to improve the contrast between the opaque protective coating 12 and the chipped portion where the upper surface 6 ′ of the IC chip 6 is exposed: As a result, the visibility of the marking is improved. Can be up.
上述した実施の形態では、 特定の材料を使用し、 特定の条件で形成した例につ いて説明したが、 この発明は多くの変更および変形を行うことができる。例えば、 上述した実施の形態では、 個々のフリップチップ半導体パッケージをダイシング により切り出す前に、 研削工程を行ったが、 この発明では、 例えば、 ダイシング 工程後に研削工程を行っても良レ、。 産業上の利用可能性  In the above-described embodiment, an example in which a specific material is used and formed under specific conditions has been described. However, the present invention can be subjected to many changes and modifications. For example, in the above-described embodiment, the grinding step is performed before each flip-chip semiconductor package is cut out by dicing. In the present invention, for example, the grinding step may be performed after the dicing step. Industrial applicability
以上のように、 本発明に係るフリツプチップ半導体パッケージおよびその製造 方法は、 カメラ一体型 V T Rや小型携帯機器等に搭載される、 信頼性おょぴ生産 性の優れたフリツプチップ半導体パッケージおよびその製造方法として好適であ る。  As described above, the flip-chip semiconductor package according to the present invention and the method for manufacturing the same are provided as a flip-chip semiconductor package mounted on a camera-integrated VTR, a small portable device, or the like and having excellent reliability and productivity and a method for manufacturing the same. It is suitable.

Claims

請 求 の 範 囲 The scope of the claims
1 . 回路基板の主表面に I Cチップの下面をフリップチップボンディングによ り実装し、 該回路基板と該 I cチップとの空隙に封止樹脂を注入して、 当該空隙 を封止したフリップチップ半導体パッケージにおいて、 1. The lower surface of the IC chip is mounted on the main surface of the circuit board by flip chip bonding, and a sealing resin is injected into a gap between the circuit board and the Ic chip to seal the gap. In semiconductor packages,
前記回路基板の主表面を基準とした、 前記 I cチップの上面の高さと、 前記空 隙から前記 I Cチップの侧面にはみ出した前記封止樹脂の最高部の高さとが実質 的に一致した  The height of the upper surface of the IC chip, with reference to the main surface of the circuit board, substantially coincided with the height of the highest portion of the sealing resin protruding from the gap to one surface of the IC chip.
、  ,
ことを特徴とするフリップチップ半導体 Flip chip semiconductor characterized by the following:
2 . 特許請求の範囲第 1項に記載のフリツプチッブ半導体パッケージにぉレ、て、 前記 I Cチップの上面が、 研削面である 2. The flip chip semiconductor package according to claim 1, wherein an upper surface of the IC chip is a ground surface.
ことを特徴とするフリツフチップ半導体パッケージ。 A flip chip semiconductor package, characterized in that:
3 . 特許請求の範囲第 1項または第 2項に記載のフリップチップ半導体パッケ ージにおいて、 3. In the flip chip semiconductor package according to claim 1 or 2,
前記封止樹脂の最高部が、 平坦面である  The highest part of the sealing resin is a flat surface
ことを特徴とするフリップチップ半導体パッケージ。 A flip chip semiconductor package characterized by the above.
4 . 特許請求の範囲第 3項に記載のフリッブチップ半導体パッケージにおいて、 前記封止樹脂の平坦面が、 前記 I Cチップの上面の周囲を取り囲んでいる ことを特徴とするフリップチップ半導体パッケージ。 4. The flip-chip semiconductor package according to claim 3, wherein a flat surface of the sealing resin surrounds a periphery of an upper surface of the IC chip.
5 . 特許請求の範囲第 3項または第 4項に記載のフリツプチップ半導体パッケ ージにおいて、 5. In the flip-chip semiconductor package according to claim 3 or 4,
前記 I Cチップの上面と、 前記封止樹脂の平坦面とが、 同一平面上の研削面で ある  The upper surface of the IC chip and the flat surface of the sealing resin are ground surfaces on the same plane.
ことを特徴とするフリップチップ半導体パッケージ。 A flip chip semiconductor package characterized by the above.
6 . 特許請求の範囲第 2 ~ 5項のいずれか一つに記載のフリツプチップ半導体 パッケージにおいて、 6. The flip-chip semiconductor package according to any one of claims 2 to 5,
前記回路基板の主表面を基準とした、 前記研削面の高さが、 前記 I Cチップの 能動素子面の高さよりも高い  The height of the ground surface with respect to the main surface of the circuit board is higher than the height of the active element surface of the IC chip.
ことを特徴とするフリップチップ半導体パッケージ。 A flip chip semiconductor package characterized by the above.
7 . 特許請求の範囲第 3〜 6項の！/、ずれか一つに記載のフリツプチップ半導体 パッケージにおいて、 7. Claims 3-6! / In the flip chip semiconductor package described in any one of
前記 I Cチップの上面および前記封止樹脂の平坦面が、 保護被膜によりコーテ ィングされた  The top surface of the IC chip and the flat surface of the sealing resin were coated with a protective coating.
ことを特徴とするフリップチップ半導体パッケージ。 A flip chip semiconductor package characterized by the above.
8 . 特許請求の範囲第 7項に記載のフリップチップ半導体パッケージにおいて、 前記保護被膜が、 前記 I Cチップの上面と前記封止樹脂の平坦面との境界線上 を覆った 8. The flip-chip semiconductor package according to claim 7, wherein the protective coating covers a boundary between an upper surface of the IC chip and a flat surface of the sealing resin.
ことを特徴とするフリップチップ半導体パッケージ。 A flip chip semiconductor package characterized by the above.
9 . 特許請求の範囲第 7項または第 8項に記載のフリツプチップ半導体パッケ —ジにおいて、 9. In the flip-chip semiconductor package according to claim 7 or 8,
前記保護被膜の材料と前記封止樹脂の材料とが異なる  The material of the protective coating is different from the material of the sealing resin
ことを特徴とするフリップチップ半導体パッケージ。  A flip chip semiconductor package characterized by the above.
1 0 . 特許請求の範囲第 1〜 9項のいずれか一つに記載のフリツプチップ半導 体パッケージにおいて、 10. The flip-chip semiconductor package according to any one of claims 1 to 9,
前記 I Cチップの上面に、 前記封止樹脂が付着していない  The sealing resin does not adhere to the upper surface of the IC chip
ことを特徴とするフリップチップ半導体パッケ一ジ。  A flip chip semiconductor package characterized by the above-mentioned.
1 1 . 切断により複数個の回路基板に分けられる集合回路基板の主表面に I C チップの下面をフリップチップボンディングにより実装する実装工程と、 該集合回路基板と該 I Cチップとの空隙おょぴ当該 I Cチップの側面を封止樹 脂により封止する封止工程と、 1 1. A mounting process in which the lower surface of the IC chip is mounted by flip-chip bonding on the main surface of the collective circuit board divided into a plurality of circuit boards by cutting, A gap between the integrated circuit board and the IC chip, a sealing step of sealing a side surface of the IC chip with a sealing resin;
前記封止工程の後に、 前記 I cチップの上面を研削する研削工程と  A grinding step of grinding the upper surface of the Ic chip after the sealing step;
を含むことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package, comprising:
1 2 . 特許請求の範囲第 1 1項に記載のフリツプチップ半導体パッケ一ジの製 造方法において、 12. The method of manufacturing a flip-chip semiconductor package according to claim 11, wherein:
前記研削工程において、 前記回路基板の主表面を基準とした、 前記 I Cチップ の上面の高さと、 前記 I cチップの側面を封止した前記封止樹脂の最高部の高さ とを実質的に一致させた  In the grinding step, the height of the upper surface of the IC chip and the height of the highest portion of the sealing resin that seals the side surface of the Ic chip are substantially determined with reference to the main surface of the circuit board. Matched
ことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package.
1 3 . 特許請求の範囲第 1 2項に記載のフリツプチップ半導体パッケ一ジの製 造方法において、 13. The method of manufacturing a flip chip semiconductor package according to claim 12, wherein:
前記研削工程において、 前記封止樹脂の最高部として平坦面を形成した ことを特徴とするフリップチップ半導体パッケージの製造方法。  In the grinding step, a flat surface is formed as the highest part of the sealing resin.
1 4 . 特許請求の範囲第 1 3項に記載のフリツプチップ半導体パッケージの製 造方法において、 14. The method of manufacturing a flip-chip semiconductor package according to claim 13, wherein:
前記研削工程において、 前記 I cチップの上面の周囲を取り囲んだ、 前記封止 樹脂の平坦面を形成した  In the grinding step, a flat surface of the sealing resin was formed, surrounding the periphery of the upper surface of the I c chip.
ことを特徴とするフリツプチップ半導体パッケージの製造方法。  A method of manufacturing a flip chip semiconductor package.
1 5 . 特許請求の範囲第 1 3項または第 1 4項に記載のフリップチップ半導体 パッケージの製造方法にぉレ、て、 15. The method of manufacturing a flip-chip semiconductor package according to claim 13 or claim 14,
前記研削工程において、前記 I cチップの上面と、前記封止樹脂の平坦面とを、 同一平面上の研削面として形成した  In the grinding step, an upper surface of the Ic chip and a flat surface of the sealing resin are formed as a ground surface on the same plane.
ことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package.
1 6 . 特許請求の範囲第 1 1〜： 1 5項のいずれか一つに記載のフリップチップ 半導体パッケージの製造方法にぉレ、て、 16. The method for manufacturing a flip-chip semiconductor package according to any one of claims 1 to 15:
前記研削工程後に、 前記 I Cチップの上面および前記封止樹脂の平坦面を保護 被膜によりコーティングするコ一ティング工程を含む  After the grinding step, a coating step of coating the upper surface of the IC chip and the flat surface of the sealing resin with a protective film is included.
ことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package.
1 7 . 特許請求の範囲第 1 6項に記載のフリツプチップ半導体パッケージの製 造方法において、 17. The method of manufacturing a flip chip semiconductor package according to claim 16, wherein:
前記コ一ティング工程において、 前記保護被膜を、 前記 I Cチップの上面と前 記封止樹脂の平坦面との境界線上に形成した  In the coating step, the protective film was formed on a boundary between the upper surface of the IC chip and the flat surface of the sealing resin.
ことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package.
1 8 . 特許請求の範囲第 1 6項または第 1 7項に記載のフリップチップ半導体 パッケージの製造方法において、 18. The method of manufacturing a flip-chip semiconductor package according to claim 16 or claim 17,
前記保護被膜をレーザ光線により削ることにより、 マーキングを行う  Marking is performed by shaving the protective coating with a laser beam.
ことを特徴とするフリップチップ半導体パッケージの製造方法。 A method for manufacturing a flip-chip semiconductor package.
1 9 . 特許請求の範囲第 1 1〜 1 8項のレ、ずれか一つに記載のフリツプチップ 半導体パッケージの製造方法にぉレヽて、 19. The method for manufacturing a flip chip semiconductor package according to any one of claims 11 to 18 of the claims,
前記研削工程の後に、 前記集合回路基板を前記回路基板ごとに切り分ける切断 工程を含む  After the grinding step, a cutting step of cutting the collective circuit board for each circuit board is included.
ことを特徴とするフリップチップ半導体パッケージの製造方法。  A method for manufacturing a flip-chip semiconductor package.
PCT/JP1998/003588 1997-08-13 1998-08-12 Flip-chip semiconductor package and method for manufacturing the same WO1999009592A1 (en)

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JP21852997A JPH1167979A (en) 1997-08-13 1997-08-13 Mounting structure for flip-chip semiconductor package and manufacture thereof
JP9/218529 1997-08-13

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US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
CN104772574B (en) * 2014-01-09 2016-09-14 中国科学院金属研究所 A kind of method at labelling interconnection structure initial liquid-solid reaction interface

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TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP2001339011A (en) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP3929250B2 (en) 2001-03-08 2007-06-13 株式会社ルネサステクノロジ Semiconductor device
JP4806196B2 (en) * 2005-01-11 2011-11-02 パナソニック株式会社 Semiconductor device
JP5280139B2 (en) * 2008-09-19 2013-09-04 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and mounting substrate

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EP1094511A2 (en) * 1999-10-22 2001-04-25 Lucent Technologies Inc. Low profile integrated circuit packages
EP1094511A3 (en) * 1999-10-22 2005-09-07 Lucent Technologies Inc. Low profile integrated circuit packages
US6459152B1 (en) * 1999-10-27 2002-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
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