JP3850967B2 - Semiconductor package substrate and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package having protruding electrodes for external connection.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flip chip bonding has been developed in which a bare chip is directly mounted face-down on a substrate as semiconductor packages become smaller and higher in density. With the advent of camera-integrated VTRs, mobile phones, and the like, mobile devices on which small packages of approximately the same dimensions as bare chips, so-called CSP (chip size / scale packages), have appeared one after another. Recently, the development of CSP is progressing rapidly, and the market demand is in full swing.
[0003]
FIG. 6 shows a conventional technique in which a large number are taken and high-density mounting is disclosed in Japanese Patent Laid-Open No. 8-1553819. The outline will be described below with reference to the drawings.
[0004]
In FIG. 6, after forming a through hole 2 in a strip-shaped circuit board 1, a step of applying a copper plating layer and a circuit constituting a plurality of, for example, two BGAs including a common electrode 14 connected to all circuit patterns. A circuit pattern forming process for forming a pattern, and after applying a photosensitive resin film on both the upper and lower surfaces of the circuit board 1, the common electrode 14 and the connecting portions of the IC chip, bonding wires, and solder bumps are removed by etching. A Ni-Au plating layer is formed on the surface of the exposed copper plating layer of the upper and lower surfaces of the circuit board 1 by using the common electrode 14 and a dry film laminating process for forming a dry film.
[0005]
Next, in the pattern separation process for separating the common electrode 14 and the circuit pattern, a long hole is formed by router processing so that the connection portions 15a connected to the circuit board 1 are left at the four corners along the four sides of the product separation line 15. 16 is drilled. Thereafter, resin sealing is performed by wire bonding and transfer molding, and solder bumps are formed on the lower surface of the circuit board 1.
[0006]
In the product separation process, since the connecting portions left at the four corners are narrow, a single BGA can be manufactured by separating very easily without applying an extra load by a separating means such as press punching.
[0007]
However, although the above-described method for manufacturing a plurality of strip-shaped semiconductor packages is slightly improved in productivity as compared to a method for manufacturing a single semiconductor package, in a CSP which is a small package, a circuit board is manufactured. This reduces the number of substrates that can be produced and increases the production cost. Further, as in the case of the CSP, when there is no difference in the distance from the outer edge of the circuit board to the center of the ball electrode located on the outermost periphery, the mold holder when separating by a separating means such as press punching in the product separation process. There was a problem such as a lack of money.
[0008]
Therefore, an outline of a method for manufacturing a conventional semiconductor package of a CSP mounted on a small portable device or the like will be described below.
[0009]
FIG. 3 shows a manufacturing process of a semiconductor package substrate. After the through hole 21 is formed in the collective circuit board 1A that is copper-coated on both sides, a copper plating layer 22 is formed by electroless copper plating and electrolytic copper plating, and the through hole is filled with a filling material 23 such as a resin, and an etching resist After forming the pattern mask by laminating and exposing and developing, pattern etching is performed using an etching solution, so that a plurality of IC connection electrodes 3 arranged on the upper surface side of the collective circuit board 1A are provided on the lower surface side. The external connection electrode 4 which is a pad electrode is formed on the substrate. Next, a solder resist process is performed to form a resist film on a predetermined portion, so that the external connection electrode 4 is exposed on the lower surface side of the collective circuit board 1A, and the exposed IC connection electrode 3 is exposed. Then, gold plating is performed on the external connection electrodes 4 to complete the collective circuit board 1A to be obtained in large numbers.
[0010]
FIG. 4A is a circuit board forming step for taking a large number of pieces as described in detail in FIG. An external connection electrode 4 having the same shape and solderable is formed. Reference numeral 2 denotes a cut line orthogonal to the X and Y directions.
[0011]
In the IC chip mounting process shown in FIG. 4B, first, the IC wafer is poured into a bump process to form solder bumps 5 on the pad electrode surface of the IC wafer. The solder bumps 5 are generally formed by a stud bump method, a ball bump method, a plated bump method, etc., in which a window is formed with a resist at the pad electrode position and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps with a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturization of IC chips.
[0012]
After forming the solder bumps 5, with the IC wafer attached with an adhesive tape or the like, the wafer thickness is cut in the X and Y directions by a full-cut method with a device such as a dicing saw to a predetermined chip size, The IC chip 6 is divided into single pieces.
[0013]
The integrated circuit board 1A in which the IC chips 6 with solder bumps or the integrated circuit board 1A described above are coated with a flux at a predetermined position on the wiring pattern and divided into a plurality of IC chips 6 divided into single pieces. After mounting at a predetermined position on each of the circuit boards 1, flip chip mounting is performed through a solder reflow process.
[0014]
In the sealing step shown in FIG. 4C, the resin is integrally sealed by side potting while straddling the plurality of adjacent IC chips 5 with the thermosetting sealing resin 7. The IC chip 6 is fixed face-down on each circuit board 1 of the collective circuit board 1A.
[0015]
Furthermore, a ball electrode 9 is formed by placing a solder ball at the position of the external connection electrode 4 formed on the lower surface side of the collective circuit board 1A on which the IC chip 6 is mounted and performing reflow.
[0016]
In the reference member pasting step shown in FIG. 5A, the external connection electrode 4 formed on the lower surface side of the collective circuit board 1A on which the IC chip 6 is mounted is fixed on the reference member 8 with an adhesive or an adhesive tape. Stick by means.
[0017]
FIG. 5B is a tiling process, and is formed on the lower surface side of the collective circuit board 1A as shown in FIG. 7A by cutting means such as a dicing saw along the above-described cut lines 2 in the X and Y directions. After cutting and dividing into single pieces based on the cut alignment marks 11, they are peeled off from the reference member 8 by heat or the like.
[0018]
FIG. 7A is a plan view of the lower surface side of the collective circuit board 1A. The external connection electrode 4 and the cutting alignment mark 11 are formed outside the product.
[0019]
FIG.7 (b) is EE 'sectional drawing of the alignment mark 11 for cutting of Fig.7 (a), and is formed with the copper pattern.
[0020]
FIG.7 (c) is FF 'sectional drawing of the electrode 4 for external connection of Fig.7 (a), and is formed of the soldering resist formed on the copper pattern. That is, the surface of the external connection electrode 4a is formed by a copper pattern, but the outer diameter and position of the electrode are determined by the opening of the solder resist.
[0021]
[Problems to be solved by the invention]
However, the semiconductor package manufacturing method described above has the following problems. That is, since the cutting alignment pattern used as a reference in the dicing process and the external connection electrode are not the same, there are problems such as poor position accuracy of the external terminals viewed from the product external reference when cut and divided into single pieces. there were. That is, the outer diameter and position of the cutting alignment pattern are determined by the copper pattern, whereas the outer diameter and position of the external connection electrode are determined not by the copper pattern but by the opening of the solder resist. It was difficult to match perfectly.
[0022]
The position accuracy of the external terminals as seen from the product outline standard is ± 150 microns, which is a combination of the solder position tolerance of ± 100 microns and the dicing tolerance of ± 50 microns with respect to the copper pattern that forms the cutting alignment pattern It becomes.
[0023]
The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor substrate and a semiconductor package with good external terminal positional accuracy with respect to an external standard to be mounted on a small portable device or the like.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a circuit board formed by arranging a plurality of bonding patterns for mounting IC chips and electrode patterns for forming external connection electrodes on the surface of the collective circuit board. In a semiconductor package substrate in which a plurality of IC chips are electrically connected and a package assembly in which the IC chips are sealed with resin is cut to form a single completed semiconductor package, the circuit board of the package assembly includes: It has an alignment pattern indicating a cutting position, and the alignment pattern is formed of the same member as a member that partially covers the electrode pattern and regulates the position of the external connection electrode. To do.
[0025]
In addition, a plurality of bonding patterns for mounting IC chips provided on one surface and electrode patterns for forming external connection electrodes provided on the other surface are arranged on the surface of the collective circuit board. A circuit board forming step, an IC chip mounting step for electrically connecting an IC chip to the bonding pattern, a sealing step for forming a package assembly by resin-sealing the IC chip, and a package assembly A holding step of fixing the IC chip mounting surface side to the reference member, an alignment pattern forming step of forming an alignment pattern that is a cutting position on the circuit board of the held package assembly, and the alignment pattern based on the alignment pattern In a semiconductor package substrate comprising a cutting step of cutting a circuit board to form a single completed semiconductor package, the alignment The cutting pattern is the same member as the member that partially covers the electrode pattern of the external connection electrode formed in the circuit board forming step and regulates the position of the external connection electrode , and is formed in the same step. It is characterized by.
[0027]
Moreover, members for regulating the position of the external connection electrodes to cover the electrode pattern partially is characterized in that a solder resist.
[0028]
The cutting step is performed by cutting with a dicing saw.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor package substrate and a manufacturing method thereof according to the present invention will be described with reference to the drawings. 1 and 2 are explanatory views of a substrate for a semiconductor package according to an embodiment of the present invention. FIG. 3 is an explanatory view showing a manufacturing process of a semiconductor package substrate. 4 and 5 are explanatory views showing a manufacturing process of a semiconductor package with protruding electrodes. The same members as those in the prior art are denoted by the same reference numerals.
[0030]
First, FIG. 3 is an explanatory diagram of a semiconductor package substrate forming process, but since it is the same as the above-described prior art, description thereof is omitted.
[0031]
FIG. 1A is a plan view showing a semiconductor package substrate of the present invention. There is a cutting alignment mark 11 formed of a solder resist outside the product. On the copper pattern on the product side, there is an external connection electrode 4b whose outer diameter and position are determined by a solder resist. That is, in the present embodiment, the case where the outer diameter of the copper pattern is larger than the opening diameter of the solder resist opening is shown, and the alignment mark 11 for cutting is determined by the solder resist that determines the outer diameter and position of the external connection electrode 4b. Since it is formed, the positional accuracy of the electrode with respect to the product outer shape is improved.
[0032]
FIG.1 (b) is AA 'sectional drawing of Fig.1 (a).
[0033]
FIG.1 (c) is BB 'sectional drawing of Fig.1 (a).
[0034]
FIG. 2A shows another example of the semiconductor package substrate of the present invention. There is a cutting alignment mark 11 formed of a copper pattern outside the product. In the portion where the solder resist on the product side is opened, there is an external connection electrode 4b formed of a copper pattern. In the present embodiment, the outer diameter of the copper pattern is smaller than the opening diameter of the solder resist opening, and the cutting alignment mark 11 determines the outer diameter and position of the external connection electrode 4b. Therefore, the positional accuracy of the electrode with respect to the product outer shape is improved.
[0035]
FIG. 2B is a cross-sectional view taken along the line CC ′ of FIG.
[0036]
FIG. 2C is a cross-sectional view taken along the line DD ′ of FIG.
[0037]
The circuit board forming process in FIG. 4A, the IC mounting process in FIG. 4B, and the resin sealing process in FIG.
[0038]
The reference member pasting step shown in FIG. 5A is performed by using a ball electrode 9a and a solder ball protrusion 9b as an adhesive to the reference member 8, for example, a heat release tape “ELEP holder pressure-sensitive dicing tape manufactured by Nitto Denko Corporation”. , SPV-224 "or the like, and is fixed on the reference member 8 by being attached thereto.
[0039]
FIG. 2 (d) shows a tiling process, along the above-mentioned cut line 2 in the X and Y directions, a dicing saw, for example, a disco dicing machine “DFD-640”, a blade used “NBC-ZB1090S3, 0.1 mm”. After cutting and dividing into single pieces with reference to the cutting alignment mark 11 formed of solder resist on the outside of the product by cutting means using “width” etc., the adhesive force of the peeling tape was reduced by heat. Then, it peels from the reference member 8. A single flip chip BGA 10 is completed through the above steps.
[0040]
【The invention's effect】
As described above, in the semiconductor package using the semiconductor package substrate of the present invention, the alignment member serving as a reference in the dicing process and the constituent members of the external connection electrodes that determine the outer diameter and position of the external terminal pattern are the same member. Since they are formed in the same process, it is possible to provide a semiconductor package with good positional accuracy of the external terminals with respect to the package outer shape and excellent mounting property and productivity of the semiconductor package on the motherboard.
[0041]
The position accuracy of the external terminals as viewed from the product outline is the same as the process of forming the alignment pattern for cutting and the electrode for external connection, so the positional tolerance of the copper pattern or solder resist is ± 10 microns and the dicing tolerance is ± 50 microns. The total is ± 60 microns.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a semiconductor substrate according to an embodiment of the present invention.
FIG. 2 is another explanatory diagram of the semiconductor substrate according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram showing a manufacturing process of a semiconductor substrate.
FIG. 4 is an explanatory diagram showing a circuit board forming process, an IC mounting process, and a resin sealing process in the manufacturing process of the BGA semiconductor package.
FIG. 5 is an explanatory diagram showing a circuit board forming process, an IC mounting process, and a resin sealing process in the manufacturing process of the BGA semiconductor package.
FIG. 6 is a plan view of a conventional strip-shaped BGA.
FIG. 7 is an explanatory diagram of a conventional semiconductor substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 1A Collective circuit board 2 Cut line 3 IC connection electrode 4a External connection electrode 4b Protrusion formation pad 5 Solder ball 6 IC chip 7 Sealing resin 8 Reference member 9 Ball electrode (protrusion electrode)
10 Flip chip BGA
11 Cutting alignment pattern

Claims (4)

A plurality of IC chips are electrically connected to a circuit board formed by arranging a plurality of bonding patterns for mounting IC chips and electrode patterns for forming external connection electrodes on the surface of the collective circuit board, In a semiconductor package substrate that forms a single completed semiconductor package by cutting a package assembly in which an IC chip is sealed with a resin, the circuit board of the package assembly has an alignment pattern indicating a cutting position. The semiconductor package substrate is characterized in that the alignment pattern is made of the same member as the member that partially covers the electrode pattern and regulates the position of the external connection electrode . A circuit in which a bonding pattern for mounting an IC chip provided on one surface and an electrode pattern for forming an external connection electrode provided on the other surface are arranged on the surface of the collective circuit board. A substrate forming step, an IC chip mounting step for electrically connecting an IC chip to the bonding pattern, a sealing step for forming a package assembly by resin-sealing the IC chip, and an IC chip for the package assembly A holding step of fixing the mounting surface side to the reference member, an alignment pattern forming step of forming an alignment pattern as a cutting position on the circuit board of the held package assembly, and the circuit board based on the alignment pattern In a semiconductor package substrate comprising a cutting step of forming a single completed semiconductor package by cutting Emissions is characterized in that it is formed by members of the same member for regulating the position of the external connection electrodes to cover the electrode pattern formed in the circuit board forming process, in part, and in the same step semiconductor A method for manufacturing a package substrate. 2. The semiconductor package substrate according to claim 1, wherein the member that partially covers the electrode pattern and restricts the position of the external connection electrode is a solder resist . The method for manufacturing a substrate for a semiconductor package according to claim 2, wherein the cutting step is performed by cutting with a dicing saw .

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