JP4002009B2 - Manufacturing method of semiconductor package - Google Patents

Manufacturing method of semiconductor package Download PDF

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Publication number
JP4002009B2
JP4002009B2 JP21514198A JP21514198A JP4002009B2 JP 4002009 B2 JP4002009 B2 JP 4002009B2 JP 21514198 A JP21514198 A JP 21514198A JP 21514198 A JP21514198 A JP 21514198A JP 4002009 B2 JP4002009 B2 JP 4002009B2
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Prior art keywords
semiconductor package
manufacturing
reference member
circuit board
forming
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JP2000049176A (en
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芳弘 石田
潔 清水
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Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
本発明は半導体パッケージの製造方法に係わり、更に詳しくは外部接続用の突起電極を有する半導体パッケージの製造方法に関するものである。
【０００２】
【従来の技術】
近年、半導体パッケージの小型化、高密度化に伴いベア・チップを直接フェイスダウンで、基板上に実装するフリップチップボンディングが開発されている。カメラ一体型ＶＴＲや携帯電話機等の登場により、ベア・チップと略同じ寸法の小型パッケージ、所謂ＣＳＰ（チップサイズ／スケール・パッケージ）を載せた携帯機器が相次いで登場してきている。最近ＣＳＰの開発は急速に進み、その市場要求が本格化している。
【０００３】
先ず、小型携帯機器等に搭載するＣＳＰの従来の半導体パッケージの製造方法について以下その概要を説明する。
【０００４】
先ず図７（ａ）に示す多数個取りする回路基板形成工程では、両面銅張りされた集合回路基板１Ａにスルーホール（図示しない）を形成した後、無電解銅メッキ及び電解銅メッキにより銅メッキ層を形成し、更にメッキレジストをラミネートし、露光現像してパターンマスクを形成した後、エッチング液を用いてパターンエッチングを行うことにより、前記集合回路基板１Ａの上面側には複数個分配列したＩＣ接続用電極３、下面側にパッド電極である外部接続用電極４を形成する。次にソルダーレジスト処理を行い、所定の部分にレジスト膜を形成することにより、前記集合回路基板１Ａの下面側には外部接続用電極４を露呈するように、マトリックス状に多数の同一形状の半田付け可能な表面であるレジスト膜の開口部を形成し、多数個取りする集合回路基板１Ａが完成される。２はＸ、Ｙ方向に直交するカットラインである。
【０００５】
図７（ｂ）に示すＩＣ実装工程では、先ず、ＩＣウエハーをバンプ工程に流して前記ＩＣウエハーのパッド電極面に半田バンプ５を形成する。前記半田バンプ５の形成方法には、一般に、スタッドバンプ方式、ボールバンプ方式、及びメッキバンプ方式等があるが、その中で、パッド電極位置にレジストにて窓を形成し半田浴槽中に浸漬してメッキにて半田バンプを形成するメッキバンプ方式は、パッド電極間の狭い配列でバンプを形成することが可能で、ＩＣチップの小型化には有効な半田バンプの形成手段である。
【０００６】
前記半田バンプ５を形成後、前記ＩＣウエハーを粘着テープ等で貼着した状態で、所定のチップサイズにダイシングソー等の装置でウエハーの厚みをフルカット方式でＸ、Ｙ方向に切断した後、ＩＣチップ６を単体に分割する。
【０００７】
前記半田バンプ付きＩＣチップ６、又は前述した集合回路基板１Ａの前記配線バターンの所定位置にフラックスを塗布して、単体に分割した前記ＩＣチップ６を１個づつ複数個分配列した集合回路基板１Ａの個々の回路基板１上の所定位置に搭載した後、半田リフロー工程を経て、フリップチップ実装を行う。
【０００８】
図７（ｃ）に示す封止工程では、熱硬化性の封止樹脂７で前記隣接する複数個のＩＣチップ５に跨がった状態で、サイドポッティングにより一体的に樹脂封止することにより、ＩＣチップ６はフェイスダウンで集合回路基板１Ａの個々の回路基板１上に固定される。
【０００９】
図７（ｄ）に示すボール付け工程では、回路基板１の下面側に形成された外部接続用電極４の位置に、半田ボールを配置してリフローすることによりボール電極９を形成する。
【００１０】
図８（ｅ）に示す基準部材張り付け工程では、ＩＣチップ６を実装し、ボール電極を形成した集合回路基板１Ａのボール電極を、基準部材８ａ上に接着剤又は粘着テープ等の固定手段で張り付ける。
【００１１】
図８（ｆ）は、タイシング工程で、前述のＸ、Ｙ方向のカットライン２に沿って、ダイシングソー等の切削手段で単個に切削、分割した後、溶解液等により基準部材８ａより剥離する。
【００１２】
このとき、図６（ａ）に示すように、ダイシング時の切削ごみが、集合基板１Ａの基準部材８ａ側表面及び半田ボール９表面に付着する。
【００１３】
又、図８（ｅ）に示す基準部材張り付け工程を、集合回路基板１ＡのＩＣ実装面と基準部材８ａで固定した場合、図６（ｂ）に示すように、ダイシング時の切削ごみが、集合基板１Ａの基準部材８ａ側実装面及び表面に付着する。
【００１４】
図８（ｇ）は、単個洗浄工程で、基準部材８ａより剥離したフリップチップＢＧＡ２０の基準部材８ａ側表面に付着した切削かすを篭に入れ、洗浄、落とす。以上の工程により単個のＰＢＧＡパッケージ２０が完成される。
【００１５】
【発明が解決しようとする課題】
しかしながら、前述した半導体パッケージの製造方法には次のような問題点がある。即ち、基準部材側のパッケージ表面に付着した切削かすを取る時、多数個のパッケージを同時に篭に入れ洗浄するため、洗浄及びその乾燥時、パッケージ同士が接触し、パッケージ表面を傷つけ、外観及び信頼性に問題を起こすことがあった。又、パッケージの接触を少なくするため、同時に篭に入れる個数を少なくすると、生産性が低く、コストアップ等の問題があった。
【００１６】
ＩＣ実装法が、フリップチップ実装で成された場合、図９に示すように、チップエッジが欠け、信頼性に重大な問題を起こす。
【００１７】
本発明は、上記従来の課題に鑑みなされたものであり、その目的は、小型携帯機器等に搭載する信頼性及び生産性に優れた、安価な半導体パッケージの製造方法を提供するものである。
【００１８】
【課題を解決するための手段】
上記目的を達成するために、本発明における半導体パッケージの製造方法は、第１及び第２の面を有する回路基板のいずれか一方の面に外部接続電極を形成し、他方の面にＩＣチップを実装した半導体パッケージの製造方法において、前記ＩＣチップ実装用のボンディングパターンと外部接続用電極を形成するための電極パターンとを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的に接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止して封止部を形成する封止工程と、前記外部接続用電極に突起電極を形成する電極形成工程とによりパッケージ集合体を構成する集合体形成工程と、前記パッケージ集合体の前記第１の面側を第１の基準部材に固定する第１保持工程と、保持されたパッケージ集合体の回路基板を切削して単個の半導体パッケージを形成する切削工程と、前記パッケージ集合体の前記第２の面側を第２の基準部材に固定する第２保持工程と、前記第１の基準部材を前記パッケージ集合体の前記第１の面側から剥離する剥離工程と、前記パッケージ集合体の前記第１の面側を洗浄する洗浄工程と、前記第２の基準部材から前記単個の半導体パッケージを取外す分離工程とからなることを特徴とする。
【００１９】
また前記パッケージ集合体は、第１の面が突起電極面であり、第２の面がＩＣチップ実装面であることを特徴とする。
【００２０】
また第１保持工程は、突起電極を基準部材に接着剤で固着することを特徴とする。
【００２１】
また前記パッケージ集合体は、第１の面がＩＣチップ実装面であり、第２の面が突起電極面であることを特徴とする。
【００２２】
また第１保持工程は、封止部を基準部材に接着剤で固着することを特徴とする。
【００２３】
また前記接着剤は、紫外線反応型樹脂であることを特徴とする。
【００２４】
また第２保持工程は、封止部を基準部材に接着剤で固着することを特徴とする。
【００２５】
また第２保持工程は、突起電極を基準部材に接着剤で固着することを特徴とする。
【００２６】
また接着剤は、熱反応型樹脂であることを特徴とする。
【００２７】
また前記ＩＣチップ実装工程は、フリップチップ実装工程であることを特徴とする。
【００２９】
また前記突起電極は、半田バンプであることを特徴とする。
【００３０】
また前記切削工程はダイシングソーによる切削で行うことを特徴とする。
【００３１】
【発明の実施の形態】
以下図面に基づいて本発明における半導体パッケージの製造方法について説明する。図１〜図３は本発明の実施の形態で、突起電極付きの半導体パッケージの製造工程を示す説明図である。図４、図５は本発明の別の実施の形態である。従来技術と同一部材は同一符号で示す。
【００３２】
先ず、図１（ａ）の回路基板形成工程、図１（ｂ）のＩＣ実装工程、図１（ｃ）の樹脂封止工程、図１（ｄ）のボール付け工程は、前述の従来技術の図７（ａ）〜（ｄ）と同様であるので、説明は省略する。
【００３３】
また図２（ｅ）の第１基準部材張り付け工程、図２（ｆ）のダイシング工程は、前述の従来技術の図８（ｅ）、図８（ｆ）と同様であるので、説明は省略する。
【００３４】
図２（ｇ）に示す第２基準部材張り付け工程では、前記集合回路基板１Ａが第１基準部材上で、単個に切削、分割された状態で、ＩＣチップ実装面を、第２基準部材８ｃ上に接着剤で張り付ける。
【００３５】
図３（ｄ）に示す第１基準部材剥離工程では、図２（ｅ）の第１基準部材張り付け工程で使った接着剤、例えば、リンテック（株）製の紫外線剥離テープ「Ｄ６３８」の接着力を紫外線で低下させ、第１基準部材８ｂと前記集合回路基板１Ａの製品外部分を第２基準部材及び製品部分より剥離する。
【００３６】
図３（ｅ）に示した洗浄工程では、図２（ｆ）のダイシング工程で発生して、前記集合回路基板１Ａの下面側及び半田ボール面に付着した切削ゴミを、第２基準部材にＰＢＧＡパッケージ１０を張り付けたまま、洗浄して落とす。
【００３７】
その後、ＰＢＧＡパッケージ１０を第２基準部材８ｃより剥離する。以上の工程により単個のＰＢＧＡパッケージが完成される。
【００３８】
図４、図５は、本発明の他の実施形態を示す。
【００３９】
図４（ａ）の第１基準部材張り付け工程では、図１（ｄ）のボール付け工程により完成したＩＣチップ６を実装し、ボール電極を形成した集合回路基板１ＡのＩＣ実装面を、第１基準部材８ｂ上に接着剤で張り付ける。
【００４０】
図４（ｂ）のタイシング工程では、前述のＸ、Ｙ方向のカットライン２に沿って、ダイシングソー等の切削手段で単個に切削する。この時、集合回路基板１Ａの周囲の不要部分は除去される。
【００４１】
図４（ｃ）に示す第２基準部材張り付け工程は、前記集合回路基板１Ａが第１基準部材８ｂ上で、単個に切削、分割された状態で、半田ボール９を第２基準部材８ｃ上に接着剤で張り付ける。
【００４２】
図５（ｄ）に示す第１基準部材剥離工程では、図３（ｄ）の工程と同様にして、第１基準部材８ｂを第２基準部材８ｃ及び製品部分より剥離する。
【００４３】
図５（ｅ）に示す洗浄工程では、図４（ｂ）のダイシング工程で発生し、前記集合回路基板１Ａの上面側及び封止面に付着した切削ゴミを、第２基準部材にＰＢＧＡパッケージ１０を張り付けたまま、洗浄して落とす。
【００４４】
その後、ＰＢＧＡパッケージ１０を第２基準部材８ｃより剥離する。以上の工程により単個のＰＢＧＡパッケージが完成される。
【００４５】
【発明の効果】
以上説明したように、本発明の半導体パッケージの製造方法によれば、前記集合回路基板の上面側に複数個分配列して回路基板にＩＣチップを実装し、封止樹脂でサイドモールドして、下面側の外部接続用電極に突起電極を形成し、半田ボールを第１基準部材に固定し、集合回路基板を切削して単個にし、ＩＣ実装部を第２基準部材に固定し、第１基準部材を剥離し、下面側を洗浄し、第２基準部材を剥離して単個の半導体パッケージを製造することにより、小型携帯機器等に搭載する信頼性及び生産性の優れた半導体パッケージの製造方法を提供することが可能である。
【図面の簡単な説明】
【図１】本発明の実施の形態に係わる半導体パッケージの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程、ボール付け工程を示す説明図である。
【図２】図１の製造工程後の第１基準部材張り付け工程、ダイシング工程、第２基準部材張り付け工程を示す説明図である。
【図３】図２の製造工程後の第１基準部材剥離工程、洗浄工程を示す説明図である。
【図４】本発明の他の実施の形態に係わる半導体パッケージの製造工程で、第１基準部材張り付け工程、ダイシング工程、第２基準部材張り付け工程を示す説明図である。
【図５】図２の製造工程後の第１基準部材剥離工程、洗浄工程を示す説明図である。
【図６】ＢＧＡ製造工程で問題となるダイシング工程後の切削ごみ付着を示す説明図である。
【図７】従来のＢＧＡの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程、ボール付け工程を示す説明図である。
【図８】従来のＢＧＡの製造工程で、図７の製造工程後の基準部材張り付け工程、ダイシング工程、単個洗浄工程を示す説明図である。
【図９】従来のフリップチップＢＧＡ製造工程で発生するＩＣ欠けを示す説明図である。
【符号の説明】
１ 回路基板
１Ａ 集合回路基板
２ カットライン
３ ＩＣ接続用電極
４ 外部接続用電極
５ 半田ボール
６ ＩＣチップ
７ 封止樹脂
８ａ 基準部材
８ｂ 第１基準部材
８ｃ 第２基準部材
９ ボール電極（突起電極）
１０ ＰＢＧＡパッケージ
１１ 切削ゴミ
１２ ＩＣ欠け[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package having protruding electrodes for external connection.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flip chip bonding has been developed in which a bare chip is directly mounted face-down on a substrate as semiconductor packages become smaller and higher in density. With the advent of camera-integrated VTRs, mobile phones, and the like, mobile devices on which small packages of approximately the same dimensions as bare chips, so-called CSP (chip size / scale packages), have appeared one after another. Recently, the development of CSP is progressing rapidly, and the market demand is in full swing.
[0003]
First, an outline of a method for manufacturing a conventional semiconductor package of a CSP mounted on a small portable device or the like will be described below.
[0004]
First, in the circuit board forming step for taking a large number of pieces shown in FIG. 7A, after forming through holes (not shown) in the collective circuit board 1A covered with copper on both sides, copper plating is performed by electroless copper plating and electrolytic copper plating. After forming a layer, laminating a plating resist, exposing and developing to form a pattern mask, pattern etching is performed using an etching solution, and a plurality of layers are arranged on the upper surface side of the collective circuit board 1A. The IC connection electrode 3 and the external connection electrode 4 which is a pad electrode are formed on the lower surface side. Next, a solder resist treatment is performed to form a resist film on a predetermined portion, so that the external connection electrodes 4 are exposed on the lower surface side of the collective circuit board 1A. An opening portion of a resist film, which is an attachable surface, is formed, and a collective circuit board 1A in which a large number are taken is completed. Reference numeral 2 denotes a cut line orthogonal to the X and Y directions.
[0005]
In the IC mounting process shown in FIG. 7B, first, the IC wafer is passed through a bump process to form solder bumps 5 on the pad electrode surface of the IC wafer. The solder bumps 5 are generally formed by a stud bump method, a ball bump method, a plated bump method, etc., in which a window is formed with a resist at the pad electrode position and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps with a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturization of IC chips.
[0006]
After forming the solder bumps 5, with the IC wafer attached with an adhesive tape or the like, the wafer thickness is cut in the X and Y directions by a full-cut method with a device such as a dicing saw to a predetermined chip size, The IC chip 6 is divided into single pieces.
[0007]
The integrated circuit board 1A in which the IC chips 6 with solder bumps or the integrated circuit board 1A described above are coated with a flux at a predetermined position on the wiring pattern and divided into a plurality of IC chips 6 divided into single pieces. After mounting at a predetermined position on each of the circuit boards 1, flip chip mounting is performed through a solder reflow process.
[0008]
In the sealing step shown in FIG. 7C, the resin is integrally sealed by side potting while straddling the plurality of adjacent IC chips 5 with the thermosetting sealing resin 7. The IC chip 6 is fixed face-down on each circuit board 1 of the collective circuit board 1A.
[0009]
In the ball attaching step shown in FIG. 7D, the ball electrode 9 is formed by placing a solder ball at the position of the external connection electrode 4 formed on the lower surface side of the circuit board 1 and performing reflow.
[0010]
In the reference member attaching step shown in FIG. 8E, the ball electrode of the collective circuit board 1A on which the IC chip 6 is mounted and the ball electrode is formed is attached onto the reference member 8a with a fixing means such as an adhesive or an adhesive tape. The
[0011]
FIG. 8 (f) shows a tiling process, which is cut and divided into pieces by a cutting means such as a dicing saw along the X and Y cut lines 2 described above, and then peeled off from the reference member 8a by a solution or the like. To do.
[0012]
At this time, as shown in FIG. 6A, cutting dust during dicing adheres to the surface of the collective substrate 1A on the side of the reference member 8a and the surface of the solder ball 9.
[0013]
Further, the reference member affixed step shown in FIG. 8 (e), the case of fixing the IC mounted surface and the reference member 8a of the collective circuit board 1A, as shown in FIG. 6 (b), the cutting waste at the time of dicing, the set It adheres to the mounting surface and the surface of the reference member 8a side of the substrate 1A.
[0014]
FIG. 8G shows, in a single cleaning process, the cutting chips adhering to the reference member 8a side surface of the flip chip BGA 20 peeled off from the reference member 8a are put in a scissors, washed and removed. A single PBGA package 20 is completed through the above steps.
[0015]
[Problems to be solved by the invention]
However, the semiconductor package manufacturing method described above has the following problems. In other words, when removing the cutting dust adhering to the package surface on the reference member side, a large number of packages are placed in a basket at the same time for cleaning, so the packages come into contact with each other during cleaning and drying, damaging the package surface, and appearance and reliability. There was a problem with sex. In addition, if the number of pieces placed in the basket at the same time is reduced in order to reduce the contact of the package, there is a problem in that productivity is low and cost is increased.
[0016]
When the IC mounting method is flip-chip mounting, chip edges are missing as shown in FIG. 9, which causes a serious problem in reliability.
[0017]
The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an inexpensive method for manufacturing a semiconductor package which is excellent in reliability and productivity mounted on a small portable device or the like.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention includes forming an external connection electrode on one surface of a circuit board having first and second surfaces and mounting an IC chip on the other surface. In the method of manufacturing a mounted semiconductor package, a circuit board forming step for forming a plurality of bonding patterns for mounting the IC chip and electrode patterns for forming external connection electrodes on the surface of the collective circuit board; and An IC chip mounting step for electrically connecting the bonding pattern and the IC chip; a sealing step for sealing the IC chip with a resin to form a sealing portion; and forming a protruding electrode on the external connection electrode. An assembly forming step of forming a package assembly by an electrode forming step, and a first holding for fixing the first surface side of the package assembly to a first reference member A cutting step of cutting a circuit board of the held package assembly to form a single semiconductor package, and a second step of fixing the second surface side of the package assembly to a second reference member. A holding step, a peeling step of peeling the first reference member from the first surface side of the package assembly, a cleaning step of cleaning the first surface side of the package assembly, and the second And a separation step of removing the single semiconductor package from the reference member.
[0019]
The package assembly is characterized in that the first surface is a protruding electrode surface and the second surface is an IC chip mounting surface.
[0020]
In the first holding step, the protruding electrode is fixed to the reference member with an adhesive.
[0021]
The package assembly is characterized in that the first surface is an IC chip mounting surface and the second surface is a protruding electrode surface.
[0022]
In the first holding step, the sealing portion is fixed to the reference member with an adhesive.
[0023]
Further, the adhesive is an ultraviolet reaction type resin.
[0024]
In the second holding step, the sealing portion is fixed to the reference member with an adhesive.
[0025]
The second holding step is characterized in that the protruding electrode is fixed to the reference member with an adhesive.
[0026]
The adhesive is a heat-reactive resin.
[0027]
Further, the IC chip mounting step is a flip chip mounting step.
[0029]
The protruding electrode is a solder bump.
[0030]
The cutting step is performed by cutting with a dicing saw.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for manufacturing a semiconductor package according to the present invention will be described with reference to the drawings. 1 to 3 are explanatory views showing a manufacturing process of a semiconductor package with bump electrodes according to an embodiment of the present invention. 4 and 5 show another embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.
[0032]
First, the circuit board forming process of FIG. 1A, the IC mounting process of FIG. 1B, the resin sealing process of FIG. 1C, and the ball attaching process of FIG. Since this is the same as FIGS. 7A to 7D, description thereof will be omitted.
[0033]
Further, the first reference member attaching step in FIG. 2E and the dicing step in FIG. 2F are the same as those in FIGS. 8E and 8F in the prior art described above, and the description thereof is omitted. .
[0034]
In the second reference member pasting step shown in FIG. 2G, the IC chip mounting surface is placed on the second reference member 8c in a state where the collective circuit board 1A is cut and divided into pieces on the first reference member. Adhere it with glue.
[0035]
In the first reference member peeling step shown in FIG. 3 (d), the adhesive used in the first reference member attaching step in FIG. 2 (e), for example, the adhesive strength of the UV peeling tape “D638” manufactured by Lintec Corporation. The first reference member 8b and the outside portion of the collective circuit board 1A are peeled off from the second reference member and the product portion.
[0036]
In the cleaning process shown in FIG. 3 (e), the cutting dust generated in the dicing process of FIG. 2 (f) and adhering to the lower surface side of the collective circuit board 1A and the solder ball surface is applied to the second reference member as PBGA. While the package 10 is stuck, it is washed and dropped.
[0037]
Thereafter, the PBGA package 10 is peeled from the second reference member 8c. A single PBGA package is completed through the above steps.
[0038]
4 and 5 show another embodiment of the present invention.
[0039]
In the first reference member attaching step of FIG. 4A, the IC mounting surface of the collective circuit board 1A on which the IC chip 6 completed by the ball attaching step of FIG. Affixed on the reference member 8b with an adhesive.
[0040]
In the tiling process of FIG. 4B, cutting is performed by a cutting means such as a dicing saw along the aforementioned X and Y cut lines 2. At this time, unnecessary portions around the collective circuit board 1A are removed.
[0041]
In the second reference member pasting step shown in FIG. 4C, the solder ball 9 is placed on the second reference member 8c in a state where the collective circuit board 1A is cut and divided into pieces on the first reference member 8b. Adhere to the adhesive.
[0042]
In the first reference member peeling step shown in FIG. 5 (d), the first reference member 8b is peeled off from the second reference member 8c and the product portion in the same manner as in the step of FIG. 3 (d).
[0043]
In the cleaning process shown in FIG. 5 (e), the cutting dust generated in the dicing process of FIG. 4 (b) and adhering to the upper surface side and the sealing surface of the collective circuit board 1A is used as a second reference member for the PBGA package 10. Wash it off while sticking.
[0044]
Thereafter, the PBGA package 10 is peeled from the second reference member 8c. A single PBGA package is completed through the above steps.
[0045]
【The invention's effect】
As described above, according to the semiconductor package manufacturing method of the present invention, a plurality of IC chips are arranged on the upper surface side of the collective circuit board, IC chips are mounted on the circuit board, side-molded with a sealing resin, A protruding electrode is formed on the external connection electrode on the lower surface side, the solder ball is fixed to the first reference member, the collective circuit board is cut into a single piece, the IC mounting portion is fixed to the second reference member, and the first Manufacture of a semiconductor package with excellent reliability and productivity to be mounted on a small portable device by peeling the reference member, cleaning the lower surface side, and peeling the second reference member to manufacture a single semiconductor package It is possible to provide a method.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a circuit board forming process, an IC mounting process, a resin sealing process, and a ball attaching process in a manufacturing process of a semiconductor package according to an embodiment of the present invention.
2 is an explanatory view showing a first reference member attaching step, a dicing step, and a second reference member attaching step after the manufacturing process of FIG. 1; FIG.
3 is an explanatory view showing a first reference member peeling step and a cleaning step after the manufacturing step of FIG. 2; FIG.
FIG. 4 is an explanatory diagram showing a first reference member attaching step, a dicing step, and a second reference member attaching step in a manufacturing process of a semiconductor package according to another embodiment of the present invention.
5 is an explanatory view showing a first reference member peeling step and a cleaning step after the manufacturing step of FIG. 2; FIG.
FIG. 6 is an explanatory diagram showing adhesion of cutting dust after a dicing process, which is a problem in the BGA manufacturing process.
FIG. 7 is an explanatory diagram showing a circuit board forming process, an IC mounting process, a resin sealing process, and a ball attaching process in a conventional BGA manufacturing process.
8 is an explanatory diagram showing a reference member pasting step, a dicing step, and a single cleaning step after the manufacturing step of FIG. 7 in the conventional BGA manufacturing step.
FIG. 9 is an explanatory diagram showing IC chipping that occurs in a conventional flip chip BGA manufacturing process;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 1A Collective circuit board 2 Cut line 3 IC connection electrode 4 External connection electrode 5 Solder ball 6 IC chip 7 Sealing resin 8a Reference member 8b First reference member 8c Second reference member 9 Ball electrode (projection electrode)
10 PBGA package 11 Cutting dust 12 IC chipping

Claims (12)

第１及び第２の面を有する回路基板のいずれか一方の面に外部接続電極を形成し、他方の面にＩＣチップを実装した半導体パッケージの製造方法において、前記ＩＣチップ実装用のボンディングパターンと外部接続用電極を形成するための電極パターンとを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的に接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止して封止部を形成する封止工程と、前記外部接続用電極に突起電極を形成する電極形成工程とによりパッケージ集合体を構成する集合体形成工程と、前記パッケージ集合体の前記第１の面側を第１の基準部材に固定する第１保持工程と、保持されたパッケージ集合体の回路基板を切削して単個の半導体パッケージを形成する切削工程と、前記パッケージ集合体の前記第２の面側を第２の基準部材に固定する第２保持工程と、前記第１の基準部材を前記パッケージ集合体の前記第１の面側から剥離する剥離工程と、前記パッケージ集合体の前記第１の面側を洗浄する洗浄工程と、前記第２の基準部材から前記単個の半導体パッケージを取外す分離工程とからなることを特徴とする半導体パッケージの製造方法。  In a manufacturing method of a semiconductor package in which an external connection electrode is formed on one surface of a circuit board having first and second surfaces and an IC chip is mounted on the other surface, the bonding pattern for mounting the IC chip and A circuit board forming step for forming a plurality of electrode patterns for forming external connection electrodes on the surface of the collective circuit board; and an IC chip mounting step for electrically connecting the bonding pattern and the IC chip; An assembly forming step of forming a package assembly by a sealing step of sealing the IC chip with a resin to form a sealing portion, and an electrode forming step of forming a protruding electrode on the external connection electrode; A first holding step of fixing the first surface side of the package assembly to the first reference member; and cutting the circuit board of the held package assembly to obtain a single semiconductor package. A cutting step of forming a wedge, a second holding step of fixing the second surface side of the package assembly to a second reference member, and the first reference member as the first of the package assembly. A separation step of separating the first semiconductor package from the second reference member, and a separation step of cleaning the first surface side of the package assembly, and a separation step of removing the single semiconductor package from the second reference member. A method of manufacturing a semiconductor package. 前記パッケージ集合体は、第１の面が突起電極面であり、第２の面がＩＣチップ実装面であることを特徴とする請求項１記載の半導体パッケージの製造方法。  2. The method of manufacturing a semiconductor package according to claim 1, wherein the package assembly has a first surface as a protruding electrode surface and a second surface as an IC chip mounting surface. 第１保持工程は、突起電極を第１の基準部材に接着剤で固着することを特徴とする請求項１または２記載の半導体パッケージの製造方法。3. The method of manufacturing a semiconductor package according to claim 1, wherein the first holding step fixes the protruding electrode to the first reference member with an adhesive. 前記パッケージ集合体は、第１の面がＩＣチップ実装面であり、第２の面が突起電極面であることを特徴とする請求項１記載の半導体パッケージの製造方法。  2. The method of manufacturing a semiconductor package according to claim 1, wherein the package assembly has a first surface as an IC chip mounting surface and a second surface as a protruding electrode surface. 第１保持工程は、封止部を第１の基準部材に接着剤で固着することを特徴とする請求項１又は４記載の半導体パッケージの製造方法。5. The method of manufacturing a semiconductor package according to claim 1, wherein the first holding step fixes the sealing portion to the first reference member with an adhesive. 前記接着剤は、紫外線反応型樹脂であることを特徴とする請求項３または５記載の半導体パッケージの製造方法。  6. The method of manufacturing a semiconductor package according to claim 3, wherein the adhesive is an ultraviolet reactive resin. 第２保持工程は、封止部を第２の基準部材に接着剤で固着することを特徴とする請求項１、３または６記載の半導体パッケージの製造方法。7. The method of manufacturing a semiconductor package according to claim 1, wherein the second holding step fixes the sealing portion to the second reference member with an adhesive. 第２保持工程は、突起電極を第２の基準部材に接着剤で固着することを特徴とする請求項１，５または６記載の半導体パッケージの製造方法。7. The method of manufacturing a semiconductor package according to claim 1, wherein the second holding step fixes the protruding electrode to the second reference member with an adhesive. 接着剤は、熱反応型樹脂であることを特徴とする請求項７または８記載の半導体パッケージの製造方法。  9. The method of manufacturing a semiconductor package according to claim 7, wherein the adhesive is a heat-reactive resin. 前記ＩＣチップ実装工程は、フリップチップ実装工程であることを特徴とする請求項１から９のいずれか１項に記載の半導体パッケージの製造方法。The IC chip mounting process, a method of manufacturing a semiconductor package according to any one of claims 1 9, characterized in that a flip-chip mounting process. 前記突起電極は、半田バンプであることを特徴とする請求項１から
１０のいずれか１項に記載の半導体パッケージの製造方法。The protruding electrodes from claim 1, characterized in that the solder bumps
11. A method for manufacturing a semiconductor package according to any one of 10 above. 前記切削工程はダイシングソーによる切削で行うことを特徴とする請求項１から１１のいずれか１項に記載の半導体パッケージの製造方法。The cutting process is a method of manufacturing a semiconductor package according to any one of claims 1 to 11, characterized in that the cutting by the dicing saw.
JP21514198A 1998-07-30 1998-07-30 Manufacturing method of semiconductor package Expired - Lifetime JP4002009B2 (en)

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