JP2000049176A - Production of semiconductor package - Google Patents

Production of semiconductor package

Info

Publication number
JP2000049176A
JP2000049176A JP10215141A JP21514198A JP2000049176A JP 2000049176 A JP2000049176 A JP 2000049176A JP 10215141 A JP10215141 A JP 10215141A JP 21514198 A JP21514198 A JP 21514198A JP 2000049176 A JP2000049176 A JP 2000049176A
Authority
JP
Japan
Prior art keywords
reference member
package
chip
semiconductor package
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10215141A
Other languages
Japanese (ja)
Other versions
JP4002009B2 (en
Inventor
Yoshihiro Ishida
芳弘 石田
Kiyoshi Shimizu
潔 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP21514198A priority Critical patent/JP4002009B2/en
Publication of JP2000049176A publication Critical patent/JP2000049176A/en
Application granted granted Critical
Publication of JP4002009B2 publication Critical patent/JP4002009B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a production method of inexpensive semiconductor package being mounted on a small portable apparatus excellent in reliability and productivity. SOLUTION: A collective package is formed by a step for forming a circuit board by arranging a plurality of a wiring pattern for mounting an IC chip and an electrode pattern for forming external connection electrodes on the surface of a collective circuit board 1A, a step for mounting an IC chip 6 on the wiring pattern, a step for resin sealing an IC chip 5, and a step for fixing solder balls to be fixed with external protruding electrodes and a single complete semiconductor package is formed by a first holding step for securing the external protruding electrodes of the collective package to a first reference member 8b, a step for cutting the collective package thus held along a cut line 2, a second holding step for securing the IC mounting face to a second reference member 8c, a step for peeling off the first reference member 8b, and a step for cleaning the collective package while pasting to the second reference member 8c.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体パッケージの
製造方法に係わり、更に詳しくは外部接続用の突起電極
を有する半導体パッケージの製造方法に関するものであ
る。
The present invention relates to a method of manufacturing a semiconductor package, and more particularly to a method of manufacturing a semiconductor package having a projection electrode for external connection.

【0002】[0002]

【従来の技術】近年、半導体パッケージの小型化、高密
度化に伴いベア・チップを直接フェイスダウンで、基板
上に実装するフリップチップボンディングが開発されて
いる。カメラ一体型VTRや携帯電話機等の登場によ
り、ベア・チップと略同じ寸法の小型パッケージ、所謂
CSP(チップサイズ/スケール・パッケージ)を載せ
た携帯機器が相次いで登場してきている。最近CSPの
開発は急速に進み、その市場要求が本格化している。
2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing.

【0003】先ず、小型携帯機器等に搭載するCSPの
従来の半導体パッケージの製造方法について以下その概
要を説明する。
First, an outline of a conventional method for manufacturing a semiconductor package of a CSP mounted on a small portable device or the like will be described below.

【0004】先ず図7(a)に示す多数個取りする回路
基板形成工程では、両面銅張りされた集合回路基板1A
にスルーホール(図示しない)を形成した後、無電解銅
メッキ及び電解銅メッキにより銅メッキ層を形成し、更
にメッキレジストをラミネートし、露光現像してパター
ンマスクを形成した後、エッチング液を用いてパターン
エッチングを行うことにより、前記集合回路基板1Aの
上面側には複数個分配列したIC接続用電極3、下面側
にパッド電極である外部接続用電極4を形成する。次に
ソルダーレジスト処理を行い、所定の部分にレジスト膜
を形成することにより、前記集合回路基板1Aの下面側
には外部接続用電極4を露呈するように、マトリックス
状に多数の同一形状の半田付け可能な表面であるレジス
ト膜の開口部を形成し、多数個取りする集合回路基板1
Aが完成される。2はX、Y方向に直交するカットライ
ンである。
First, in a circuit board forming step of forming a large number of circuit boards shown in FIG.
After forming a through hole (not shown), a copper plating layer is formed by electroless copper plating and electrolytic copper plating, a plating resist is further laminated, a pattern mask is formed by exposure and development, and an etching solution is used. By performing pattern etching, a plurality of IC connection electrodes 3 arranged in a plurality are formed on the upper surface side of the collective circuit board 1A, and external connection electrodes 4 as pad electrodes are formed on the lower surface side. Next, a solder resist process is performed to form a resist film on a predetermined portion, so that a large number of solders of the same shape are formed in a matrix so that the external connection electrodes 4 are exposed on the lower surface side of the collective circuit board 1A. An integrated circuit board 1 for forming an opening of a resist film, which is a surface that can be attached, and taking a large number of pieces.
A is completed. 2 is a cut line orthogonal to the X and Y directions.

【0005】図7(b)に示すIC実装工程では、先
ず、ICウエハーをバンプ工程に流して前記ICウエハ
ーのパッド電極面に半田バンプ5を形成する。前記半田
バンプ5の形成方法には、一般に、スタッドバンプ方
式、ボールバンプ方式、及びメッキバンプ方式等がある
が、その中で、パッド電極位置にレジストにて窓を形成
し半田浴槽中に浸漬してメッキにて半田バンプを形成す
るメッキバンプ方式は、パッド電極間の狭い配列でバン
プを形成することが可能で、ICチップの小型化には有
効な半田バンプの形成手段である。
In the IC mounting step shown in FIG. 7B, first, an IC wafer is flowed to a bump step to form solder bumps 5 on pad electrode surfaces of the IC wafer. The method of forming the solder bump 5 generally includes a stud bump method, a ball bump method, a plating bump method, etc. Among them, a window is formed with a resist at a pad electrode position, and the window is immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps in a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturizing IC chips.

【0006】前記半田バンプ5を形成後、前記ICウエ
ハーを粘着テープ等で貼着した状態で、所定のチップサ
イズにダイシングソー等の装置でウエハーの厚みをフル
カット方式でX、Y方向に切断した後、ICチップ6を
単体に分割する。
After the solder bumps 5 are formed, the thickness of the wafer is cut in the X and Y directions by a full-cut method with a device such as a dicing saw while the IC wafer is adhered with an adhesive tape or the like. After that, the IC chip 6 is divided into single pieces.

【0007】前記半田バンプ付きICチップ6、又は前
述した集合回路基板1Aの前記配線バターンの所定位置
にフラックスを塗布して、単体に分割した前記ICチッ
プ6を1個づつ複数個分配列した集合回路基板1Aの個
々の回路基板1上の所定位置に搭載した後、半田リフロ
ー工程を経て、フリップチップ実装を行う。
A flux is applied to a predetermined position of the wiring pattern of the IC chip 6 with the solder bumps or the wiring pattern of the above-mentioned collective circuit board 1A, and the IC chips 6 divided into a single unit are arranged in plurals one by one. After being mounted at a predetermined position on each circuit board 1 of the circuit board 1A, flip-chip mounting is performed through a solder reflow process.

【0008】図7(c)に示す封止工程では、熱硬化性
の封止樹脂7で前記隣接する複数個のICチップ5に跨
がった状態で、サイドポッティングにより一体的に樹脂
封止することにより、ICチップ6はフェイスダウンで
集合回路基板1Aの個々の回路基板1上に固定される。
In the sealing step shown in FIG. 7C, the resin is integrally sealed by side potting with the thermosetting sealing resin 7 straddling the plurality of adjacent IC chips 5. By doing so, the IC chip 6 is fixed face down on the individual circuit boards 1 of the collective circuit board 1A.

【0009】図7(d)に示すボール付け工程では、回
路基板1の下面側に形成された外部接続用電極4の位置
に、半田ボールを配置してリフローすることによりボー
ル電極9を形成する。
In the ball attaching step shown in FIG. 7D, a solder ball is arranged at the position of the external connection electrode 4 formed on the lower surface side of the circuit board 1 and reflowed to form the ball electrode 9. .

【0010】図8(e)に示す基準部材張り付け工程で
は、ICチップ6を実装し、ボール電極を形成した集合
回路基板1Aのボール電極を、基準部材8a上に接着剤
又は粘着テープ等の固定手段で張り付ける。
In the reference member attaching step shown in FIG. 8E, the ball electrodes of the collective circuit board 1A on which the IC chip 6 is mounted and the ball electrodes are formed are fixed on the reference member 8a with an adhesive or an adhesive tape. Paste by means.

【0011】図8(f)は、タイシング工程で、前述の
X、Y方向のカットライン2に沿って、ダイシングソー
等の切削手段で単個に切削、分割した後、溶解液等によ
り基準部材8aより剥離する。
FIG. 8 (f) shows a tying step in which a single piece is cut and divided by a cutting means such as a dicing saw along the above-described cut line 2 in the X and Y directions, and then a reference member is formed with a solution or the like. 8a.

【0012】このとき、図6(a)に示すように、ダイシ
ング時の切削ごみが、集合基板1Aの基準部材8a側表
面及び半田ボール9表面に付着する。
At this time, as shown in FIG. 6 (a), cutting dust during dicing adheres to the surface of the collective substrate 1A on the side of the reference member 8a and the surface of the solder ball 9.

【0013】又、図8(e)に示す基準部材張り付け工
程を、集合回路基板1AのIC実装面と基準部材8aで
固定した場合、図6(b)に示すように、ダイシング時
の切削込みが、集合基板1Aの基準部材8a側実装面及
び表面に付着する。
When the reference member attaching step shown in FIG. 8E is fixed to the IC mounting surface of the collective circuit board 1A and the reference member 8a, as shown in FIG. Adhere to the mounting surface and the surface of the collective substrate 1A on the reference member 8a side.

【0014】図8(g)は、単個洗浄工程で、基準部材
8aより剥離したフリップチップBGA20の基準部材
8a側表面に付着した切削かすを篭に入れ、洗浄、落と
す。以上の工程により単個のPBGAパッケージ20が
完成される。
FIG. 8 (g) shows a single-piece cleaning step in which the cutting chips adhered to the surface of the flip chip BGA 20 separated from the reference member 8a on the reference member 8a side are put into a basket, washed and dropped. Through the above steps, a single PBGA package 20 is completed.

【0015】[0015]

【発明が解決しようとする課題】しかしながら、前述し
た半導体パッケージの製造方法には次のような問題点が
ある。即ち、基準部材側のパッケージ表面に付着した切
削かすを取る時、多数個のパッケージを同時に篭に入れ
洗浄するため、洗浄及びその乾燥時、パッケージ同士が
接触し、パッケージ表面を傷つけ、外観及び信頼性に問題
を起こすことがあった。又、パッケージの接触を少なく
するため、同時に篭に入れる個数を少なくすると、生産性
が低く、コストアップ等の問題があった。
However, the above-described method for manufacturing a semiconductor package has the following problems. In other words, when removing the cutting residue attached to the package surface on the reference member side, a large number of packages are simultaneously placed in a basket and washed, so that during cleaning and drying, the packages come into contact with each other, damaging the package surface, and improving the appearance and reliability. There was a problem with gender. In addition, if the number of pieces to be put in the basket at the same time is reduced in order to reduce the contact of the package, there is a problem that productivity is low and cost is increased.

【0016】IC実装法が、フリップチップ実装で成さ
れた場合、図9に示すように、チップエッジが欠け、信頼
性に重大な問題を起こす。
When the IC mounting method is implemented by flip chip mounting, chip edges are chipped as shown in FIG. 9, causing a serious problem in reliability.

【0017】本発明は、上記従来の課題に鑑みなされた
ものであり、その目的は、小型携帯機器等に搭載する信
頼性及び生産性に優れた、安価な半導体パッケージの製
造方法を提供するものである。
The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a method of manufacturing an inexpensive semiconductor package which is excellent in reliability and productivity and is mounted on a small portable device or the like. It is.

【0018】[0018]

【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体パッケージの製造方法は、第
1及び第2の面を有する回路基板のいずれか一方の面に
外部接続電極を形成し、他方の面にICチップを実装し
た半導体パッケージの製造方法において、前記ICチッ
プ実装用のボンディングパターンと外部接続用電極を形
成するための電極パターンとを集合回路基板面に複数個
分配列して形成する回路基板形成工程と、前記ボンディ
ングパターンと前記ICチップを電気的に接続するIC
チップ実装工程と、該ICチップを樹脂封止して封止部
を形成する封止工程と、前記外部接続用電極に突起電極
を形成する電極形成工程とによりパッケージ集合体を構
成する集合体形成工程と、前記パッケージ集合体の前記
第1の面側を第1の基準部材に固定する第1保持工程
と、保持されたパッケージ集合体の回路基板を切削して
単個の半導体パッケージを形成する切削工程と、前記パ
ッケージ集合体の前記第2の面側を第2の基準部材に固
定する第2保持工程と、前記第1の基準部材を前記パッ
ケージ集合体の前記第1の面側から剥離する剥離工程
と、前記パッケージ集合体の前記第1の面側を洗浄する
洗浄工程と、前記第2の基準部材から前記単個の半導体
パッケージを取外す分離工程とからなることを特徴とす
る。
In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention comprises forming an external connection electrode on one of surfaces of a circuit board having first and second surfaces. In the method of manufacturing a semiconductor package having an IC chip mounted on the other surface, a bonding pattern for mounting the IC chip and an electrode pattern for forming an electrode for external connection are arranged on the collective circuit board surface by a plurality of pieces. Circuit board forming step, and an IC for electrically connecting the bonding pattern and the IC chip
Forming an assembly forming a package assembly by a chip mounting step, a sealing step of forming a sealing portion by resin sealing the IC chip, and an electrode forming step of forming a protruding electrode on the external connection electrode And a first holding step of fixing the first surface side of the package assembly to a first reference member; and cutting a circuit board of the held package assembly to form a single semiconductor package. A cutting step, a second holding step of fixing the second surface side of the package assembly to a second reference member, and peeling the first reference member from the first surface side of the package assembly Separating the package assembly, cleaning the first surface side of the package assembly, and separating the single semiconductor package from the second reference member.

【0019】また前記パッケージ集合体は、第1の面が
突起電極面であり、第2の面がICチップ実装面である
ことを特徴とする。
Further, the package assembly is characterized in that the first surface is a protruding electrode surface and the second surface is an IC chip mounting surface.

【0020】また第1保持工程は、突起電極を基準部材
に接着剤で固着することを特徴とする。
The first holding step is characterized in that the protruding electrode is fixed to the reference member with an adhesive.

【0021】また前記パッケージ集合体は、第1の面が
ICチップ実装面であり、第2の面が突起電極面である
ことを特徴とする。
Further, the package assembly is characterized in that the first surface is an IC chip mounting surface and the second surface is a protruding electrode surface.

【0022】また第1保持工程は、封止部を基準部材に
接着剤で固着することを特徴とする。
Further, the first holding step is characterized in that the sealing portion is fixed to the reference member with an adhesive.

【0023】また前記接着剤は、紫外線反応型樹脂であ
ることを特徴とする。
Further, the adhesive is an ultraviolet reactive resin.

【0024】また第2保持工程は、封止部を基準部材に
接着剤で固着することを特徴とする。
Further, the second holding step is characterized in that the sealing portion is fixed to the reference member with an adhesive.

【0025】また第2保持工程は、突起電極を基準部材
に接着剤で固着することを特徴とする。
In the second holding step, the protruding electrode is fixed to the reference member with an adhesive.

【0026】また接着剤は、熱反応型樹脂であることを
特徴とする。
The adhesive is a heat-reactive resin.

【0027】また前記ICチップ実装工程は、フリップ
チップ実装工程であることを特徴とする。
Further, the IC chip mounting step is a flip chip mounting step.

【0028】また前記電極形成工程が、被洗浄部材を用
いた突起電極形成工程であることを特徴とする。
Further, the electrode forming step is a step of forming a protruding electrode using a member to be cleaned.

【0029】また前記突起電極は、半田バンプであるこ
とを特徴とする。
Further, the projection electrode is a solder bump.

【0030】また前記切削工程はダイシングソーによる
切削で行うことを特徴とする。
Further, the cutting step is performed by cutting with a dicing saw.

【0031】[0031]

【発明の実施の形態】以下図面に基づいて本発明におけ
る半導体パッケージの製造方法について説明する。図1
〜図3は本発明の実施の形態で、突起電極付きの半導体
パッケージの製造工程を示す説明図である。図4、図5
は本発明の別の実施の形態である。従来技術と同一部材
は同一符号で示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor package according to the present invention will be described below with reference to the drawings. FIG.
FIG. 3 to FIG. 3 are explanatory views showing a manufacturing process of a semiconductor package having a bump electrode according to an embodiment of the present invention. 4 and 5
Is another embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.

【0032】先ず、図1(a)の回路基板形成工程、図
1(b)のIC実装工程、図1(c)の樹脂封止工程、
図1(d)のボール付け工程は、前述の従来技術の図7
(a)〜(d)と同様であるので、説明は省略する。
First, a circuit board forming step shown in FIG. 1A, an IC mounting step shown in FIG. 1B, a resin sealing step shown in FIG.
The ball attaching step shown in FIG.
(A) to (d), and the description is omitted.

【0033】また図2(e)の第1基準部材張り付け工
程、図2(f)のダイシング工程は、前述の従来技術の
図8(e)、図8(f)と同様であるので、説明は省略
する。
The first reference member attaching step of FIG. 2 (e) and the dicing step of FIG. 2 (f) are the same as those shown in FIGS. 8 (e) and 8 (f) of the above-mentioned prior art. Is omitted.

【0034】図2(g)に示す第2基準部材張り付け工
程では、前記集合回路基板1Aが第1基準部材上で、単
個に切削、分割された状態で、ICチップ実装面を、第
2基準部材8c上に接着剤で張り付ける。
In the second reference member attaching step shown in FIG. 2 (g), in a state where the integrated circuit board 1A is cut and divided on the first reference member, the IC chip mounting surface is moved to the second reference member. It is stuck on the reference member 8c with an adhesive.

【0035】図3(d)に示す第1基準部材剥離工程で
は、図2(e)の第1基準部材張り付け工程で使った接
着剤、例えば、リンテック(株)製の紫外線剥離テープ
「D638」の接着力を紫外線で低下させ、第1基準部材
8bと前記集合回路基板1Aの製品外部分を第2基準部
材及び製品部分より剥離する。
In the first reference member peeling step shown in FIG. 3D, the adhesive used in the first reference member attaching step shown in FIG. 2E, for example, an ultraviolet release tape "D638" manufactured by Lintec Corporation. Of the first reference member 8b and the external part of the integrated circuit board 1A are separated from the second reference member and the product part.

【0036】図3(e)に示した洗浄工程では、図2
(f)のダイシング工程で発生して、前記集合回路基板
1Aの下面側及び半田ボール面に付着した切削ゴミを、
第2基準部材にPBGAパッケージ10を張り付けたま
ま、洗浄して落とす。
In the cleaning step shown in FIG.
The cutting dust generated in the dicing step (f) and adhered to the lower surface side and the solder ball surface of the collective circuit board 1A is
While the PBGA package 10 is stuck to the second reference member, it is washed and dropped.

【0037】その後、PBGAパッケージ10を第2基
準部材8cより剥離する。以上の工程により単個のPB
GAパッケージが完成される。
Thereafter, the PBGA package 10 is peeled off from the second reference member 8c. By the above process, a single PB
The GA package is completed.

【0038】図4、図5は、本発明の他の実施形態を示
す。
FIGS. 4 and 5 show another embodiment of the present invention.

【0039】図4(a)の第1基準部材張り付け工程で
は、図1(d)のボール付け工程により完成したICチ
ップ6を実装し、ボール電極を形成した集合回路基板1
AのIC実装面を、第1基準部材8b上に接着剤で張り
付ける。
In the first reference member attaching step of FIG. 4A, the integrated circuit board 1 on which the IC chip 6 completed by the ball attaching step of FIG.
The IC mounting surface of A is attached to the first reference member 8b with an adhesive.

【0040】図4(b)のタイシング工程では、前述の
X、Y方向のカットライン2に沿って、ダイシングソー
等の切削手段で単個に切削する。この時、集合回路基板
1Aの周囲の不要部分は除去される。
In the tying step shown in FIG. 4B, a single cutting is performed by a cutting means such as a dicing saw along the cut line 2 in the X and Y directions. At this time, unnecessary portions around the collective circuit board 1A are removed.

【0041】図4(c)に示す第2基準部材張り付け工
程は、前記集合回路基板1Aが第1基準部材8b上で、
単個に切削、分割された状態で、半田ボール9を第2基
準部材8c上に接着剤で張り付ける。
In the step of attaching the second reference member shown in FIG. 4C, the assembly circuit board 1A is mounted on the first reference member 8b.
The solder ball 9 is stuck on the second reference member 8c with an adhesive in a state of being cut and divided into single pieces.

【0042】図5(d)に示す第1基準部材剥離工程で
は、図3(d)の工程と同様にして、第1基準部材8b
を第2基準部材8c及び製品部分より剥離する。
In the first reference member peeling step shown in FIG. 5D, the first reference member 8b is formed in the same manner as in the step of FIG. 3D.
From the second reference member 8c and the product part.

【0043】図5(e)に示す洗浄工程では、図4
(b)のダイシング工程で発生し、前記集合回路基板1
Aの上面側及び封止面に付着した切削ゴミを、第2基準
部材にPBGAパッケージ10を張り付けたまま、洗浄
して落とす。
In the cleaning step shown in FIG.
(B) generated in the dicing step,
The cutting dust adhering to the upper surface side and the sealing surface of A is washed and dropped while the PBGA package 10 is adhered to the second reference member.

【0044】その後、PBGAパッケージ10を第2基
準部材8cより剥離する。以上の工程により単個のPB
GAパッケージが完成される。
Thereafter, the PBGA package 10 is peeled off from the second reference member 8c. By the above process, a single PB
The GA package is completed.

【0045】[0045]

【発明の効果】以上説明したように、本発明の半導体パ
ッケージの製造方法によれば、前記集合回路基板の上面
側に複数個分配列して回路基板にICチップを実装し、
封止樹脂でサイドモールドして、下面側の外部接続用電
極に突起電極を形成し、半田ボールを第1基準部材に固
定し、集合回路基板を切削して単個にし、IC実装部を
第2基準部材に固定し、第1基準部材を剥離し、下面側
を洗浄し、第2基準部材を剥離して単個の半導体パッケ
ージを製造することにより、小型携帯機器等に搭載する
信頼性及び生産性の優れた半導体パッケージの製造方法
を提供することが可能である。
As described above, according to the semiconductor package manufacturing method of the present invention, a plurality of IC chips are arranged on the circuit board by arranging a plurality of IC chips on the upper surface side of the collective circuit board.
Side-molding with a sealing resin, forming protruding electrodes on the external connection electrodes on the lower surface side, fixing the solder balls to the first reference member, cutting the collective circuit board into single pieces, By fixing to the second reference member, peeling the first reference member, cleaning the lower surface side, and peeling the second reference member to manufacture a single semiconductor package, the reliability of mounting on a small portable device and the like is improved. It is possible to provide a method for manufacturing a semiconductor package having excellent productivity.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係わる半導体パッケージ
の製造工程で、回路基板形成工程、IC実装工程、樹脂
封止工程、ボール付け工程を示す説明図である。
FIG. 1 is an explanatory view showing a circuit board forming step, an IC mounting step, a resin sealing step, and a ball attaching step in a manufacturing process of a semiconductor package according to an embodiment of the present invention.

【図2】図1の製造工程後の第1基準部材張り付け工
程、ダイシング工程、第2基準部材張り付け工程を示す
説明図である。
FIG. 2 is an explanatory view showing a first reference member attaching step, a dicing step, and a second reference member attaching step after the manufacturing step of FIG. 1;

【図3】図2の製造工程後の第1基準部材剥離工程、洗
浄工程を示す説明図である。
FIG. 3 is an explanatory view showing a first reference member peeling step and a cleaning step after the manufacturing step of FIG. 2;

【図4】本発明の他の実施の形態に係わる半導体パッケ
ージの製造工程で、第1基準部材張り付け工程、ダイシ
ング工程、第2基準部材張り付け工程を示す説明図であ
る。
FIG. 4 is an explanatory view showing a first reference member attaching step, a dicing step, and a second reference member attaching step in a semiconductor package manufacturing step according to another embodiment of the present invention.

【図5】図2の製造工程後の第1基準部材剥離工程、洗
浄工程を示す説明図である。
FIG. 5 is an explanatory view showing a first reference member peeling step and a cleaning step after the manufacturing step of FIG. 2;

【図6】BGA製造工程で問題となるダイシング工程後
の切削ごみ付着を示す説明図である。
FIG. 6 is an explanatory view showing adhesion of cutting dust after a dicing step, which is a problem in a BGA manufacturing process.

【図7】従来のBGAの製造工程で、回路基板形成工
程、IC実装工程、樹脂封止工程、ボール付け工程を示
す説明図である。
FIG. 7 is an explanatory view showing a circuit board forming step, an IC mounting step, a resin sealing step, and a ball attaching step in a conventional BGA manufacturing process.

【図8】従来のBGAの製造工程で、図7の製造工程後
の基準部材張り付け工程、ダイシング工程、単個洗浄工
程を示す説明図である。
FIG. 8 is an explanatory view showing a reference member attaching step, a dicing step, and a single-piece cleaning step after the manufacturing step of FIG. 7 in a conventional BGA manufacturing step.

【図9】従来のフリップチップBGA製造工程で発生す
るIC欠けを示す説明図である。
FIG. 9 is an explanatory diagram showing an IC chip occurring in a conventional flip chip BGA manufacturing process.

【符号の説明】[Explanation of symbols]

1 回路基板 1A 集合回路基板 2 カットライン 3 IC接続用電極 4 外部接続用電極 5 半田ボール 6 ICチップ 7 封止樹脂 8a 基準部材 8b 第1基準部材 8c 第2基準部材 9 ボール電極(突起電極) 10 PBGAパッケージ 11 切削ゴミ 12 IC欠け DESCRIPTION OF SYMBOLS 1 Circuit board 1A Collective circuit board 2 Cut line 3 IC connection electrode 4 External connection electrode 5 Solder ball 6 IC chip 7 Sealing resin 8a Reference member 8b First reference member 8c Second reference member 9 Ball electrode (projection electrode) 10 PBGA package 11 Cutting dust 12 IC chip

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 第1及び第2の面を有する回路基板のい
ずれか一方の面に外部接続電極を形成し、他方の面にI
Cチップを実装した半導体パッケージの製造方法におい
て、前記ICチップ実装用のボンディングパターンと外
部接続用電極を形成するための電極パターンとを集合回
路基板面に複数個分配列して形成する回路基板形成工程
と、前記ボンディングパターンと前記ICチップを電気
的に接続するICチップ実装工程と、該ICチップを樹
脂封止して封止部を形成する封止工程と、前記外部接続
用電極に突起電極を形成する電極形成工程とによりパッ
ケージ集合体を構成する集合体形成工程と、前記パッケ
ージ集合体の前記第1の面側を第1の基準部材に固定す
る第1保持工程と、保持されたパッケージ集合体の回路
基板を切削して単個の半導体パッケージを形成する切削
工程と、前記パッケージ集合体の前記第2の面側を第2
の基準部材に固定する第2保持工程と、前記第1の基準
部材を前記パッケージ集合体の前記第1の面側から剥離
する剥離工程と、前記パッケージ集合体の前記第1の面
側を洗浄する洗浄工程と、前記第2の基準部材から前記
単個の半導体パッケージを取外す分離工程とからなるこ
とを特徴とする半導体パッケージの製造方法。
An external connection electrode is formed on one surface of a circuit board having first and second surfaces, and an I / O electrode is formed on the other surface.
In a method of manufacturing a semiconductor package having a C chip mounted thereon, a circuit board is formed by arranging a plurality of bonding patterns for mounting the IC chip and electrode patterns for forming electrodes for external connection on a surface of a collective circuit board. An IC chip mounting step of electrically connecting the bonding pattern to the IC chip; a sealing step of sealing the IC chip with a resin to form a sealing portion; An assembly forming step of forming a package assembly by an electrode forming step of forming a package, a first holding step of fixing the first surface side of the package assembly to a first reference member, and a held package A cutting step of cutting the circuit board of the assembly to form a single semiconductor package;
A second holding step of fixing the first reference member to the reference member, a separating step of separating the first reference member from the first surface side of the package assembly, and cleaning the first surface side of the package assembly. And a separating step of removing the single semiconductor package from the second reference member.
【請求項2】 前記パッケージ集合体は、第1の面が突
起電極面であり、第2の面がICチップ実装面であるこ
とを特徴とする請求項1記載の半導体パッケージの製造
方法。
2. The method of manufacturing a semiconductor package according to claim 1, wherein the first surface of the package assembly is a protruding electrode surface, and the second surface is an IC chip mounting surface.
【請求項3】 第1保持工程は、突起電極を基準部材に
接着剤で固着することを特徴とする請求項1または2記
載の半導体パッケージの製造方法。
3. The method according to claim 1, wherein in the first holding step, the protruding electrode is fixed to the reference member with an adhesive.
【請求項4】 前記パッケージ集合体は、第1の面がI
Cチップ実装面であり、第2の面が突起電極面であるこ
とを特徴とする請求項1記載の半導体パッケージの製造
方法。
4. The package assembly according to claim 1, wherein the first surface is I-shaped.
2. The method according to claim 1, wherein the mounting surface is a C-chip mounting surface, and the second surface is a protruding electrode surface.
【請求項5】 第1保持工程は、封止部を基準部材に
接着剤で固着することを特徴とする請求項1または4記
載の半導体パッケージの製造方法。
5. The method according to claim 1, wherein in the first holding step, the sealing portion is fixed to the reference member with an adhesive.
【請求項6】 前記接着剤は、紫外線反応型樹脂である
ことを特徴とする請求項3または5記載の半導体パッケ
ージの製造方法。
6. The method according to claim 3, wherein the adhesive is an ultraviolet-reactive resin.
【請求項7】 第2保持工程は、封止部を基準部材に
接着剤で固着することを特徴とする請求項1、3または
6記載の半導体パッケージの製造方法。
7. The method for manufacturing a semiconductor package according to claim 1, wherein in the second holding step, the sealing portion is fixed to the reference member with an adhesive.
【請求項8】 第2保持工程は、突起電極を基準部材
に接着剤で固着することを特徴とする請求項1、5また
は6記載の半導体パッケージの製造方法。
8. The method according to claim 1, wherein in the second holding step, the protruding electrode is fixed to the reference member with an adhesive.
【請求項9】 接着剤は、熱反応型樹脂であることを特
徴とする請求項7または8記載の半導体パッケージの製
造方法。
9. The method according to claim 7, wherein the adhesive is a heat-reactive resin.
【請求項10】 前記ICチップ実装工程は、フリップ
チップ実装工程であることを特徴とする請求項1から9
記載の半導体パッケージの製造方法。
10. The IC chip mounting step is a flip chip mounting step.
The manufacturing method of the semiconductor package described in the above.
【請求項11】 前記電極形成工程が、被洗浄部材を用
いた突起電極形成工程であることを特徴とする請求項1
から10記載の半導体パッケージの製造方法。
11. The method according to claim 1, wherein the step of forming an electrode is a step of forming a protruding electrode using a member to be cleaned.
11. The method for manufacturing a semiconductor package according to items 10 to 10.
【請求項12】 前記突起電極は、半田バンプであるこ
とを特徴とする請求項11記載の半導体パッケージの製
造方法。
12. The method according to claim 11, wherein the protruding electrodes are solder bumps.
【請求項13】 前記切削工程はダイシングソーによる
切削で行うことを特徴とする請求項1から12記載の半
導体パッケージの製造方法。
13. The method of manufacturing a semiconductor package according to claim 1, wherein said cutting step is performed by cutting with a dicing saw.
JP21514198A 1998-07-30 1998-07-30 Manufacturing method of semiconductor package Expired - Lifetime JP4002009B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21514198A JP4002009B2 (en) 1998-07-30 1998-07-30 Manufacturing method of semiconductor package

Publications (2)

Publication Number Publication Date
JP2000049176A true JP2000049176A (en) 2000-02-18
JP4002009B2 JP4002009B2 (en) 2007-10-31

Family

ID=16667378

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003044806A (en) * 2001-07-27 2003-02-14 Toppan Forms Co Ltd Method for mounting ic chip of rf-id media onto antenna
JP2013247124A (en) * 2012-05-23 2013-12-09 Panasonic Corp Mounting device and mounting method for semiconductor element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164336A (en) * 1986-12-26 1988-07-07 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH02125633A (en) * 1988-11-04 1990-05-14 Nec Corp Integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164336A (en) * 1986-12-26 1988-07-07 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH02125633A (en) * 1988-11-04 1990-05-14 Nec Corp Integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003044806A (en) * 2001-07-27 2003-02-14 Toppan Forms Co Ltd Method for mounting ic chip of rf-id media onto antenna
JP2013247124A (en) * 2012-05-23 2013-12-09 Panasonic Corp Mounting device and mounting method for semiconductor element

Also Published As

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