JPS60957B2 - Manufacturing method for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a pressure contact type semiconductor device, and is particularly applicable to transistors and gate turn-off thyristors (hereinafter referred to as G
(abbreviated as TO), relates to a method for manufacturing semiconductor devices such as high frequency thyristors.

FIGS. 1, 2, and 3 show examples of conventional GTOs. Figure 2 shows the Rollo cross section of Figure 1.
The figure shows a portion of FIG. 2 in enlarged form. In the figure,
A voltage is applied in the positive direction to the anode electrode 10 that supports and fixes the semiconductor substrate 1, a voltage is applied in the negative direction to the cathode electrode 9 which is pressed into contact with the semiconductor substrate 1 from above, and a forward bias voltage is applied between the gate electrode 7 and the cathode electrode 9. Then, by turning on the semiconductor substrate 1 and applying a reverse bias voltage between the gate electrode 7 and the cathode electrode 9, the semiconductor substrate 1 in the on state can be returned to the off state again.

In this way, GTO differs from normal Siris, in that it has a gate
It is necessary to improve the reverse direction characteristics between the cathodes. More specifically, in addition to reducing the reverse leakage current between the gate and cathode and increasing the reverse breakdown voltage, it is necessary to reduce the lateral resistance of the P base layer 3 on which the gate electrode 7 is provided. For this purpose, the N emitter layer 2 with which the cathode electrode 9 comes in contact is shaped like an elongated tanza, and the P base layer 3 has a structure surrounding the N emitter layer 2. The width of the electrode 6 (hereinafter abbreviated as emitter electrode) fixedly contacted on the N emitter layer 2 is usually 500 ridges or less, and the thickness of the emitter electrode 6 is about 10 μm. Therefore, in order to increase the current capacity of the GTO, the voltage drop along the length of the emitter electrode 6 becomes too large to be ignored as the length of the N emitter layer 2 is increased, and in the end, the entire surface of the emitter layer 2 cannot operate effectively. This makes it difficult to increase capacity. In order to solve this problem, the thick cathode electrode 9 is brought into contact with the entire surface of the emitsu yugiri pole 6 so that the main current path is substantially perpendicular to the electrode and the resistance of the electrode part is not affected. . Since the emitter electrodes 6 are embedded in each other, the flat cathode electrode 9 cannot be brought into contact with only the emitter electrode 6 as it is. In order to solve this problem, there is a method of making the emitter electrode 6 and the gate electrode 7 different in height, and the gate electrode 7 of the cathode electrode 9 that should be in contact with the emitter electrode 6.
There is a way to make the area corresponding to the area concave. The semiconductor substrate 1 is composed of an N emitter layer 2, a P base layer 3, an N base layer 4, and a P emitter layer 5, as shown in FIG. A surface stabilizing film is provided except for the portion where the gate electrode 7
An insulating film is provided on the top for insulation from the cathode electrode 9, but is omitted in the drawing for the sake of simplification.

When a reverse bias voltage is applied between the gate electrode 7 and the cathode electrode 9 to the turned-on GTO, the GTO attempts to return to the turned-off state.

However, if one of the emitter electrodes 6 is defective at this time, that is, if there is an emitter electrode whose gate trigger voltage or gate trigger current during reverse bias is smaller than other emitter electrodes, that emitter electrode Since the turn-off time of the electrode tends to be longer than that of other emitter electrodes, the OTO cannot completely return to the turn-off state.
The current flowing between the anode electrode 10 and the cathode electrode 9 concentrates on this defective emitter electrode 6, resulting in a poor turn-off condition, which causes local heating of this area and the semiconductor. There was a risk that the base 1 would be destroyed. An object of the present invention is to solve the above-mentioned disadvantages of the conventional method and to provide an improved method for manufacturing a semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device with improved gate turn-off performance.

In order to achieve this purpose, the defective emitter electrode of the cathode electrode formed surrounded by one of the main electrodes is removed.

The present invention will be explained below using drawings showing embodiments.

In the embodiment shown in FIG. 4, the same parts as in FIGS. 1, 2, and 3 are designated by the same reference numerals as in FIGS. 1, 2, and 3.

In FIG. 4, the semiconductor substrate 1 and the anode electrode 10 are fixed to each other through a brazing material 8', aluminum is vacuum-deposited for about 10 minutes, and a gate electrode 7 is formed using a photo-etching technique.

In this state, the gate trigger voltage and current of the gate electrode 7 and each emitter electrode 6 are measured, and if there is an abnormality in which the voltage and current are smaller than those of other emitter electrodes, photo-etching technology is used to remove the abnormal emitter electrode 6. Remove. Next, the cathode electrode 9 is placed on the emitter electrode 6 and pressurized. An insulator is provided on the removed abnormal emitter electrode for insulation from the cathode electrode 9, but like the surface stabilizing film and the insulating film on the gate electrode 7, it is omitted in the drawing for simplicity.

According to the present invention, the abnormal emitter electrode is detected and removed in a junction state, current does not flow from the abnormal emitter electrode to the cathode electrode 9, and the turn-off operation is performed only with the normal emitter electrode, so that the turn-off performance is improved. can do.

In addition, since the current does not concentrate on the abnormal emitter electrode, this part will not be locally heated and the semiconductor substrate will not be destroyed.This improves the stability and reduces the cost of the product. Next, the effects will be explained using specific numerical values.

The diameter of the semiconductor substrate 1 is 3, and the number of emitter electrodes 6 is 7.
Regarding GTOs with two emitter electrodes and a rated current of 60, 28% of them had an abnormality in one emitter electrode, 6% had an abnormality in two emitter electrodes,
There were 1% cases in which three emitter electrodes were abnormal, and none of them could be turned off. Therefore, according to the present invention, when the emitter electrodes were removed from those with these abnormalities, good gate turn-off performance was obtained for all of them.

As explained in detail above, according to the present invention, current flows uniformly in each part of the emitter electrode of the semiconductor substrate.
Gate turn-off performance can be improved.

[Brief explanation of drawings]

Figures 1 to 3 show a conventional GTO, where Figure 1 is a plan view of the N emitter layer side, Figure 2 is a sectional view taken along the Rollo cutting line in Figure 1, and Figure 3 is a An enlarged view of a part of the figure
FIG. 4 is a diagram showing an embodiment of the present invention. 1... Semiconductor substrate, 2... N emitter layer, 3...
...P base layer, 4...N base layer, 5...P emitter layer "6..., emitter electrode, 7... gate electrode"
8... Brazing metal, 9... Cathode electrode L I0...
...Anode electrode. Festival I Figure 2 Figure 2 Crowding Figure 4

Claims (1)

[Claims] 1 At least two layers are exposed on one main surface of the semiconductor substrate, one layer is divided and each surrounded by the other layer, and each of the divided layers and the other layer are separated. In a semiconductor device in which a second electrode is contacted to each of the first electrodes on each of the divided portions of one layer, and a second electrode is further contacted to each of the first electrodes on each of the divided portions of one layer. For each electrode, remove abnormal electrodes,
A method for manufacturing a semiconductor device, comprising bringing a second electrode into contact with each of the remaining normal first electrodes.