JPS6092655A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To accomplish a CIGF constitution using only one laminated body by a method wherein, in the laminated type complementary insulated gate type semiconductor device (CIGF) of longitudinal channel type, the mounting of one conductive electrode of the laminated body is formed in common manner. CONSTITUTION:A conductive film 2, the first non-single crystal semiconductors 3 and 3' of P and N type, the second semiconductor or insulating material 4, an N type semiconductor 5', the third semiconductor 5, the second conductor 6, and a silicon oxide film 7 are formed on a substrate 1, and laminated bodies 50 and 50' are formed by performing a selective etching. The fourth semiconductor 35 of non-single crystal constituting a channel forming region is laminated covering blocks 10 and 10', and a silicon nitride film 34 is formed. The second conductive film 30 is formed, an aniotropic etching is performed, and the residues located on the side circumference of the laminated bodies 50 and 50' are used as electrodes 40-43. The block 10' constitutes an inverter, and the block 10 constitutes a switch. In the block 10', the gates 40 and 41 are made common, and they are connected to an input 61 by passing through along the side circumference of the laminated body 50'.

Description

Detailed Description of the Invention The present invention relates to a vertical channel stacked complementary insulated gate semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.
It relates to complementary IGF &;l:C/IGF).

The present invention is a laminate consisting of a first conductive electrode, a first semiconductor, a second semiconductor or insulator, a third semiconductor, and a second conductive electrode on an insulating substrate. A fourth non-single crystal semiconductor that forms a channel is further provided around the two sides, and one side is connected to the
The purpose is to provide a channel type IGF (hereinafter referred to as PIGF) and the other to provide an N-channel IGF (hereinafter referred to as NIGF).

The present invention connects C/IGFs in series to form an inverter configuration by using one laminate and making one of the conductive electrodes common to each other.
The switch is constructed by connecting F in parallel and providing both electrodes in common, and is characterized by a C/IGF configuration even though it is a single laminate.

Conventionally, complementary insulated gate field effect semiconductor devices (hereinafter also referred to as C7MO3) using single crystal silicon are known.

An example of this is shown in FIG.

As is clear from the drawing, an N-type single crystal silicon substrate (
1) A P well (94) is provided, and isolation is provided by a buried field insulator (93) to form an N-channel MO5, FET (52), and a P-channel MO5 PU.
T (51) are respectively sources (13')-(13),
Drain (15'> (15), gate electrode (41),
(40) is shown.

The integrated circuit (IC) of this C/MO5 is a horizontal channel type, and electrically includes three diodes (90).

(91), <92).

In order to provide these three diodes, the isolation area becomes large, and an area 1.8 to 2.5 times that required for two IGFs of the same channel type is required.

This is because this semiconductor is a single crystal, and is an unavoidable drawback. As a result, problems such as the lunch-up phenomenon occurred.

However, the inventors have found that if a non-single crystal semiconductor containing amorphous silicon is used instead of this single crystal semiconductor as the semiconductor, such isolation becomes substantially unnecessary and the concept can be changed.

The present invention provides a non-single crystal semiconductor, and C/IGF
(Since it is a stacked vertical channel, it is called IGF here to distinguish it from MOS and FHT devices used in conventional horizontal channel single crystal semiconductors.) C/1 even though the same laminate is used without providing
．． I was able to get G17.

That is, in a non-single crystal semiconductor, if the thickness is 20 times or more than the thickness of the formed semiconductor film, it can be completely treated as an insulator. That is, P, 1. When the thickness of N is 0.1 μ, 1 μ, and 0.1 μ, respectively, the width is 2 μ,
20μ, 2μ or more can be substantially treated as an insulator. Furthermore, a PN junction in which a P-type non-single crystal semiconductor and an N-type non-single crystal semiconductor are stacked exhibits ohmic contact;
Only IN, PI, and Nl junctions (wherein an I-type semiconductor has an impurity concentration of B or P of 5 x 10'' cm-3 or less) exhibit diode characteristics.

Therefore, in the present invention, it was possible to provide a C/IGF with a small cell area, which is completely different from C/MO5, using a conventional single crystal semiconductor.

The present invention is characterized by configuring two IGFs as a pair in the same laminate to reduce the area required for isolation and IGF wiring. That is, compared to single crystal C7MO5, no particular area is required for isolation. Furthermore, by making it a vertical channel type,
The fourth semiconductor, which constitutes the channel formation region, is a non-single crystal semiconductor whose main component is silicon doped with hydrogen or fluorine. Furthermore, it is a non-single-crystal semiconductor, and has the disadvantage of having lower carrier mobility than this single-crystal semiconductor. Therefore, in the present invention, the film thickness of the second semiconductor or insulator is 1 μm or less, and as a result, the channel formed in the semiconductor of box 4 is a short channel, and has a cutoff frequency of 10 MIIz or more. .

In this way, by combining the present invention based on the design specifications, it was possible to create a circuit that can be applied to peripheral circuits of solid-state display devices for flat-screen TVs that replace cathode ray tubes.

FIG. 2 shows a longitudinal cross-sectional view of a stacked IGF for carrying out the present invention and its manufacturing process.

This drawing shows PIGF (51), (54) and NIGF.
A manufacturing example is shown in which two IGFs (52>, <53) are fabricated into one laminate. In particular, the drawing shows an inverter (10') in which C/lGp is connected in series, and a switch (10') in which C/lGp are connected in parallel. are shown in the left and right areas, respectively. Furthermore, the same process can be used to improve the degree of integration.

In FIG. 2(A), tin oxide + TiS is deposited on an insulating substrate (1) of quartz glass or borosilicate glass.
A first conductive film (2) such as tl +W+'Cr was provided as a lower electrode and lead. In this embodiment, a conductive film containing Cr as a main component is formed to a thickness of 0.2 μm. Selective etching was performed on this using the first mask (3). Further, on this upper surface, a first non-single crystal semiconductor (hereinafter referred to as P type X 3 ) (hereinafter simply referred to as 51) having a conductivity type of P or N type was formed by 100 to 3000 people by a known pcvCD method. Furthermore, the N-type non-single crystal semiconductor (3') is
It was made to a thickness of 00 to 1000 people. In the drawing, the P-type semiconductor (3) is 5ixC1-x (0<X≦1, e.g.
．． 1), and an N-type semiconductor (3') was a microcrystalline semiconductor. After this, the N-type semiconductor was etched with hydrazine using a second mask (3). ) (hereinafter referred to as D32) (0,3~3μ
) were laminated by PCVD method. Here 5i3N4-
(0<x<4). That is, at x=0, it becomes an insulator,
When Q<x<4, it becomes a semiconductor or a semi-insulator. Furthermore, a microcrystalline N-type semiconductor (5') is formed again to a thickness of 200 to 1000 nm, and selectively etched with a third mask. 3 semiconductors (5〉 (hereinafter simply referred to as S3) x200 ~ 0.2μ) were laminated (stacked or referred to as S). Through this lamination, the regions (51) and <54) formed a III+' structure (l has an insulator or an intrinsic semiconductor) and a region (52
), < 53) had a NIN junction (actually l'NINP junction).

In the drawing, ζ, PN junction is IGF due to ohmic contact.
.

At the end, it becomes the old N junction.

In FIG. 2(A), ITO (
indium tin oxide), Mo5iL, 1tst,
A second conductor (6) made of a heat-resistant metal such as Ti, Mo, or the like, here Cr, was laminated to a thickness of 0.2 μm by an electron beam method. Next, of this second conductor, the laminate (5
0), <50') was removed using the fourth FNA 1-Mask (2).

Furthermore, LP CVD method (low pressure vapor phase method), PC
A silicon oxide film (7) with a thickness of 0.3 to 1 μm was formed by a VD method or a photo-CVD method. In the case of PCVD method, N,
The reaction between O and S s I (4) was carried out at 250°C.

The N and P layers of the first and third semiconductors are
P as N'NINN+, P"PIPP" (I is an insulator or an intrinsic semiconductor) as P or N and the first and second
It was effective to lower the contact resistance with one pole.

In this way, the first conductor, the first semiconductor, the second semiconductor or insulator, the third semiconductor, and the second conductor were formed into layers.

Next, as shown in FIG. 2(B), the insulator (7), conductor (6), Sl, S2. S
3 is removed by a selective etching method to obtain a laminate (50),
(50') was formed. That is, the laminate (50), <50
'> respective second conductors (16), (26)
and 07ri (10') (10) 4 pieces apart, 5
1, 52, and 53 were formed to have approximately the same shape. All of these were microwaved (2,45
GIIZ's anisotropic plasma vapor phase etching method was used.

Etching gas CI5. A gas mixture of liver or CIFOL was used. The pressure was 0.1 to 0.5 torr, the output was 200, and the etch rate was 200 people/min.

After this, these laminates (50') and the blocks (10
') in the first conductor (12>, (12'), Sl
(13), <13'), 52 (14), S3 (15)
, <15'), second conductor (16) and block (1
0), the first conductor (22), Sl (23).

(23'), 52 (24), 53 (25<25
'), an intrinsic, P or N type non-single crystal semiconductor was laminated as a fourth semiconductor (35) to cover the conductor (26) of 〒2 and constitute a channel formation region. This fourth semiconductor (35) is manufactured using a silane glow discharge method (P) on the substrate.
CVD method), photo CVD method, LT CVD method (IIOMO
(also referred to as CVD method), the temperature range from room temperature to 500°C, e.g. 250°C in PCVD method, is 10,1 torr.
, 30 W, and 13.56 MIIx, and uses an amorphous, semi-amorphous, or polycrystalline non-single crystal silicon semiconductor. The present invention focuses on amorphous or semi-amorphous silicon semiconductors doped with hydrogen or fluorine.

Furthermore, a silicon nitride film (34) is coated on the top surface in the same reactor without exposing the fourth semiconductor surface to the atmosphere.
Silane (disilane is also acceptable) and ammonia are produced by a gas phase reaction using mercury excitation using the VD method, and the thickness is 300-2.
000 people.

This insulating film may be immersed in a nitrogen or ammonia atmosphere activated by electromagnetic energy at a frequency of 13.56 M11z to 2.45 GIIz for 100 to 400''c to form silicon nitride in a solid-vapor phase reaction.

Alternatively, silicon nitride may be formed by a PCVD method.

Then, 52 (around the 14 person (24) side, the channel forming region (9), <9') and the gate insulator (3
4). The fourth semiconductor (25) is sl
, S3 constitute a diode junction.

This fourth semiconductor (35) (e.g. P-type silicon) and the gate insulator (34) are first placed in a region (52), <53).
Further, with a silicon oxide mask, another fourth semiconductor (for example, N-type silicon) and an insulator are laminated in the regions (51) and (54), and Using a semiconductor doped with a small amount of P- or N- type impurity is effective in controlling the threshold voltage, although the number of masks increases.

In FIG. 2(B), electrode holes are further made using the sixth mask (2), and then the silicon nitride film (2
4), a second conductive film (30) was formed to a thickness of 0.3 to 1 μm.

This conductive film (30) is a transparent conductive film such as ITO (indium tin oxide), Ti5ii, Mo5iiJ.
SiL.

A heat-resistant conductive film such as W+Tj+Mo may also be used. Here, a silicon semiconductor doped with a large amount of N-type impurities was manufactured by PCVD. That is, a microcrystalline (grain size 50 to 300) non-single crystal semiconductor having a thickness of 0.4 μm and having 1% phosphorus added thereto was fabricated by the PCVO method.

After that, a resist (3
8), (38') was formed.

Furthermore, as shown in FIG. 2C, anisotropic etching in the vertical direction was performed using the seventh photolithography technique (1) in the same manner as in the fifth photolithography. That is, for example, a reactive gas such as CFLCIL, CF4+OL+liver, etc. was turned into plasma using microwaves, and this plasma was further applied from above the substrate. Then, the conductor (30) is placed on the plane (
This coating is removed by etching a thickness of 0.4 .mu. on the top surface), but on the sides it has 2 to 3 .mu. of the sum of the laminate thickness and the coating thickness in the vertical direction. Therefore, if anisotropic etching is performed in the vertical direction as shown in the drawing,
Mask these conductors (38) as shown by broken lines (39) and (39').

It was possible to leave it in areas other than the area (3B').

As a result, it was possible to selectively provide gate residues (39) and (39') only around the sides of the stacked bodies (50) and (50'). Furthermore, in the present invention, this residual material is made into a gate electrode (40), <41), <42), <43), and does not exist above the second semiconductor (16), <26), resulting in The parasitic capacitance between the semiconductor of No. 2 and the gate electrode could be made substantially equal to zero.

In the drawing, the gate electrode and its leads (40) to (4
3) The conductors around the other side except 3) were removed by horizontal vapor phase etching using an eighth photomask (3), and each gate was operated independently.

Thus, Figure 2 <C> was obtained.

The plan view of FIG. 2(C) is shown as FIG. 3(A). Further, its electrical equivalent circuit is shown in FIG. 3(B). It is clear from the drawing that (51) and (54) are PIGF.

(52) and (53) are NIGF. The numbers correspond to those in FIG. 2(C).

As is clear from FIGS. 3(A) and 3(B) and FIG. 2(C), one block has two IGFs configured relative to each other as a C/IGF. Here are four IGFs
(51) to (54), and channels (9>, (9')
) and four. The block (10'> is an inverter, and the block (lO) is a switch. Therefore, in the block (10'), the gate electrode (40),
<41) is common and is connected to the input (61) along the periphery of the stacked body (50'). The output (64) is derived from the upper side. Drain voltage v2. (65).

v! , is connected to (60). The important point here is that in (71) in Figure 2 (C), V + vG is a non-single crystal, so it can be insulated without providing an isolation region like a single crystal semiconductor. It is.

NIGF also has conductors (12'), (16), P semiconductors (13), <15) and N semiconductors (13') (1
5'), there is no problem at all.

That is, in the drawing, two IGFs (51), <52) can be provided as a pair. This is two IG
the semiconductor or insulator between the channels of F is insulating;
If Sl, 32.53 has a width of 20 l or more, it is several tens of MΩ.
This is because it becomes a resistance and can be practically configured independently.
By utilizing this property, it was possible to create a structure completely different from that of crystalline semiconductors.

The fourth semiconductor (25) of the present invention uses a non-single-crystal semiconductor containing amorphous silicon, uses hydrogen to neutralize the dangling bonds in the semiconductor, and dehydrates its surface without exposing it to the atmosphere. Making insulators. Furthermore, the photoresist is not brought into contact with the fourth semiconductor during the process, so that there is no deterioration of the characteristics. Furthermore, this semiconductor and P
In addition, since N has sufficient diode characteristics with Sl and S3, it has another feature that there are no manufacturing difficulties.

Thus, in the block (10'), the source or drain is 51 (13), the channel forming region (9') is S4 (35), the drain or source is 53
(15) Laminated layers forming a pair formed by (15'), with a gate insulator (34) provided on the side surface of the channel forming region (9') and gate electrodes (40>, <41') provided on the outer surface thereof. We were able to create C/IGF (51) and (52) of the type.

Furthermore, in FIGS. 2(C) and 3(A), block (10) has a source or drain connected to 51 (23).

(23'), 54 with channel forming region (9) (
35), drain or source S3 (25>, <2
A gate electrode (42) is formed on the outside of the gate insulator (34) on the side surface of the channel forming region (9).
), (43) to create a stacked c/IGF (53),
(54) was prepared. At this time, the first conductor (22-input second conductor (27)) shares two IGFs, and the C/I
A switch configuration was adopted in which GFs were connected in parallel. For this purpose, a gate input (62) is provided.

(63), signal input (66) or (67), and signal output (67>, <66).

Furthermore, in the IGF of the present invention, the electron mobility is 5 to 30 times that of holes, so in VLSI, this C
It is preferable to use /IGF in a part and to operate the other part as an N-channel type.

For example, NI
GF, the peripheral part is a decoder, and the driver is C/I
A typical application of the GF is to improve its operating characteristics and reduce its power consumption.

In this invention, the channel length is determined by the thickness of S2 (14), which is generally 0.1 to 3μ, here 1.0μ.
And so. Due to such a short channel, although the mobility of the non-single crystal semiconductor (25) is 115 to 1/100 times lower than that of a single crystal, the dual transistors were made to have a cutoff frequency characteristic of 10 MHz or more.

Kaku Shite, C/IGF 4 Nharta Toshi TV,, = 1
0VV = 10V, operating frequency 18.3MHz.

In addition, reverse leakage is caused by Sl or S as shown in Figure 1.
3 to 5ixC1-) < (0 < x < 1 For example, X
=0.2), S2 is further reduced to 5iIN+
-C (0<X<4) or 5iXC1-x (0<x<
By making it into an insulator as 1), this Sl, S3
impurities flowing into 52 are reduced, and this N
The leakage of =1 junction or P-1 junction was less than 10 nA/- even when IOV was applied in the opposite direction. This is 2 to 3 orders of magnitude lower than the reverse leakage of single crystals, which is preferable because physical properties specific to non-single crystal semiconductors are actively utilized. Furthermore, in operation at high temperatures, the metal of the electrode easily mixes into the non-single crystal 31, S3 and causes defects, so the side close to this electrode is 5ixC1-x (Q<x<
1 For example! =0.2). As a result, even though the device was operated at 150° C. for 1,000 hours, no malfunction was found even after evaluating 1,000 devices. This is because if 51 or S3 were formed with only amorphous silicon in close contact with this electrode, it would not be able to withstand 150°C for 10 hours.
This resulted in an extremely high level of reliability improvement.

In the above description, the fourth semiconductor was used as the channel formation region. However, it is also possible to use non-monocrystalline silicon to which hydrogen is added as the second semiconductor, and use this side surface as the channel formation region.

That is, gate insulators were prepared on the side surfaces of the first, second and third semiconductors in the same manner as in FIG.
One constitutes an IF junction and the other constitutes an NIN junction (actually PNI junction).
NP) to create C/IGF.

This structure has the advantage that the number of steps for stacking the fourth semiconductor is reduced. However, since the surface of the second semiconductor comes into contact with the atmosphere due to the etching of the fifth mask, there are many recombination centers at the interface, resulting in a frequency characteristic of 3 to 4M.
l1z has also gone down.

As explained above, since the present invention is a stacked IGF,
It has become possible to create a plurality of C/IGFs on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past. As an application, it has become possible to develop it into image sensors and liquid crystal displays.

The non-single crystal semiconductor in the present invention is silicon, germanium, or silicon carbide (SixC1-)<0<x<
1).

Silicon carbide or silicon nitride was used as the insulator.

[Brief explanation of the drawing]

FIG. 1 shows a conventional complementary insulated gay I-type semiconductor device. FIG. 2 is a longitudinal cross-sectional view showing the process of manufacturing a complementary stacked insulated gate type semiconductor device of the present invention. FIG. 3 shows a plan view and an equivalent circuit of a stacked insulated gate type semiconductor having the structure of the present invention. Patent applicant: Iari Yama - Masu Hei Shiruro 1 mouth

Claims (1)

[Claims] 1. a first semiconductor on a first electrode of a conductor on a substrate;
a semiconductor or an insulator, a third semiconductor and a second conductor.
a stacked body in which electrodes are stacked in substantially the same shape, the first and third semiconductors constitute a source and a drain, and a fourth semiconductor adjacent to a side of the stacked body forms a channel. A gate insulating film on the fourth semiconductor and two gate electrodes adjacent to the gate insulating film are disposed on two side surfaces of the stacked body, and a first and second An insulated gate type semiconductor device comprising an insulated gate type semiconductor device, wherein one of the first and second insulated gate type semiconductor devices has a P channel type and the other has an N channel type. 2, the first semiconductor on the first electrode of the conductor on the substrate, the second
a laminate in which a semiconductor, a third semiconductor, and a second electrode of a conductor are laminated in approximately the same shape,
A semiconductor is used to form a source and a drain, a channel formation region is formed and provided on a side surface of the second semiconductor, and a gate insulating film on the second semiconductor and a channel forming region are formed adjacent to the gate insulating film on the second semiconductor. First and second insulated gate type semiconductor devices are provided by disposing two gate electrodes on two side surfaces of the stacked body, and one of the first and second insulated gate type semiconductor devices is of a P-channel type. 1. An insulated gate type semiconductor device characterized in that the other has an N-channel type. 3. In claim 1 or 2, the first
and a second insulated gate field effect semiconductor device, wherein at least one of the first electrode and the second electrode is connected by a common conductor. 4. In claim 1 or 2, the first and third semiconductors in one insulated gate field effect semiconductor device are provided with a P-type semiconductor and an N-type semiconductor in close contact with each other. An insulated gate semiconductor device characterized by: 5. In the first or second claim ≠, the second claim
The semiconductor or insulator is Si, N4-e (0≦X<4)
) or 5ixCI-x (0≦x<1) as a main component.