JPS6076169A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To operate the titled semiconductor device at higher frequency by forming a gate insulating film on a fourth semiconductor and a gate electrode while being adjoined onto the gate insulating film in a shape that they are not extended to the upper section of a third semiconductor. CONSTITUTION:A first conductive film 2 is formed on an insulating substrate as a lower side electrode and a lead, and etched selectively (1). A P or N type conduction type first nonsingular semiconductor 3 (S1), a second semiconductor or insulator 4 (S2) and a third semiconductor 5 (S3) having the same conduction type as the first semiconductor are laminated on the upper surface of the conductive film 2, and a laminate (S) is shaped. An intrinsic or P or N type nonsingular semiconductor constituting a channel forming region while coating these laminates S1, 13, S2, 14, S3, 15 a conductor 23, an insulator 24 is laminated as a fourth semiconductor. A nonsingle crystal silicon semiconductor in amorphous or semi-amorphous or polycrystalline structure is used as the fourth semiconductor. An silicon nitride film 16 is prepared on the upper surface of the fourth semiconductor by a vapor phase reaction through a mercury excitation method by silane and ammonia through an optical CVD method without bringing the surface of the fourth semiconductor into contact with atmospheric air by the same reaction furnace.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical channel type stacked type insulated gate type semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.

The present invention provides at least three gate electrodes for this IGF.
The gate electrode is provided on a non-single-crystal semiconductor constituting a channel forming region provided around the sides of the stacked structure in which the gate electrode is stacked, and the upper end of the gate electrode is provided without extending above the stacked semiconductor. The purpose is to operate at high frequencies.

This invention further provides a non-single-crystal semiconductor that forms a channel around two sides of a three-layer stack, and uses this semiconductor to fabricate two IGFs, thereby creating circuit elements such as impark. The purpose is to provide a highly integrated system.

The present invention relates to a composite semiconductor device having a capacitor connected to the source or drain of a stacked IGI' on a substrate.

The present invention is characterized in that such a composite semiconductor device is provided on a substrate in a 7-trinks structure, and a liquid crystal display type display device is provided.

When providing a flat solid state display device, a liquid crystal display device is known in which a pair of electrodes are provided on parallel light-transmitting substrates, such as glass or plastic plates, and liquid crystal is injected between the electrodes. However, in this case, the number of picture elements in this display section is 20 to 20.
The limit is up to 0, and if it is larger than that, the number of terminals taken out from the display section would be equal to the number of picture elements, so it could not be put to practical use at all.

For this reason, this display section is made up of multiple picture elements, which are arranged in a matrix, and any given picture element is controlled by a logic circuit of a decoder and driver installed around it to turn it on or off. , it was necessary to manufacture the IGF, inverter, resistor, etc. corresponding to the picture element using the same process and the same structure. A control signal is then given to this IGF to turn on or off the corresponding picture element.

This liquid crystal display or electrochromic display element can be represented by a capacitor (hereinafter referred to as C) as any other circuit. For this purpose, IGF and C are arranged in a 2×2 matrix configuration (40) in FIG. 1 (A>
Shown below.

In Figure <A), one address of Matri Nox (40) constitutes one picture element by one IGF (10) and one C (31). Use this as a batter (51
), <52) are connected to the focus line, and on the other hand, gates are connected to provide columns (41), (42> (word)).

Then, for example, set (51>, <41> to "1",
(52) and (42) are 10'', then IGF (10
) is turned on, and other IGI's such as IGF (10'>
is off. Then, by selecting only the address (2, 1) and turning it on, it is possible to electrically turn on the display section indicating the number of nights, such as C':31).

The present invention is characterized in that the matrix-structured IGF is made symmetrical, thereby reducing the area required for IGF wiring other than the display area. Further, by forming the vertical channel type, the semiconductor constituting the channel forming region, which is the fourth semiconductor, is a non-single crystal semiconductor of silicon or germanium whose main component is silicon doped with hydrogen or fluorine.

Furthermore, since it has the disadvantage of low carrier mobility, the second semiconductor or insulator film JV is set to 1 μm or less to shorten the channel length. As a result, 10MII
It was possible to have a cutoff frequency higher than z.

As shown in FIGS. 1B, 1C, and 1D, the present invention allows a decoder and a driver to be configured on the same substrate, so that other insulated gate semiconductor devices (lO) and other inverters (60 inputs) can be used. The purpose is to provide a resistor (70) on the same substrate.

Thus, by combining the present invention based on the design specifications, it was possible to create a solid-state display device for flat-screen televisions that can replace cathode ray tubes.

FIG. 2 shows a vertical i-plane view of the stacked IGF of the present invention and its manufacturing process. This drawing is one IGP
An example of manufacturing is shown below, but the process is exactly the same when multiple units are manufactured on the same substrate.

In the drawings, a first conductive film (hereinafter referred to as El) was provided as a lower electrode or lead on an insulating substrate, such as a quartz glass or borosilicate glass substrate.

In this embodiment, a transparent conductive film containing tin oxide as a main component is formed to a thickness of 0.2 μm. Selective etching ■ was applied to this. Furthermore, a first non-single crystal semiconductor (2) (hereinafter simply referred to as 31) having a P or N type conductivity is formed on this upper surface.
1,000 to 3,000 people, the second semiconductor or insulator (
4) (hereinafter simply referred to as S2><0.3 to 3μ), and a third semiconductor having the same conductivity type as the first semiconductor (5) Hereinafter simply referred to as S3, Xo, 1 to 0.5μ) are laminated. A laminate (called "S") was provided. Due to this lamination, N
It had an IN, PIP structure (■ is an insulator or an intrinsic semiconductor).

In the drawing, ITO (indium oxide 71
．． ), MoSi, Mountain SIL 1 WSII IW
Here, a heat-resistant metal conductor (6) such as + TI + Mo was laminated with Ti 2 Si to a thickness of 0.2 μm by CVD method. Furthermore, in order to make the laminate even thicker, a silicon oxide film (7) is made in advance to a thickness of 0.3 to 1μ by LP CVD (low pressure vapor phase method), PCVD, or photoCVD.
may be formed. In case of PCVO method, town 0 and S
The reaction with +Il+ was carried out at 250°C and pricking was performed.

Assuming this N, 11 as NfN or chu1), N”NINN
It was a great idea to reduce the contact resistance between P or N and the electrode by using ", Il"r'IPI" (I is an insulator or an intrinsic semiconductor).

Furthermore, in FIG. 2(B), the insulating film (7) is removed by the °ζ selective etching method using the mask .
Using the Oc film (7) as a mask, the conductor (G) below it,
S3. S2 and Sl were removed, and the remaining laminates were formed into approximately the same shape. Plasma vapor phase etching was performed using the same mask, for example, using IIF gas or a mixed gas of CI+10 at an etch rate of 500 people/min at 0.1 to 0.5 torr for 30 hours.

After this, these laminates Sl (13), S2 (14)
, S3 (15).

An intrinsic, II or N type non-single crystal semiconductor was laminated as a fourth semiconductor, covering the conductor (23) and the insulator (24) to form a channel and T-channel forming region. This fourth semiconductor is deposited on the substrate using a silane glow discharge method (PCVD method).
For example, PC
250°C, 0-1 torr + 30 in VD method
11 + 13, 5 (+tlllz), and is amorphous.

Alternatively, a non-single crystal silicon semiconductor having a semi-amorphous or polycrystalline structure is used. In the present invention, an amorphous or semi-amorphous semiconductor (hereinafter SA
(referred to as S).

Furthermore, silicon nitride was added to the top surface in the same reactor without exposing the fourth semiconductor surface to the atmosphere! FIIQ (1G) was produced by a gas phase reaction of silane (disilane is also acceptable) and ammonia using a mercury excitation method using a photo-CVD method, and the thickness was 300 mm.
~2000 people.

This insulating film may be activated by electromagnetic energy at a frequency of 13.56M11z to 2.45GI1z and immersed in a nitrogen or ammonia atmosphere at 100 to 400°C to form silicon nitride in a solid-vapor phase reaction.

Alternatively, silicon nitride may be formed by IIcVD method.

Then, around the side of 52 (14), the channel forming region (9), <9') and the gay 1-insulator (16
) was formed as an insulator (16). The fourth semiconductor forms a diode junction with Sl and S3.

In FIG. 2 (13), an electrode hole is further made using the mask 3 on surface 3, and then a second conductive film (FIG. 17) is formed covering the silicon nitride film (16) on this rfl If body.
．． It was formed to a thickness of 3 to 1 μm.

This conductive film (17) is a transparent conductive film such as ITO (indium tin oxide), Tl5II + MoSi
A heat-resistant conductive film such as LIWS+LIW, Ti, Mo, etc. may be used. Here, a silicon semiconductor doped with a large amount of P- or N-type impurities was fabricated using the IIcVD method. That is, 0
．． A microcrystalline (grain size: 50 to 300 yen) non-single crystal semiconductor having a thickness of 3 μm and having 1% phosphorus added thereto was fabricated by PCVD.

After that, a resist (18) was formed on this upper surface.

Furthermore, as shown in FIG. 2(C), a fourth photolithography technique was used to perform heterogeneous etching in the vertical direction. For example, (, l'LcIL, CI'F +O
A reactive gas such as L+liver was turned into plasma, and this plasma was applied vertically from above the substrate as shown by the arrow (28). Then, the conductor (17) has a thickness of 0.3μ on the plane.
), this coating is removed, but on the side surfaces it has a vertical dimension of 2 to 3 μ, the sum of the thickness of the laminate and the thickness of the coating 11Q. Therefore, if anisotropic etching is performed in the vertical direction as shown in the drawing, the broken line (38), <38'
), these conductors could be left in areas other than the mask (18).

As a result, it was possible to selectively provide the DET electrodes around the sides of the laminate. Furthermore, this gate electrode does not exist above the third semiconductor, and as a result, the parasitic capacitance between the third semiconductor and the gate electrode can be made substantially equal to zero.

(Then, Figure 2 (C) was set as fj7.

The plan view of FIG. 2(C) is shown as FIG. 2(D). The numbers correspond to each other.

It is clear from Figure 2 (C>, <D) that <, IGF
(10) has two channels (9) and (9'),
It has a source or drain (13), a drain or source (15), and a gate (20) (<20'). The electrode (19) of G3 extends to the lead (21) and
The lead of l is set C according to (22). Therefore, in the drawing, two lG11 can be provided as a pair. This is because the 52 semiconductors or insulators between the two IGF channels are insulating, and if 52 has a diameter of 10μ, it is several tens of M
This is because it has a resistance of Ω and has a substantially independent structure, and this structure allows it to have a structure completely different from that of a crystalline semiconductor.

The fourth semiconductor of the present invention uses a non-single crystal semiconductor containing amorphous silicon, uses hydrogen to neutralize dangling bonds in the semiconductor, and has a substrate, a semiconductor, and an electrode lead made of different abrasive materials. In order to reduce stress due to thermal expansion, all treatments were preferably carried out at 600°C or lower, preferably 300°C or lower.

In addition, the gate electrode (20), <20') is connected to Sl (13)
, 52 (14).

A semiconductor similar to G3 (15) is electrically provided as a floating L1, and a second
It is also possible to use a non-volatile memory with the gate as a control gate.

Thus, G4 (25) with source or drain 51 (13), channel forming regions (9), (9')
, a multilayer IGF (10) in which the drain or source is formed by G3 (15), and a gate insulator (16 insulators) is provided on the side surface of the channel formation region, and a gate electrode (20) <20' is provided on the outer surface of the gate insulator (16). I was able to make it.

In this invention, the channel length is determined by the thickness of G2 (14), which is generally 0.1 to 3μ, here 0.5μ. Since the mobility of a non-single crystal semiconductor is different from that of a single crystal, and is only 115 to 1/100 L, the channel length is shortened to promote the frequency '14+' characteristic as an IGF.

Furthermore, in the IGF of the present invention, since the electron mobility is 5 to 100 times higher than that of a ball, it was preferable to use an N-channel type.

A small amount of boron impurity was added to G4 (16) during film formation (
It was effective to control the threshold ball 1~voltage by adding 0,1~IOIIPM) as an intrinsic or II or N semiconductor.

Thus, as drain (15)', source (12), gay I. (20) or (20') -5v, v6.
-5v and an operating frequency of 15.5M1lz could be obtained.

Figure 3 shows the first example using the IGF of the present invention shown in Figure 2↓.
This is a vertical view of part of the display panel in Figure (A).

Figure 3 (A) is Figure 1 + 7) IGF (1 (1), <1
0'), and the upper electrode of the capacitor (><32, which is provided on the lower side in FIG. 3). In the drawings, (B) and (C) are vertical cross-sectional views taken along lines Δ-A' and B-13' of the plan view of (A).

In the drawings, Sl (13); G2 (14), G3
For the laminate of (15), the lower electrode is 2 (12),
(12') is provided. The upper electrode (19)
A lead (51) is provided in the direction. Gate electric +i (20).

(20') is two IGF (10), <10') region (region (10), <1
0')), the leads (41) and (42) are arranged in the Y direction. The lower electrode (12), (12') further extends to one electrode (32), <32' of the capacitor.
)It has become. As a result, it was possible to have a matrix structure in the X and Y directions, and an ITr/pixel structure. Further (71).

The region (71') was filled with a display material, such as a liquid crystal, and the region (71) was controlled by turning on and off the IGF (10), <10'.

In FIG. 3, the metal conductor (23) and insulator (24) have been removed from 53 (15) as shown in FIG.

This is because if a conductor is provided, this conductor becomes a lead in the Y direction, and S3 cannot be made into a 7twax in the X direction. Therefore, in Fig. 2, the conductor (23) on S3 (15)
The insulator (24) may be provided according to its design specifications.

Also, as is clear from Figure 3, S3 and S4 (2
5) is essentially an intrinsic non-crystalline semiconductor, so even if S3 and S4 remain between the 1612 arranged in the Y direction, there is no need for an isolation/f-joon. For this reason, the IGI' in the Y direction is spaced apart from each other by at least 50μ
Directional wiring (51), <52) was set up. In addition, in the drawing, the leads (51) other than the display part (32) are <4
1>, it is effective to cover (4'2) with an insulating film (26).

Furthermore, as is clear from FIG.
In addition to using GF, since IGF has a short channel length, the area required on the substrate can be reduced. and) has the other advantage that the precision of A-lithography does not limit the upper limit of the operating frequency.

FIG. 3 shows an outline of + and + operations corresponding to FIG. 1(A). In the N-channel ICF, all these IGFs are normally off, so the leads in the X direction (41
), <42), when the Y-direction leads (51) and (52) apply voltage to both, rlJ can be set, and when only force is applied or no force is applied, it can be set to "0". Ta.

Furthermore, in order to operate these picture elements at high frequencies, J
The frequency characteristics of GI' are extremely important, and the IGF of the present invention was able to have a cutoff frequency of 10 MIIZ or more (14.5 MIIz) (N-channel ICF) at V-5V and V-5V. V+＾=
It became possible to set the voltage to 0.2 to 2 V by controlling the concentration of impurities added to S4 (25).

The IGF of the present invention will be described below with respect to the resistor (D) and inverter (C) necessary for the peripheral decoder and driver.

FIG. 4 shows a longitudinal cross-sectional view of the inverter (60) of FIG. 1.

In FIGS. 4(A) and 4(B), 1crt corresponds to the number in FIG. 2. The driver (61) used the left IGF, and the load used the right IGF.

In drawing (A), the load gate electrode (20) and ■ (65
) and an enhancement type that continues with the drawing (B).
shows a depression type IGF in which the output (62) and the gate electrode (20) are connected.

Furthermore, the output of this impark (60) is ((i2),
, then the two IGFs on this board (61), <
64) of the same semiconductor block (
13).

(14), < 15).

The inverter shown in Fig. 4(A) has two FIs connected to the upper electrode.
It was determined to be independent as an ET (19), <19'). Thus one IGF (640 load) is attached to the electrode (19).

Drain (15), channel (9), source (13 people?
i4m (12), that is, output (62) is ia JGF (
electrode (2) of the driver), drain (13-channel channel (
9'), a source (15'), and an electrode (66). As a result, two IGFs can be combined into one s
- It was possible to integrate it with the block of s3 and make it impark.

Moreover, FIG. 4(B) shows the lower electrode divided into two parts. i.e. v with one IGF load (64).

(65), lower IR electrode (12), drain (I3),
Channel (9), source (5), electrode (62), drain (15) in other IGF (driver X61), channel (9'), source (13), electrode (12') ), ν, ((iG), input (63)
The output (62') was drawn out from S3 to the gate electrode (20').

The resistor (70) in FIG. 1 is determined by the resistivity of the bulk component of 54 (25) in FIG. 2 CD), <E) and FIG.

That is, it is determined by the resistivity of the bulk component of 34, regardless of the voltage applied to the gate electrode. That is, 51.82. without the gate electrode. It is sufficient to stack S3.

Further, this resistance value may be determined according to the design specifications based on the resistivity of S2, its JI7, and the area occupied on the board.

As described above, the present invention is a vertical channel, and the gate electrode is not provided above 53, so that either Sl or S3, which reduces the parasitic capacitance between the gate electrode of the IGF and 33, acts as a drain. , since its exterior is insulated, it can be said to be the most ideal IGF. Further, under the channel of S4, two IGFs contributing to improvement of frequency characteristics can be formed at the same time as a pair due to the insulating properties of S2. It is sufficient to manufacture masks 5 times, and the channel length is 0.2~l tt.
In addition to being able to make it extremely short, it was also possible to store it.

The display of FIG. 3 in accordance with the present invention has one electrode (3
2) determines the size of one picture element. In Caliculeik and the like, it has a diameter of 0.1 to 5 mm or a rectangular shape. However, in the scanning type system as shown in Fig. 1,
1000X as a matrix-like picture element of 500μ0
It was set to 1000. A liquid crystal display section (31) was provided on this substrate as another electrode of the capacitor. That is, the other electrode is a glass plate having a grounded transparent electrode such as ITO, and this glass plate and the substrate of FIG.
A gap of 1 mm was provided, and nematic liquid crystal, for example, was injected into the gap.

This display may also be displayed in color.

Furthermore, for example, these picture elements may be stacked in triplicate. Then, the three elements of red, green, and yellow may be arranged alternately.

Therefore, the breakdown voltage is 20 to 30 V + V+h"i -4 to
It was possible to control the voltage within the range of 4v, for example, 1±0.2v. Furthermore, since the frequency characteristics are microchannels with a channel length of 0.1 to 1μ, the frequency characteristics are 50 times that of conventional horizontal channel type insulated diode type semiconductor devices using non-single crystal semiconductors.
I was able to obtain 0M1lz or more. In addition, if S2 is insulating, the withstand voltage is 4 to 50V, and the cutoff frequency is 50M1L.
It was possible to have Z or higher.

In addition, reverse leakage is caused by SL or S as shown in Figure 1.
3 to 5ixC1-y (Q < x < l For example x
= 0.2), and by making S2 an insulator, the impurities of Sl and S3 will be less likely to flow into 32, and the leakage of this N-1 junction or P-1 junction will be in the opposite direction. Even if lOν is added, lpn^/c+i
It was less than l. This is 2 to 3 orders of magnitude lower than the reverse leakage of single crystals, which is preferable because physical properties specific to non-single crystal semiconductors are actively utilized.

Furthermore, in operation at high temperatures, the metal of the electrode easily mixes into the non-single crystal 51, S3 and causes defects, so the side close to this electrode is 5ixC+-x (0< x < 1
For example, X = 0.2). As a result, 1 at 150℃
Although the operating time exceeded 1,000 hours, no malfunction was found even when 1,000 devices were evaluated. This is because if Sl or S3 were formed with only amorphous silicon in close contact with this electrode, it would not be able to withstand 150°C for 10 hours.
This resulted in an extremely high level of reliability improvement.

Furthermore, because of such a stacked IGF, it has become possible to fabricate a plurality of IGFs, resistors, and capacitors on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past. This made it possible to develop it into liquid crystal displays.

The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide (SixC1-x0<x<1
>, silicon carbide or silicon nitride was used as the insulator. However, as a semiconductor, nr such as I+iP, BP, GaAs, etc.
-v compound semiconductors may also be used.

[Brief explanation of drawings]

FIG. 1 shows a circuit having a matrix structure in which picture elements include an insulated gate type semiconductor device, an inverter, a resistor, a capacitor, or an insulated gate type semiconductor device and a capacitor according to the present invention. FIG. 2 is a longitudinal cross-sectional view showing the process of manufacturing a stacked insulated gate type semiconductor device of the present invention. FIG. 3 is a side view of a composite semiconductor Ii (1 (Ii) showing a flat display in which a stacked insulated gate semiconductor device of the present invention, a capacitor, and a display unit are integrated. Shows the inverter structure of an insulated gate semiconductor device. Patent applicant Semiconductor Energy Research Institute Co., Ltd. (I, 2nd C2, 2) '7..L: role, 〆ga- □□□j-=; 蛎= subzo 17

Claims (1)

[Scope of Claims] 1. A laminate comprising a first semiconductor on a substrate or an electrode on the substrate, a second semiconductor or an insulator, and a third semiconductor stacked thereon in approximately the same shape; The first and third semiconductors constitute a source and drain, a fourth semiconductor is provided adjacent to a side of the stacked body to constitute a channel formation region, and a gate insulator is provided on the fourth semiconductor. 1. An insulated gate type semiconductor device characterized in that a gate insulating film and a gate insulating film are provided adjacent to each other without extending above the third semiconductor. 2. A laminate in which a first semiconductor, a second semiconductor or an insulator, and a third semiconductor are laminated in approximately the same shape on the substrate or a lower electrode on the substrate, and the first and third semiconductors A fourth semiconductor is provided adjacent to the sides of the multilayer structure to form two channel forming regions, and a gate insulating film is formed on two side surfaces of the fourth semiconductor. An insulated gate type semiconductor device characterized in that: and respective gate electrodes are provided adjacent to the gate insulating crotch. 3. In claim 1 or 2, the first
or in close proximity to the third semiconductor conductive electrode, 5ixC
1-)<(0<x≦1) An insulated gate type semiconductor device characterized in that the first or third semiconductor of P or N type is provided. 4. In claim 2, each gay l
- An insulated diode type semiconductor device, characterized in that at least one of the electrical losses is provided without extending above the third semiconductor. 5. In claim 1 or 2, the second
An insulated gate type semiconductor device characterized in that the semiconductor or insulator is mainly composed of Si7N,-,c (0≦X4)) or 5ixC+-x (0≦x<1).