JPS60124963A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement of the frequency characteristic and the reduction of the off-current by a method wherein a single crystal or polycrystalline structural insulated gate type semiconductor device and an amorphous or semi-amorphous structural one are formed on the same substrate. CONSTITUTION:A conductive film 2, a non P type conductivity non single crystal semiconductor 3, a semiconductor or insulator 4, and a P type semiconductor 5 are laminated on the insulation substrate 1. Successively, a heat-resisting metallic conductor 6 and an Si oxide film 7 are formed thereon. Next, the film 7 and the conductor 6 are selectively etched by using a mask 2. Then, a non single crystal semiconductor is laminated on the laminated body thereof, and channel-forming regions 9 and 9' and a gate insulator 26 are formed on its top. In such a manner, two insulated gate type semiconductor devices having the regions 9 and 9', sources or drains 13 and 15, and gates 20 and 20' are formed as a pair. One of these two semiconductor devices is formed as a single crystal or polycrystalline structure excellent in the frequency characteristic, and the other as an amorphous or semi-amorphous structure with a small amount of off-current.

Description

Detailed Description of the Invention The present invention relates to an insulated gate type semiconductor device (hereinafter referred to as IG) of a vertical channel type stacked band using a semiconductor on a substrate having an insulating surface.
(referred to as F).

The present invention uses a first IGF as a semiconductor material constituting a channel forming region provided around the side of a stacked structure in which gate electrodes are stacked in at least three layers.
In the second IGF, this semiconductor is made to have a single-crystalline or polycrystalline structure that has a somewhat large off-state current but excellent frequency characteristics, and furthermore, in the second IGF, this semiconductor is made to have an amorphous or semi-amorphous structure that has a small off-state current. The purpose is to

The present invention provides an interface for controlling picture elements in a solid-state display device.
The semiconductor constituting the Nayanel formation region of GF has an amorphous or semi-amorphous structure (Σl) with low off-current.
A semiconductor with a crystallinity of 80% or less and some single crystals, but whose average grain size is 200 Å or less when examined by Raman spectroscopy. Furthermore, these semiconductors have an oxygen and nitrogen concentration of 5 x 10110l9 or less (preferably 5 x 10110l8 or less), and on the other hand, they constitute the channel forming region of IGF such as the inverter that constitutes the decoder and driver that are peripheral circuits. The purpose of this invention is to improve the frequency characteristics by making the semiconductor into a single crystal or a polycrystal with an average crystal grain size of 500 Å or more.

This invention further provides a non-single-crystal semiconductor that forms a channel around two sides of a three-layer stack, and uses this semiconductor to fabricate two IGFs, thereby creating circuit elements such as inverters. The purpose is to provide a highly integrated system.

The present invention relates to a solid state display composite semiconductor device represented by an equivalent circuit of a capacitor connected to the source or drain of a stacked IGF on a substrate.

The present invention is characterized in that such a composite semiconductor device is provided on a substrate in a 71-linox structure to provide a solid-state display device.

When a flat solid-state display device is provided, the display section is made up of a plurality of picture elements, arranged in a matrix, and any picture element is controlled by a decoder and a logic circuit installed around it. To turn on or off, press IG+? corresponding to that picture element. In addition, it was necessary to manufacture inverters, resistors, etc. using the same process and structure. A control signal is then sent to this IGF to turn on or off the corresponding picture element.

This liquid crystal display or electrochromic display element can be represented by a capacitor (hereinafter referred to as C) as its equivalent circuit. For this reason, the IGF and C are configured in a 2×2 7-twax configuration (40) as shown in FIG. 1(A).
Shown below.

In FIG. 1(A), one address of the matrix (40) constitutes one picture element by one IGF (10) and one c (31). This is connected to the decoder and driver circuit (44) as Pino 1-Cotton row (51), <52), while Kay 1-Column (41), <
42) (word), and a decoder and a driver circuit (hereinafter referred to as the D11 circuit><43) are connected.

Then, for example, (51), < 41 ) is set to 111,
(52) and (42) are 10'', then IGF (10
) is turned on, and other IGFs such as IGI'(10')
is off. Then, by selecting and turning on only the address (2,1), it is possible to selectively turn on the display section electrically equivalently shown as C(31).

The present invention provides for this heptrinox-configured IGP,
71-The IG++ channel forming region (hereinafter referred to as CFI?) in the linox part is made of silicon having an amorphous or semi-amorphous structure (hereinafter simply referred to as an amorphous structure), and its off-state current is reduced to 10-9 to IQ-11. . In addition, CF is added to the IGF of the DR circuit.
R uses a laser annealing process to transform the semiconductor into a single-crystal or polycrystalline structure to improve the frequency characteristics, and the 5-cut cant-off frequency is increased to 30 to 80 MIIz. The fourth semiconductor constituting this CFR is a silicon/kermanium semiconductor whose main component is silicon doped with hydrogen or fluorine. Further, the present invention generally relates to carrier mobility (0,01 to I an!
On the one hand, a non-single-crystal semiconductor, which has the disadvantage of a small V/sec), was made into an amorphous structure, and its characteristic of low off-state current was actively utilized.

Furthermore, since the 017 circuit must pass a large amount of current to the matrix at high speed, its vertical channel type IG
Laser annealing the fourth semiconductor of F to make it a single crystal,
The carrier mobility of the electron is 100 to 500-ν/se
A solid-state display device is constructed by using each IGF as c.

As shown in FIG.
44), another insulated gate type semiconductor device (10) and another depression type inverter (6
.

In this way, by combining the present invention based on its design specifications, it was possible to create a solid-state display device for flat-screen televisions that can replace cathode ray tubes.

FIG. 2 shows the stacked IGF of the present invention shown in FIG. 1(B).
FIG. Although this drawing shows a manufacturing example in which one IGF is manufactured, it is exactly the same when multiple IGFs are manufactured on the same substrate.

In the drawings, a first conductive film (2) (hereinafter referred to as E1) was provided as a lower electrode or lead on an insulating substrate, such as a quartz glass or borosilicate glass substrate.

In this embodiment, a transparent conductive film containing tin oxide as a main component is formed to a thickness of 0.5 μm. Selective etching ■ was applied to this. Further, on this upper surface, a first non-single crystal semiconductor (2) having N or P type conductivity (hereinafter simply referred to as Sl) is formed.
(Electrical conductivity 10-3 to 102 (Ωcm)'') to 10
00-3000 people, without addition of second impurity or B
Semiconductor with 5 PPM or less added or SixC1-
an insulator (4) of )(0,
A laminate (referred to as "S") was prepared by stacking 1 to 0.5 .mu.m. This lamination provided a NIN, pH' structure (■ indicates an insulator or an intrinsic semiconductor).

In the drawing, ITO (M-indium tin), MoSi, Ti5iL+ WSiL+ W+ are shown on the top surface.
Heat-resistant metal conductor such as Ti + Mo, Cr ((5)
Here, Cr was deposited to a thickness of 0.2 μm by electron beam evaporation. Furthermore, in order to further reduce the parasitic capacitance so that PJ<L, the laminate is preliminarily heated to 0.3 to
・Formation of silicon oxide glands (7) with a thickness of 1μ is f1
It is effective. In the case of the pcvu method, N, O and S + 114
25 (1°C).

This N, 11 is N”N or fp as N” NINN
It was effective to lower the contact resistance between P or N and the electrode by using +, P+ gate pHf (I is an insulator or an intrinsic semiconductor). In addition, in Figure 2 (B), selective etching was performed using a mask ■. 1 ton of insulation by law! ! (7) is removed, and using S'0JIN (7) as a mask, the conductor (6) below it is removed.
), S3. S2 and Sl were removed, and the remaining laminates were anisotropically etched into approximately the same shape. Plasma gas phase etch using the same mask, for example, using liver gas or a mixed gas of C1↓4oL, 0.1 to 0.5t
The orr was set to 30 and the niche degree was set to 1500 people/minute.

After this, these laminates Sl (13), S2 (14)
, S3 (15), conductor (23), and insulator (24) to form a channel forming region.
A type of non-single crystal semiconductor was laminated as a fourth semiconductor.

This fourth semiconductor was prepared using a silane glow discharge method (
PCVD method, photoCVD method, LT CVD method (IIOMO
(Also called CVD method)
, IOW, 13.56 MIIz. It uses crystalline silicon semiconductor. The present invention focuses on amorphous semiconductors (hereinafter referred to as SAS).

Furthermore, a silicon nitride element (16) was applied to the top surface in the same reactor without exposing the fourth semiconductor surface to the atmosphere by photo-CVD.
The thickness is 300 to 200 mm.
There were 0 people.

This insulating film is activated by electromagnetic energy or light energy with a frequency of 13.56 MH2 to 2.45 GH2.
Silicon carbide may be formed by chemical vapor phase reaction of methylsilane such as MS (11□Si (C1l,)□).

Alternatively, silicon nitride may be formed by an I'CVD method.

Then, around the side of 52 (14), an insulator (1G) was formed as a channel forming region (9) and a gate insulator (26) on it.The fourth semiconductor was made of Sl,
S3 constitutes a diode junction.

Furthermore, in order to single-crystallize this semiconductor for CFR, laser light was irradiated. Here, YAG laser (wavelength 1.0
6μ repetition frequency 3KIIz operation speed 30cm/
sec average output 2W light diameter 250μφ). Then, only the portion of the fourth semiconductor that is irradiated with the laser beam is annealed and made into a single crystal or polycrystal. At this time, since the upper surface of this fourth semiconductor is covered with a gay 1-insulating film, it does not come into contact with the atmosphere, and since the annealing is performed below the top of the stack, it has good crystallinity and is substantially simple. It was possible to crystallize. Furthermore, by moving the substrate in the laser of this YAG radar, it is possible to selectively make the area irradiated with light only CFR. Therefore, it has the great advantage that only the particularly necessary fourth semiconductor of the IGF of the OR circuit on the back of one substrate can be selectively made into single crystal or polycrystal.

In Fig. 2 CB), the first IGF is not laser annealed, and the second IGF is laser annealed, and as the next step, an electrode hole is formed using the third mask. The silicon nitride film (1
6), a second conductive film (17) was formed to a thickness of 0.3 to 1 μm.

This conductive film (17) is made of ITO' (indium oxide).
Transparent conductive film such as tin), Ti5il, MoSi
, ,WSi, .

A heat-resistant conductive film such as W + Ti + Mo may also be used. Here, a microcrystalline silicon semiconductor doped with a large amount of P or N type impurities (electrical conductivity 1 to 100 (0 cm)) is used.
”) was made by the P'CVD method. That is, it was made with a thickness of 0.3μ, 1% phosphorus added, and microcrystalline (grain size 50-3
A non-single-crystal semiconductor of 0.00% was fabricated using the 11 CVD method.

After that, a resist (18) was formed on this upper surface.

Furthermore, as shown in FIG. 2 <C>, the fourth f, t
Anisotropic etching in the vertical direction was performed using I. lithography technology. That is, for example, CF yo CIL+ CF, +0
．． A reactive gas such as +11F was turned into plasma, and this plasma was applied perpendicularly to the negative side of the substrate as shown by the arrow (28). Then, this film is removed by etching the conductor (17) on the flat surface, which has a thickness of 0.3 mm, but on the side surfaces, the thickness of the conductor (17) is 2 to 3 μm, which is the sum of the thickness of 1IIJ1 and the thickness of the film. in the vertical direction. Therefore, by performing anisotropic etching in the vertical direction as shown in the drawing, these conductors could be left in areas other than the mask (18) as shown by the broken line (3B, <38').

As a result, it was possible to selectively provide the DET electrodes Lj only around the sides of the laminate. Furthermore, this gate electrode exists on three sides of the third semiconductor, and as a result, the parasitic interaction between the third semiconductor and the gate electrode can be substantially eliminated.

Thus, Figure 2(C) was obtained.

2(C)] is shown as FIG. 2(D).

The numbers correspond to each other.

As is clear from Figure 2 (C), <i)), IG
I'(10) is channel CFR(9), <9') and 2
Source or drain (13), drain or source (15), gate (20), <20'
). The electrode (19) of S3 extends to the lead (21) and the lead of Sl is provided by (22) 6[
In the drawings, two IGFs can be provided as a pair. This is several tens of micrometers if the 32 semiconductors or insulators between the channels of two IGFs have a diameter of 10μ or more.
This is because it has a resistance of Ω and can have a substantially independent structure, and this structure can be completely different from that of a crystalline semiconductor.

Thus, the source or drain is S1 (13), S4 (25>) with channel forming regions (9), (9')
, I Ruins or sources are formed by S3 (15), and a gate insulator (2
6), we were able to fabricate a stacked IGF (10) with gate electrodes (20>, <20') provided on its outer surface.

In this invention, the channel length, channel/l-, is S2
It is determined by the thickness of (14), 0.1 to 3μ, here 1
．． 0μ, and IO~100μ, where 3oit was used. Further, the mobility of the amorphous semiconductor of the fourth semiconductor was 0.01 to 1cIII/sec, but the mobility around the cutoff was 10 to 15M112. At the same time, the off-state current was 10'A, which was extremely low. Furthermore, the second
Figure (B) When the fourth semiconductor is made into a single crystal by laser annealing, the carrier mobility is 20 to 100.
cl+V/sec, which was improved by 30 to 100 times, and this semiconductor was also single crystal or partially polycrystalline, and its crystal structure was clearly different from an amorphous structure. Therefore, the IGF cutoff periphery is 40 to 80M.
It had 1lz-tl-. However, the off-state current is also 10-'
It was 100 times larger than A and when laser annealing was not performed.

A small amount of boron impurity was added to S4 (1G) during film formation (
It was effective to control the threshold voltage by adding (0.03 to 3r'PM) as an intrinsic or P semiconductor.

Figure 3 shows the first example using the IGF of the present invention shown in 2v1.
FIG. 2 is a longitudinal sectional view of a part of the front panel of FIG.

Figure 3 (A) is the IGF of Figure 1 (10), <10')
, the upper electrode (32), <32') of the capacitor (31), <31') is provided on the side G (in FIG. 3).

Vertical cross-sectional views taken along lines AA' and BB' in the plan view of FIG. 3(A) are shown in (B) and (c).

In the drawings, si (13), S2' (14), 5
In contrast to the laminate of No. 3 (15), S4 (25) uses an amorphous semiconductor, and in particular hydrogenated amorphous silicon is used here to provide an off-state current of 10-8 A or higher. Furthermore, two lower electrodes (12), <12') of the ICF are provided.

The upper electrode (19) is provided as F, (51) and -ζ in the X direction. Gate electrode (20), <20')
are the two IGF (10) and (10') regions (Fig. 3 (
Leads (41), <42) are arranged in the Y direction, except for the region (10), <10')) surrounded by the broken line in A). The lower electrode (12), (12') & further extends to become one electrode (32), <32') of the capacitor. In this way, it was possible to have a 71-lix configuration in the X and Y directions and an lTr/pixel structure.

The areas of (31) and (31') are filled with a display material, such as liquid crystal or chromink, and the area of (31) is filled with I
Control was performed by turning on and off GF (10), <10').

In Fig. 3, a metal conductor (23) is provided on s3 (15) for the area where the IGF is provided, and this conductor and S3 (15) without this conductor are covered and insulated. A body (24) is provided. That is, the single-crystal or polycrystalline IGF 34 in FIG. 2 and the IGF in FIG. 3 have the same structure. Furthermore, as is clear from Fig. 3, since S4 (25) is essentially an intrinsic amorphous semiconductor, even if S4 remains between +C++ arranged in the Y direction, if it is separated by 10 μ or more, "1" - (X
Directional wiring (51) and e (52) were provided. Also, in the drawings, a lead (51) other than the display part (32).

It is effective to cover (41) and <42) with insulating films (72> and (73)).

Furthermore, as is clear from FIG. 3, the area required for IG++ in this display is less than 1% of the total area. The display area is 91% and the lead area is 8%. This means that in addition to using a pair of IGFs, since the IGFs have short channel lengths, the area required for constructing the IGFs on the substrate can be reduced. Another advantage is that the accuracy of lithography does not limit the upper limit of the operating frequency.

An outline of the operation in FIG. 3 is shown corresponding to FIG. 1(A). In the N-channel IGF, since all these IGFs are normally off, the lead in the X direction (41),
(42), the Y direction lead (51), < 52) can have a "1" when voltage is applied to both sides, and a - can have a "0" when only one side is applied or no voltage is applied. Ta.

Furthermore, in order to operate these picture elements at high frequencies, IGF
The frequency characteristics of the present invention (7) I are extremely important.
The GF was able to have a cathode off frequency of 10M1lz or more (14.5MHz > (N channel IGF) at V, = 5VIV, = 5V.V, H =
It became possible to control the concentration of impurities added to 54 (25) to make it 0.2 to 2 V.

IGI' (
10) (B), I of the present invention for resistance inverter (C)
GP is described below.

FIG. 4 shows a longitudinal cross-sectional view of the inverter (60) shown in FIGS. 1(C) and 1(D).

The IGIi 54 in FIG. 4, particularly the CFRs (9) and (9'') of the driver IGF, are provided with a single crystal or polycrystalline semiconductor to improve frequency characteristics.

In Fig. 4 (A) and (B'), IGF is shown in Fig. 2 (
C), (f)) and their numbers are made to correspond. The driver IGF (61) connects the left IGF to the load IGF'
F used the IGF on the right. In Fig. 4(A), the gate electrode (2+1) of the load and V (65) are connected in an Enchenstan type 1 type (Fig. 1(C)), and in Fig. 4(B)
1(D) shows a depletion-type input circuit in which the output (66) and the gate electrode (20) are connected.

Furthermore, the output of this inverter (60) is (66), and the two IGFs (61) on this board are <64
) without separating the same semiconductor blocks (13
The feature is that it is provided in combination with (14), <15).

The impark in FIG. 4(A) is the upper electrode (23).

(23') as two independent FETs (19),
<19'). Thus one IGF (64>
(load) to contact (19 input electrode (23), drain (15), channel (9), source (13), electrode (12) i.e. output (66) and other IGF (driver) electrode (2), Drain (13), channel (9') provided by single crystal or polycrystalline semiconductor, source (
15'), an electrode (23'), and a contact I-(6B).

As a result, it was possible to integrate two IGFs with one block 31 to S3 to form an inverter.

Moreover, FIG. 4 1(B) shows the lower electrode divided into two. That is, with one IGF load (64), vDO (65
), lower electrode (12), drain (13), channel (
9), source (5), electrode (23) or output (66),
Drain in Haku's IGF (Driver 861) (15)
, channel (9'), source (13), electrode (12'), v, (
68), and human power ((i7) is connected to the gate electrode (20'
) to output (66') from 83, 1! Ta.

715, +tC anti is 21 & I (I)), (LE)
and 11 (determined by the resistivity of the bulk component of 54 (25), i.e., 34 regardless of the voltage applied to the gay 1 electrode)
determined by the low resistivity of the bulk components. That is, without providing the gate voltage 4, S1, S2 . It is sufficient to stack S3. Also, this resistance value is determined by the resistance A4 of S2, its thickness, and the substrate −
All you have to do is decide on the area occupied by 1 x 1 x 1 x i-mail.

Furthermore, when using an amorphous structure to control the llj: I)'j value, ;1; or by using a single crystal or polycrystalline structure by laser annealing, the amount L
) is my own J′□.

Thus, the present invention is a vertical channel, and the first IGIi on one substrate is CF l? The other second ICP has a single crystal or other crystal structure.

Especially in solid-state display devices, IG controls the picture elements of the display section.
Ii uses an amorphous semiconductor for CTI+, and Dl
A feature of the present invention is that by using a single crystal or a polycrystal for IGI' in the r section, the features of each IG'F are synergistically derived, resulting in a comprehensive semiconductor device.

In the display of FIG. 3 according to the present invention, one electrode (32) determines the size of one picture element.

In Caliculeik and the like, it has a diameter of 0.1 to 51φ or a rectangular shape. However, in the scanning type system as shown in FIG. 1, about tgooo x about 1000 is used as a 71-linox-like pixel of 10 to 5000 pD. A liquid crystal display section (31) was provided on this substrate as another electrode of the capacitor. That is, the other electrode is a glass plate having a transparent electrode such as ITO grounded, and this glass plate and FIG.
A gap of 0.01 to 1 mm is provided between the two substrates, and, for example, nematic liquid crystal is injected therein.

This display may also be displayed in color.

Furthermore, for example, these picture elements may be separated into three layers using filters. Then, the three elements of red, green, and blue may be arranged alternately.

Therefore, it was possible to control the voltage within the range of 20 to 30V and V%-4 to 4V, for example, 1±0.2V. Furthermore, since the frequency characteristic is a microchannel with a channel length of 0.1 to 1μ, it is possible to obtain a frequency of 10M1lz or more, which is 50 times higher than that of conventional lateral channel type insulated gate type semiconductor devices using non-single crystal semiconductors. Ta. Moreover, when S2 was insulating, it was able to have a monthly resistance of 24 to 50 V and a cutoff frequency of 50 MIIZ or more.

In addition, reverse leakage is caused by SL or S as shown in Figure 1.
3 to 5ixC1-) < (0 < x < 1 For example, X
= 0.2), and by making S2 an insulator, the impurities in 81 and S3 will be less likely to flow into 32, and the leakage at the N-I junction or P--1 junction will be reduced. Even when IOV was applied in the opposite direction, it was less than 10 nA/cJ. This is even more than the single crystal reverse leakage.
It was three orders of magnitude less, which is preferable because the physical properties of non-single crystal semiconductors including an amorphous structure were actively utilized.

Furthermore, in operation at high temperatures, the metal of the electrode tends to mix into the non-single crystal 31, S3 and cause defects, so the side close to this electrode is 2). As a result, 100 at 150℃
Although the device was operated for 0 hours, no malfunction was found even after evaluating 1000 devices. This is because when 31 or S3 is formed of only amorphous silicon closely to this electrode,
Considering that it can withstand temperatures of 150°C for less than 10 hours, this is a remarkable improvement in reliability.

Furthermore, because of such a stacked type IGF, it has become possible to fabricate a plurality of IGFs, resistors, and capacitors on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past. This made it possible to develop it into liquid crystal displays.

The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide (SixC1-x0<x<1
), silicon carbide or silicon nitride was used as the insulator.

[Brief explanation of drawings]

FIG. 1 shows an equivalent circuit of a matrix structure in which an insulated gate semiconductor device, an inverter, a capacitor, or an insulated gate semiconductor device and a capacitor according to the present invention are used as picture elements. FIG. 2 is a longitudinal cross-sectional view showing the process of manufacturing a stacked insulated gate type semiconductor device of the present invention. FIG. 3 is a longitudinal sectional view of a composite semiconductor showing a flat display in which the stacked insulated gate semiconductor device of the present invention, a capacitor, and a display section are integrated. FIG. 4 shows the inverter structure of the stacked insulated gate semiconductor device of the present invention. Patent applicant pIl'1l (C) Id(nokawa4i

Claims (1)

[Claims] 1. A laminate in which a second semiconductor or an insulator and a third semiconductor are laminated in approximately the same shape on a first semiconductor on a substrate having an insulating surface or an electrode on the substrate. the first and third semiconductors constitute a source and drain; a first insulated gate type semiconductor device comprising a gate insulating film on the fourth semiconductor and a diode electrode adjacent to the gate insulating film; a second insulated gate type semiconductor device having the same stacked structure as the insulated gate type semiconductor device on the substrate and having a channel formation region of the fourth semiconductor having an amorphous or semi-amorphous structure; An insulated gate semiconductor device characterized by having: 2. In claim 1, the insulated gate type semiconductor device of Introduction 1 in the solid-state display device is provided in a peripheral circuit, and the second insulated gate type semiconductor device is used as an insulated gate type semiconductor device for controlling picture elements. An insulated gate type semiconductor device characterized in that: 3. A first semiconductor, a second semiconductor, and a third semiconductor are stacked in substantially the same shape on a substrate or a lower electrode on a substrate, and the first and third semiconductors are used as a source and a source. An insulated gate comprising a drain, and comprising a gate insulating film on each channel forming side surface around two sides of the second semiconductor, and a respective dito electrode adjacent to the gate insulating crotch. type semiconductor device.