JPH05257163A - Composite semiconductor device - Google Patents

Abstract

PURPOSE:To enable the formation of plural IGFs, resistance, etc., on an insulating substrate by providing capacitors serially connected to the sources or drains of insulated gate type field-effect semiconductor devices having laminated projecting shapes on a substrate. CONSTITUTION:This composite semiconductor device has the field-effect semiconductor device (IGF) 10 consisting of a first semiconductor (S1) 12 having a conduction type of a p<+> type, a second intrinsic or N or p type semiconductor (S2) 14, a third semiconductor (S3) 15 having the same conduction type as the conduction type of the first semiconductor and the gate part consisting of a gate insulator 16 and a gate electrode 17 on a substrate 1. The other part of the S1 and S2 connected an electric system has one electrode 22 of the capacitor 24 and this other part is constituted with one electrode 32 of the liquid crystal display as well. The storage capacitor and the liquid crystal indicated by an equiv. circuit of the liquid crystal capacitor (liquid crystal display part) are connected and provided in parallel and may be provided in series as well.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal electro-optical device provided with a vertical channel type laminated insulating gate type semiconductor device on a substrate.

Furthermore, the present invention relates to a liquid crystal electro-optical device provided with a composite semiconductor device having a capacitor connected to the source or drain of a laminated insulating gate type field effect semiconductor device on a substrate.

The present invention is characterized in that such a composite semiconductor device is provided in a matrix structure on a substrate and a liquid crystal display type display device is provided.

In the present invention, when a surface type solid-state display device is provided, a liquid crystal display device is known in which electrodes are provided in parallel glass plates and liquid crystal is injected between the electrodes. However, in this case, the number of picture elements in this display is limited to 20 to 200. If the number of picture elements is more than this, as many terminals as there are picture elements need to be taken out from this display. I couldn't. Therefore, a field effect semiconductor device (referred to as IGF) corresponding to the picture element is required in order to form this display unit into a plurality of picture elements, form a matrix, and control any picture element to turn it on or off. I was trying. Then, a control signal is applied to this IGF to turn on or off the corresponding picture element.

This liquid crystal display section can be represented by a capacitor (hereinafter referred to as C) as its equivalent circuit. Therefore, for example, IGF and C are arranged in a matrix of 2 × 2 (40)
Fig. 1 shows the result.

In FIG. 1, the matrix (40) constitutes one picture element by one IGF (10) and one C (31). This is connected to the bit lines (51) and (51 ') in rows, while the gates are connected to provide columns (41) and (41').

Then, for example, (51) and (41) are set to "1",
When (51 ') and (41') are set to "0", only the address of (1,1) is selected and turned on, and the liquid crystal display electrically equivalent to C (31) is selectively turned on. Can be An object of the present invention is to provide another insulating gate type semiconductor device (50), another inverter (60) and a resistor (70) on the same substrate in order to configure a decoder and a driver on the same substrate.

Thus, by combining the present invention on the basis of its design specifications, a solid-state display device for a flat-screen television, which replaces the CRT, can be manufactured.

Further, there are 10 display devices for the calculator.
^It is enough to accumulate ² to 10 ³ picture elements, and 10 ⁴ for TV.
It can be seen that 10 ⁵ pieces, for example, 25 × 10 ³ picture elements are provided on the same substrate, and an IGF, an inverter, and a resistor in which the necessary decoders and drivers are simultaneously formed around the picture elements can be used.

The present invention relates to a laminated IGF necessary for making a system according to the present invention and a picture element in which a liquid crystal display section is connected to the IGF.

FIG. 2 shows a vertical sectional view of the laminated IGF of the present invention and a manufacturing process thereof.

In the drawing, a first semiconductor (2) (hereinafter simply referred to as S1) having a P ⁺ or N ⁺ type conductivity type on an insulating substrate, for example, a glass or alumina substrate, having a thickness capable of passing a tunnel current or semi-insulating. Film (3) Laminated a second intrinsic or N or P type semiconductor (4) (hereinafter simply referred to as S2) and a third semiconductor (5) having the same conductivity type as the first semiconductor (hereinafter simply referred to as S3) I set it up.

This semiconductor is provided on a substrate at a temperature of room temperature to 500 ° C. by utilizing the glow discharge method of silane.
A silicon semiconductor having an amorphous or semi-amorphous structure is used. In the present invention, a semi-amorphous semiconductor (hereinafter referred to as SAS) is mainly shown. Regarding this SAS, a patent application which becomes the invention of the present inventor, for example, Japanese Patent Application No. 55-143885 (application for 55.10.15) (semi-amorphous semiconductor), Japanese Patent Application No. 55-122786 (application for 55.9.4) (semiconductor device), Japanese Patent Application A detailed example is shown in Japanese Patent Application Laid-Open No. 55-026388 (55.3.3 application) (semi-amorphous semiconductor).

Further, in FIG. 2, S3 was selectively removed by a photolithography technique, and then S2 was removed using this S3 as a mask. In order to see the end point of this photoetching, the insulating or semi-insulating film (hereinafter simply referred to as an insulating film) (13) was formed by using silicon nitride.

Further, its thickness is 5 to 30 Å, which was achieved by exposing the first semiconductor to an ammonia atmosphere exposed to plasma irradiation. Next, this insulating film (13)
After being chemically removed, FIG. 2 (B) was obtained.

In order to make the insulating film formed later on S3 thicker, a silicon oxide film may be formed in advance to a thickness of 0.3 to 1 μm by the LPCVD method (decompression vapor phase method). Good. In addition, 0.2 Mo and W on this S3
~0.5μ further improving the electrical conductivity at S3 by the SiO ₂ and 0.3~1μ thereon was effective to matrixing.

In FIG. 2 (B), the side surface may be formed vertically on the surface of the substrate (1), but the trapezoid is taper-etched to further cut the step at the stepped portion of the gate electrode to be further laminated. It was effective to remove.

Further, as shown in FIG. 2 (C), S1 was formed into an arbitrary predetermined shape by the photolithography technique. For this reason, in the drawing, the substrate surface was exposed at (11).

After this, an insulating film (6) was formed on the entire surface of S1, S2 and S3. This insulating film is 13.56
It was formed by being activated by electromagnetic energy with a frequency of MHz to 2.45 GHz, immersed in oxygen or a mixed gas atmosphere of oxygen and hydrogen at 100 to 700 ° C., and oxidized.

Further, a multi-layer structure in which silicon nitride or phosphorus glass is formed by the LPCVD method may be used.

Then, a gate insulator is formed around the S2 (14) side.
This insulator (16) was formed as (16), and the surfaces of S1 and S3 could be formed as a film for isolation.

Further, as shown in (D), an electrode hole (8) is formed in S1 (12) and an electrode hole (7) is formed in S3 (15) by the third photolithography technique to connect to the gate electrode. The metal or semiconductor layer was laminated again.

Next, this film is selectively etched by the fourth photolithography technique to form the gate electrodes (17) with the gate insulators (16) and (16 ') in two directions, and at the same time, S1 ( 12), S3 (15) through the electrode hole, IGF of other parts,
The capacitors and resistors were routed closely to the substrate surface or insulator (6).

The vertical sectional view AA 'of FIG. 2D can be seen as FIG. 2E when viewed from the lateral direction. The numbers correspond to each other.

The semiconductor of the present invention mainly uses SAS,
Hydrogen is used to neutralize the dangling bonds among them, and the substrate, semiconductor, and electrode leads are made of different materials, and all treatments are performed at 300 to 600 ° C in order to reduce stress due to their thermal expansion. It is preferable that the temperature is preferably 300 ° C. or lower.

Further, the gate electrode (17) may have a multi-layer wiring structure in which a semiconductor of the same conductivity type as S1 and S3 and a double structure of a metal such as Mo are added to the semiconductor.

Thus, the source or drain is connected to S1 (1
2), S2 (14) having channel forming regions (9) and (9 '), drain or source is formed by S3 (15), and gate insulators (16) and (16') are formed on the sides of the channel forming region. A laminated type IGF (10) having a gate electrode (17) on its outer surface could be produced.

In the present invention, it is determined by the thickness of the channel length S2 (14), and here it is set to 0.05 to 0.5 μm.
The mobility of SAS is one-fifth that of single crystals, unlike that of single crystals.
Since there is only 1/100, IGF
It is to promote the characteristics as.

The SAS has an electron bulk mobility of 100 to 5
It is 5 to 100 cm ² V / S and 1/5 to 1/100, while 00 cm ² V / S and 1/3 to 1/10. However, amorphous silicon has 0.1-10 electrons.
cm ² V / S, hole is 10 to 1 compared to 0.01 cm ² V / S or less
Considering that it is as long as 0 ³ times, it is extremely important to use the SAS having a microcrystal structure in the semiconductor device of the present invention.

Furthermore, in the IGF of the present invention, the electron mobility is 5 to 10 times larger than that of a single crystal, which is 3 times that of a single crystal.
Since it is 0 times, it was very preferable to use the N-channel type.

Therefore, since an intrinsic semiconductor of S2 in which impurities are not added to the surface portion is N ⁻ type, it is used as P type.

FIG. 3 is a vertical sectional view of another IGF of the present invention and a manufacturing process thereof.

In FIG. 3A, a silicon film of SAS was formed as S1 (2) on the substrate (1). Furthermore, selective etching is performed by photolithography technology, and the substrate (1)
Exposed part (11) of.

Next, optical (laser) annealing for crystallizing the SAS, thermal annealing, or a combination thereof was used to transform the SAS into a single crystal or polycrystal structure. The heating temperature was set to 700 ° C. or lower in order to prevent thermal stress on the substrate material.

Basically, the etching rate of S1 (2) may be different from that of S2 and S3. For this reason, S1 is added with P- or N-type oxygen or nitrogen to form SiO _2−x (0.
It may be a semiconductor having an intrinsic or semi-insulating property with a stoichiometry of 5 <x <2) and Si ₃ N _4-x (1 <x <4).

After this, as shown in FIG.
2 (4) was intrinsic, N ⁻ or P type, and S3 (5) was laminated on the same conductivity type as S1 to P or N type and formed in the same reaction furnace.

Further, as shown in FIG. 3C, this S2 (4)
, S3 (5) are formed to have substantially the same shape by selectively removing the other part, and S2 (14) and S3 (15) are provided on S1 (12). Then, the upper surface of S1, S2 and S3 is oxidized to form an insulating film (6).
It was established as. At this time, the gate insulating film is around the S2 (14) side.
It was provided as (16), and the other part was provided as an isolation film.

Next, a semiconductor or conductor film was provided on the entire upper surface of the electrode holes or contact portions (7) and (8) by using the third photolithography technique. This film is the fourth
Is selectively removed by the photolithography technology of
Connect the continuous electrode lead (22) to the other part to 1 (12) with S3 (1
Similar electrodes and leads are provided on 5) via contacts (7), and channel formation regions (9), (9 ') around the S2 (14) side.
A gate electrode (17) was formed on the side surfaces of the gate electrodes (16) and (16 ').

In this way, the source or drain is S
The channel forming regions (9) and (9 ') are made of S1 (12), and the drain or source is made of S3 (15). Gates are gate insulators (16), (16 ') and gate electrodes (17)
Has become. In this way, when the gate electrode is set to "1" and the source or drain is set to "1", a current flows through the channel forming region to turn on, and if one or both of them is "0", an off state can be created. did it.

"1" is a positive value of 0 for N-channel IGF.
A current of 5 to 10 V, "0" means a current of 0 V or less than the threshold voltage.

For the P-channel type IGF, the polarity of its electrode may be changed. These logic systems are the same in FIGS. 1 and 2 and also in FIG. 3 and the embodiments of the present invention.

The resistance 70 of FIG. 1 is determined by the resistivity of the bulk component of S2 regardless of the voltage applied to the gate in FIGS. 2D, 2E and 3D. That is, S1, S2, and S3 may be stacked without providing the gate electrode.
Further, this resistance value may be determined according to the design specifications by the resistivity of S2, its thickness, and the area to be formed on the substrate.

A driver for the inverter (60) of FIG.
(61) is shown in Fig. 2 and Fig. 3 (D), and its load (64) is S
An enhancement-type or depletion-type IG that connects one of 3 (15) and S1 (12) to the gate electrode (17)
It was set to F.

Further, the output of the inverter (60) is composed of (62), and two IGFs may be laminated on the substrate at a distance to form a composite, and the input portion corresponds to the gate electrode (17). It should be provided.

FIG. 4A shows another vertical sectional view of the present invention. That is, S1 (12), S2 (1
4), S3 (15) and IGF (10) whose gate part is composed of a gate insulator (16) and a gate electrode (17), and the other part which is S1 (12) and is connected to the electric system is one of the capacitors. Electrode (2
2), and the other part also constitutes one electrode (32) of the liquid crystal display. That is, S1 is one of the electrodes of the two capacitors. One of the capacitors is used to increase the storage capacity and the display time of the liquid crystal display.

That is, even if the time when a specific IGF is turned on in FIG. 1 is 10 to 100 nsec, the liquid crystal display has a display of 1 to 1000 msec because the liquid crystal panel and the capacitor are connected in series. The so-called afterglow characteristic could be provided. For this reason, if the storage (storage capacitor) is large, the display on a flat panel corresponding to, for example, a TV CRT becomes sharp, and the number of picture elements becomes 10 ⁴ to 10 ⁵ , and these are scanned digitally. However, it is possible to keep displaying "0" and "1" on other picture elements. The effectiveness of this storage capacity is effective in order to prevent the viewer from being blinded when the number of picture elements exceeds 10.

By using the same material as the gate insulator (16) for this storage capacitor, it was possible to fabricate the same badge type without any new process. However, in order to increase this capacitance in a small area, silicon nitride, tantalum oxide or other ferroelectric material may be used instead of silicon oxide.

Another electrode (32) electrically connected to S1 (12) in the present invention is provided through an electrode hole (25). An interlayer insulating material such as polyimide or PIQ having a thickness of 1 to 3 μm may be provided on these IGF (10) and selectively provided by a photolithography technique. This electrode (32) determines the size of one picture element. Calculators and the like have a shape of 0.1 to 5 mmφ or a square shape. However, in the scanning type system as shown in FIG.
μ □ was used as a matrix and was set to 500 × 500. The liquid crystal display part (31) has one electrode having a semiconductor device electrode on this substrate and the other having a glass plate (28) having a transparent electrode (27) such as ITO with a gap of 1 to 20 μm. For example, a nematic liquid crystal (26) was injected and provided there.

The display may be color-displayed. Further, for example, these picture elements may be triple-layered. Then, the three elements of red, green and blue should be arranged alternately.

In contrast to FIG. 4 (A), in which the storage capacitor and the liquid crystal shown by the equivalent circuit of the liquid crystal capacitor are connected in parallel, FIG. 4 (B) is provided in series.

That is, the dielectric film (23) on the one electrode (22) electrically connected to S1 (12), the other electrode (24), and the second liquid crystal capacitor (24) connected to this electrode (24). One electrode (32) of (31) is connected through the opening (25)
Corresponding to (32), counter electrode (27) with transparent electrode is liquid crystal (26)
It is provided with a dielectric between them.

As is apparent from FIGS. 4A and 4B, the present invention is a substrate
(1) A flat panel for liquid crystal display is provided as a plurality of IGF capacitors, resistors or a sandwich structure at the same time.

Further, as is apparent from the drawing, in order to prevent the light from irradiating the IGF (10) from above when it is in the "0" state, it is covered from above in order to prevent it from leaking. Another feature is that one electrode (32) of the picture element is provided.

In addition, unlike the prior art, the fact that the IGF is provided in a laminated type completely isolated from other picture elements on the insulating substrate is a very great feature. Especially, this entire process is performed at 600 ° C. or less, particularly 300 ° C. The fact that the panel can be manufactured at the following temperatures has a great feature that the panel is not easily affected by thermal strain even if it has a large area.

In addition, the semiconductor used in the present invention is mainly composed of a non-single crystal structure, and in particular, it has an intermediate structure of SAS called amorphous and single crystal, and is stable against heat energy up to 600 ° C. It is another feature of the present invention.

Particularly, SAS is a non-single crystal semiconductor having a large microcrystal structure with a lattice distortion of 10 to 100 Å, and the temperature up to 300 ° C. is sufficient for its production even if inductive energy of 500 KHz to 3 GHz is used. In addition, the diffusion length of the electrons and holes is 10 for amorphous silicon.
It has the physical property of being 0 to 10 ⁵ times as large.
With the structure in which such a non-single crystal semiconductor is laminated on a substrate,
Since the IGF is provided, and in addition, a current flows in the vertical direction, a microchannel type IGF having a channel length of 0.1 to 1 μ can be manufactured without using a highly accurate photolithography technique. Is.

Further, in the present invention, the characteristic as IGF is in consideration of the characteristic of SAS, and the threshold voltage (V _TM ) thereof is not the doping by the ion implantation method but the addition amount of the impurity added to S2. Another feature is that it is controlled by high frequency power.

Therefore, withstand voltage 20 to 30 V, V _TM = −4 to
It was possible to control 4 V within a range of ± 0.2 V. Furthermore, since the frequency characteristic is a micro channel having a channel length of 0.1 to 1 μ, it is one of the conventional single crystal type insulated gate semiconductor devices.
/ 5 to 1/50 could be obtained even though the non-single crystal semiconductor was used.

Although it is a reverse leak, by inserting silicon nitride to a thickness of 10 to 40Å between S1 and S2 as shown in FIG. 1, this N ⁺ -P junction or P ^{+ is formed.}
-N junction leakage is 10 mA even if 10 V is applied in the reverse direction.
It was below. This was a favorable comparison with the reverse leakage of a single crystal.

Further, S1 is, for example, oxygen of 10 to 30 mol%.
When added, in the structure shown in FIG. 3, similarly, there is little leakage in the opposite direction, which is 1/10 to 10% as compared with the case of no addition.
The leak was 1/10 times less. It is natural that this small amount of leakage is very effective when implementing the matrix structure of FIG.

Further, this reverse leakage is due to this laminated type S
When S1, S2, and S3 are made of only amorphous silicon semiconductor, 1 mA is applied when a reverse bias of 10 V is applied.
Although it was above, when it was set to SAS, it fell to 5 to 50 nA. It is 0 in the case where the impurities of B and P in the P or N type semiconductor of S1 and S3 are coordinated to the substitution type and the ionization rate thereof is 4N or more like the single crystal and the activation energy thereof is also amorphous. .2-0.3
This is because it was smaller than eV by 0.005 to 0.001 eV.

For this reason, the impurities that have once been coordinated did not out-diffuse during lamination, and as a result, the junction was clean.

That is, the present invention is a laminated type IGF, a non-single crystal semiconductor is used therefor, especially SAS is used, and nitric oxide is added to S1 to clarify the junction between S1 and S2. It is characterized in that it is added at the same time to increase the reverse withstand voltage mainly as an energy band width, or to form an SIS junction with an insulating or semi-insulating film interposed.

Further, because of the laminated type IGF, it becomes possible to form a plurality of IGFs, resistors, and capacitors on a substrate, particularly an insulating substrate, without using a high-precision photolithography technique as in the past. And it has become possible to develop it into a liquid crystal display.

Silicon is used as the semiconductor in the present invention, and silicon oxide or silicon nitride is used as the insulator. However, germanium, InP, BP, GaAs or the like may be used as the semiconductor. Needless to say, a single crystal semiconductor may be used instead of the non-single crystal semiconductor, and a polycrystalline semiconductor having a large crystal grain size may be used instead of the SAS.

[Brief description of drawings]

FIG. 1 shows an equivalent circuit of an insulating gate type semiconductor device, an inverter resistance, a capacitor used in a liquid crystal electro-optical device according to the present invention, or a matrix structure in which an insulating gate type semiconductor device and a capacitor are picture elements.

FIG. 2 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device used in a liquid crystal electro-optical device according to the present invention.

FIG. 3 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device used for a liquid crystal electro-optical device according to the present invention.

FIG. 4 is a vertical cross-sectional view of a composite semiconductor showing a planar display in which a laminated insulating gate type semiconductor device of the present invention and a capacitor or liquid crystal are integrated.

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[Procedure amendment]

[Submission date] September 5, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Composite semiconductor device

[Claims]

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device having a vertical channel-type stacked insulating gate type field effect semiconductor device provided on a substrate.

Further, the present invention provides a composite semiconductor device having a capacitor connected to a source or a drain of an insulating gate type field effect semiconductor device having a stacked convex shape on a substrate in series.

The present invention is characterized in that such a composite semiconductor device is provided in a matrix structure on a substrate and a liquid crystal display type display device is provided.

In the present invention, when a surface type solid-state display device is provided, a liquid crystal display device is known in which electrodes are provided in parallel glass plates and liquid crystal is injected between the electrodes. However, in this case, the number of picture elements in this display is limited to 20 to 200. If the number of picture elements is more than this, as many terminals as there are picture elements need to be taken out from this display. I couldn't. Therefore, a field effect semiconductor device (referred to as IGF) corresponding to the picture element is required in order to form this display unit into a plurality of picture elements, form a matrix, and control any picture element to turn it on or off. I was trying. Then, a control signal is applied to this IGF to turn on or off the corresponding picture element.

This liquid crystal display section can be represented by a capacitor (hereinafter referred to as C) as its equivalent circuit. Therefore, for example, IGF and C are arranged in a matrix of 2 × 2 (40)
Fig. 1 shows the result.

In FIG. 1, the matrix (40) constitutes one picture element by one IGF (10) and one C (31). This is connected to the bit lines (51) and (51 ') in rows, while the gates are connected to provide columns (41) and (41').

Then, for example, (51) and (41) are set to "1",
When (51 ') and (41') are set to "0", only the address of (1,1) is selected and turned on, and the liquid crystal display electrically equivalent to C (31) is selectively turned on. Can be An object of the present invention is to provide another insulating gate type semiconductor device (50), another inverter (60) and a resistor (70) on the same substrate in order to configure a decoder and a driver on the same substrate.

Thus, by combining the present invention on the basis of its design specifications, a solid-state display device for a flat-screen television, which replaces the CRT, can be manufactured.

Further, there are 10 display devices for the calculator.
^It is enough to accumulate ² to 10 ³ picture elements, and 10 ⁴ for TV.
It can be seen that 10 ⁵ pieces, for example, 25 × 10 ³ picture elements are provided on the same substrate, and an IGF, an inverter, and a resistor in which the necessary decoders and drivers are simultaneously formed around the picture elements can be used.

The present invention relates to a laminated IGF necessary for making a system according to the present invention and a picture element in which a liquid crystal display section is connected to the IGF.

FIG. 2 shows a vertical sectional view of the laminated IGF of the present invention and a manufacturing process thereof.

In the drawing, a first semiconductor (2) (hereinafter simply referred to as S1) having a P ⁺ or N ⁺ type conductivity type on an insulating substrate, for example, a glass or alumina substrate, having a thickness capable of passing a tunnel current or semi-insulating. Film (3) Laminated a second intrinsic or N or P type semiconductor (4) (hereinafter simply referred to as S2) and a third semiconductor (5) having the same conductivity type as the first semiconductor (hereinafter simply referred to as S3) I set it up.

This semiconductor is provided on a substrate at a temperature of room temperature to 500 ° C. by utilizing the glow discharge method of silane.
A silicon semiconductor having an amorphous or semi-amorphous structure is used. In the present invention, a semi-amorphous semiconductor (hereinafter referred to as SAS) is mainly shown. Regarding this SAS, a patent application which becomes the invention of the present inventor, for example, Japanese Patent Application No. 55-143885 (application for 55.10.15) (semi-amorphous semiconductor), Japanese Patent Application No. 55-122786 (application for 55.9.4) (semiconductor device), Japanese Patent Application A detailed example is shown in Japanese Patent Application Laid-Open No. 55-026388 (55.3.3 application) (semi-amorphous semiconductor).

Further, in FIG. 2, S3 was selectively removed by a photolithography technique, and then S2 was removed using this S3 as a mask. In order to see the end point of this photoetching, the insulating or semi-insulating film (hereinafter simply referred to as an insulating film) (13) was formed by using silicon nitride.

Further, its thickness is 5 to 30 Å, which was achieved by exposing the first semiconductor to an ammonia atmosphere exposed to plasma irradiation. Next, this insulating film (13)
After being chemically removed, a convex semiconductor shown in FIG. 2 (B) was obtained.

In order to make the insulating film formed later on S3 thicker, a silicon oxide film may be formed in advance to a thickness of 0.3 to 1 μm by the LPCVD method (decompression vapor phase method). Good. In addition, 0.2 Mo and W on this S3
~0.5μ further improving the electrical conductivity at S3 by the SiO ₂ and 0.3~1μ thereon was effective to matrixing.

Further, in FIG. 2B, the side surface may be formed vertically on the surface of the substrate (1), but a trapezoidal taper etch is performed to form a step cut at the step portion of the gate electrode to be further laminated. It was effective to remove.

Further, as shown in FIG. 2 (C), S1 was formed into an arbitrary predetermined shape by the photolithography technique. For this reason, in the drawing, the substrate surface was exposed at (11).

After this, an insulating film (6) was formed on the entire surface of S1, S2 and S3. This insulating film is 13.56
It was formed by being activated by electromagnetic energy with a frequency of MHz to 2.45 GHz, immersed in oxygen or a mixed gas atmosphere of oxygen and hydrogen at 100 to 700 ° C., and oxidized.

Further, a multi-layer structure in which silicon nitride or phosphorus glass is formed by the LPCVD method may be used.

Then, a gate insulator is formed around the S2 (14) side.
This insulator (16) was formed as (16), and the surfaces of S1 and S3 could be formed as a film for isolation.

Further, as shown in FIG. 2D, an electrode hole is formed on the S1 (12) by the third photolithography technique.
An electrode hole (7) was formed in (8) for S3 (15), and a metal or semiconductor layer connected to the gate electrode was laminated again.

Next, this film is selectively etched by the fourth photolithography technique to form the gate electrodes (17) with the gate insulators (16) and (16 ') in two directions, and at the same time, S1 ( 12), S3 (15) through the electrode hole, IGF of other parts,
The capacitors and resistors were routed closely to the substrate surface or insulator (6).

The vertical sectional view AA 'of FIG. 2D can be seen as FIG. 2E when viewed from the lateral direction. The numbers correspond to each other.

The semiconductor of the present invention mainly uses SAS,
Hydrogen is used to neutralize the dangling bonds among them, and the substrate, semiconductor, and electrode leads are made of different materials, and all treatments are performed at 300 to 600 ° C in order to reduce stress due to their thermal expansion. It is preferable that the temperature is preferably 300 ° C. or lower.

Further, the gate electrode (17) may have a multi-layer wiring structure in which a semiconductor of the same conductivity type as S1 and S3 and a double structure of a metal such as Mo are added to the semiconductor.

Thus, the source or drain is connected to S1 (1
2), S2 (14) having channel forming regions (9) and (9 '), drain or source is formed by S3 (15), and gate insulators (16) and (16') are formed on the sides of the channel forming region. A laminated type IGF (10) having a gate electrode (17) on its outer surface could be produced.

In the present invention, the channel length is determined by the thickness of S2 (14), which is 0.05 to 0.5 μm here. The mobility of SAS is different from that of single crystal.
Since there is only 5 to 1/100, shorten the channel length
It is to promote the characteristics of GF.

The SAS has an electron bulk mobility of 100 to 5
It is 5 to 100 cm ² V / S and 1/5 to 1/100, while 00 cm ² V / S and 1/3 to 1/10. However, amorphous silicon has 0.1-10 electrons.
cm ² V / S, hole is 10 to 1 compared to 0.01 cm ² V / S or less
Considering that it is as long as 0 ³ times, it is extremely important to use the SAS having a microcrystal structure in the semiconductor device of the present invention.

Furthermore, in the IGF of the present invention, the electron mobility is 5 to 10 times larger than that of a single crystal, which is 3 times that of a single crystal.
Since it is 0 times, it was very preferable to use the N-channel type.

Therefore, since an intrinsic semiconductor of S2 in which impurities are not added to the surface portion is N ⁻ type, it is used as P ⁻ type.

FIG. 3 is a vertical sectional view of another IGF of the present invention and a manufacturing process thereof.

In FIG. 3A, a silicon film of SAS was formed as S1 (2) on the substrate (1). Furthermore, selective etching is performed by photolithography technology, and the substrate (1)
Exposed part (11) of.

Next, optical (laser) annealing for crystallizing the SAS, thermal annealing, or a combination thereof was used to transform the SAS into a single crystal or polycrystal structure. The heating temperature was set to 700 ° C. or lower in order to prevent thermal stress on the substrate material.

Basically, the etching rate of S1 (2) may be different from that of S2 and S3. For this reason, S1 is added with P- or N-type oxygen or nitrogen to form SiO _2−x (0.
It may be a semiconductor having an intrinsic or semi-insulating property with a stoichiometry of 5 <x <2) and Si ₃ N _4-x (1 <x <4).

After this, as shown in FIG.
2 (4) was intrinsic, N ⁻ or P ⁻ type, and S3 (5) was laminated on the same conductivity type as S1 to form P or N type and formed in the same reaction furnace.

Further, as shown in FIG. 3C, this S2 (4)
, S3 (5) are made to have substantially the same shape, and the other portions are selectively removed to form a convex semiconductor, and S2 (14) and S3 (15) are replaced by S1 (12).
I set it up. After that, the upper surfaces of S1, S2 and S3 were oxidized to provide an insulating film (6). At this time, the periphery of the S2 (14) side was provided as a gate insulating film (16), and the other part was provided as an isolation film.

Next, a semiconductor or conductor film was provided on the entire upper surface of the electrode holes or contact portions (7) and (8) by using the third photolithography technique. This film is the fourth
Is selectively removed by the photolithography technology of
Connect the continuous electrode lead (22) to the other part to 1 (12) with S3 (1
Similar electrodes and leads are provided on 5) via contacts (7), and channel formation regions (9), (9 ') around the S2 (14) side.
A gate electrode (17) was formed on the side surfaces of the gate electrodes (16) and (16 ').

In this way, the source or drain is S
The channel forming regions (9) and (9 ') are made of S1 (12), and the drain or source is made of S3 (15). Gates are gate insulators (16), (16 ') and gate electrodes (17)
Has become. In this way, when the gate electrode is set to "1" and the source or drain is set to "1", a current flows through the channel forming region to turn on, and if one or both of them is "0", an off state can be created. did it.

"1" is a positive value of 0 for N-channel IGF.
A current of 5 to 10 V, "0" means a current of 0 V or less than the threshold voltage.

For the P-channel type IGF, the polarity of its electrode may be changed. These logic systems are the same in FIGS. 1 and 2 and also in FIG. 3 and the embodiments of the present invention.

The resistance 70 of FIG. 1 is determined by the resistivity of the bulk component of S2 regardless of the voltage applied to the gate in FIGS. 2D, 2E and 3D. That is, S1, S2, and S3 may be stacked without providing the gate electrode.
Further, this resistance value may be determined according to the design specifications by the resistivity of S2, its thickness, and the area to be formed on the substrate.

A driver for the inverter (60) of FIG.
(61) is shown in Fig. 2 and Fig. 3 (D), and its load (64) is S
An enhancement-type or depletion-type IG that connects one of 3 (15) and S1 (12) to the gate electrode (17)
It was set to F.

Further, the output of the inverter (60) is composed of (62), and two IGFs may be laminated on the substrate at a distance to form a composite, and the input portion corresponds to the gate electrode (17). It should be provided.

FIG. 4A shows another vertical sectional view of the present invention. That is, S1 (12), S2 (1
4), S3 (15) and IGF (10) whose gate part is composed of a gate insulator (16) and a gate electrode (17), and the other part which is S1 (12) and is connected to the electric system is one of the capacitors. Electrode (2
2), and the other part also constitutes one electrode (32) of the liquid crystal display. That is, S1 is one of the electrodes of the two capacitors. One of the capacitors is used to increase the storage capacity and the display time of the liquid crystal display.

That is, in FIG. 1, even when a specific IGF is turned on for 10 to 100 ns and the off state is maintained as it is, the liquid crystal display is displayed because the liquid crystal panel and the capacitor are connected in series. Is 1-100
It has a so-called afterglow characteristic of 0 ms and is on (transmitted).
Or it could be off (non-transparent). For this reason, if the storage (storage capacitor) is large, the display on a flat panel corresponding to, for example, a TV CRT becomes sharp, and the number of picture elements becomes 10 ⁴ to 10 ⁵ , and these are scanned digitally. However, it is possible to continue displaying "0" and "1" on other picture elements.
The effectiveness of this storage capacity is effective in order to prevent the viewer from being blinded when the number of picture elements exceeds 10.

By using the same material as the gate insulator (16) for this storage capacitor, it was possible to fabricate the same badge type without any new process. However, in order to increase this capacitance in a small area, silicon nitride, tantalum oxide or other ferroelectric material may be used instead of silicon oxide.

Another electrode (32) electrically connected to S1 (12) in the present invention is provided through an electrode hole (25). An interlayer insulator such as polyimide or PIQ having a thickness of 1 to 3 μm may be provided on these IGFs (10) and selectively provided by a photolithography technique. This electrode (32) determines the size of one picture element. Calculators and the like have a shape of 0.1 to 5 mmφ or a square shape. However, in the scanning type system as shown in FIG.
μm □ was formed into a matrix and made 500 × 500.
The liquid crystal display part (31) has one electrode having a semiconductor device electrode on this substrate and the other having a glass plate (28) having a transparent electrode (27) such as ITO with a gap of 1 to 20 μm. For example, a nematic liquid crystal (26) was injected and provided there.

The display may be color-displayed. Further, for example, these picture elements may be triple-layered. Then, the three elements of red, green and blue should be arranged alternately.

In FIG. 4 (A), a storage capacitor and a liquid crystal capacitor (liquid crystal display section) are provided in parallel connection with the liquid crystal, whereas in FIG. 4 (B), they are provided in series. It is a thing.

That is, the dielectric film (23) on the one electrode (22) electrically connected to S1 (12), the other electrode (24), and the second liquid crystal capacitor (24) connected to this electrode (24). One electrode (32) of (31) is connected through the opening (25)
Corresponding to (32), counter electrode (27) with transparent electrode is liquid crystal (26)
It is provided with a dielectric between them.

As is apparent from FIGS. 4A and 4B, the present invention is a substrate
(1) A flat panel for liquid crystal display is provided as a plurality of IGF capacitors, resistors or a sandwich structure at the same time.

Further, as is apparent from the drawing, in order to prevent the light from irradiating the IGF (10) from above when it is in the "0" state, it is covered from above in order to prevent it from leaking. Another feature is that one electrode (32) of the picture element is provided.

In addition, unlike the prior art, the fact that the IGF is provided in a laminated type completely isolated from other picture elements on the insulating substrate is a very great feature. Especially, this entire process is performed at 600 ° C. or less, particularly 300 ° C. The fact that the panel can be manufactured at the following temperatures has a great feature that the panel is not easily affected by thermal strain even if it has a large area.

Thus, it was possible to provide a convex semiconductor on the substrate, and to provide a vertical channel type insulated gate field effect semiconductor device and a capacitor in series with it on both sides of this semiconductor.

In addition, the semiconductor used in the present invention is mainly composed of a non-single crystal structure, and in particular, it has an intermediate structure of SAS called amorphous and single crystal and is stable against heat energy up to 600 ° C. It is another feature of the present invention.

Particularly, SAS is a non-single crystal semiconductor having a large microcrystal structure with a lattice distortion of 10 to 100 Å, and the temperature up to 300 ° C. is sufficient for its production even if inductive energy of 500 KHz to 3 GHz is used. In addition, the diffusion length of the electrons and holes is 10 for amorphous silicon.
It has the physical property of being 0 to 10 ⁵ times as large.
With the structure in which such a non-single crystal semiconductor is laminated on a substrate,
Since the IGF is provided, and in addition, a current flows in the vertical direction, a microchannel type IGF having a channel length of 0.1 to 1 μ can be manufactured without using a highly accurate photolithography technique. Is.

Further, in the present invention, the characteristic as IGF is in consideration of the characteristic of SAS, and the threshold voltage (V _TM ) thereof is not, for example, doped by the ion implantation method, but the amount of impurities added to S2 and the high frequency to be added. Another feature is that it is controlled by power.

Therefore, withstand voltage 20 to 30 V, V _TM = −4 to
It was possible to control 4 V within a range of ± 0.2 V. Furthermore, since the frequency characteristic is a micro channel having a channel length of 0.1 to 1 μ, it is one of the conventional single crystal type insulated gate semiconductor devices.
/ 5 to 1/50 could be obtained even though the non-single crystal semiconductor was used.

Although it is a reverse leak, by inserting silicon nitride to a thickness of 10 to 40Å between S1 and S2 as shown in FIG. 1, this N ⁺ -P junction or P ^{+ is formed.}
-N junction leakage is 10 mA even if 10 V is applied in the reverse direction.
It was below. This was a favorable comparison with the reverse leakage of a single crystal.

Further, S1 is, for example, oxygen of 10 to 30 mol%.
When added, in the structure shown in FIG. 3, similarly, there is little leakage in the opposite direction, which is 1/10 to 10% as compared with the case of no addition.
The leak was 1/10 times less. It is natural that this small amount of leakage is very effective when implementing the matrix structure of FIG.

Further, this reverse leakage is due to this laminated type S
When S1, S2, and S3 are made of only amorphous silicon semiconductor, 1 mA is applied when a reverse bias of 10 V is applied.
Although it was above, when it was set to SAS, it fell to 5 to 50 nA. It is 0 in the case where the impurities of B and P in the P or N type semiconductor of S1 and S3 are coordinated to the substitution type and the ionization rate thereof is 4N or more like the single crystal and the activation energy thereof is also amorphous. .2-0.3
This is because it was smaller than eV by 0.005 to 0.001 eV.

For this reason, the impurities that have once coordinated do not out-diffuse during stacking, and as a result, the junction is clean.

That is, the present invention is a laminated IGF, a non-single crystal semiconductor is used therefor, especially SAS is used, and nitric oxide is added to S1 to clarify the junction between S1 and S2. It is characterized in that it is added at the same time to increase the reverse withstand voltage mainly as an energy band width, or to form an SIS junction with an insulating or semi-insulating film interposed.

Further, because of such a laminated type IGF, it becomes possible to form a plurality of IGFs, resistors and capacitors on a substrate, particularly an insulating substrate, without using a high precision photolithography technique as in the past. And it has become possible to develop it into a liquid crystal display.

In the present invention, silicon is used as the semiconductor and silicon oxide or silicon nitride is used as the insulator. Needless to say, a single crystal semiconductor may be used instead of the non-single crystal semiconductor, and a polycrystalline semiconductor having a large crystal grain size may be used instead of the SAS.

[Brief description of drawings]

FIG. 1 shows an equivalent circuit of an insulating gate type semiconductor device, an inverter resistance, a capacitor used in a liquid crystal electro-optical device according to the present invention, or a matrix structure in which an insulating gate type semiconductor device and a capacitor are picture elements.

FIG. 2 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device used in a liquid crystal electro-optical device according to the present invention.

FIG. 3 is a vertical cross-sectional view showing a process of a laminated insulating gate type semiconductor device used for a liquid crystal electro-optical device according to the present invention.

FIG. 4 is a vertical cross-sectional view of a composite semiconductor showing a planar display in which a laminated insulating gate type semiconductor device of the present invention and a capacitor or liquid crystal are integrated.

Claims (2)

[Claims] 1. A first impurity region having a convex semiconductor on a substrate, the source or drain being formed above the convex semiconductor, and the second impurity region being drain or forming the source below. And a channel is provided between the first and second impurity regions on one side of the convex semiconductor below the gate insulating film and the gate electrode. The first and second insulating gate type field effect semiconductor devices are provided by using both sides, and a capacitor is provided electrically in series with the second impurity region of the insulating gate type field effect semiconductor device. And a composite semiconductor device. 2. The liquid crystal display device according to claim 1, further comprising a liquid crystal between the other electrode of the capacitor and an on / off state of the display unit having the liquid crystal according to an on / off state of the insulated gate field effect semiconductor device. A compound semiconductor device characterized by being manufactured.