JPS6095970A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To isolate a plurality of semiconductor devices easily without using photolithography technique by utilizing a fact that a nonsingular crystal semiconductor can be treated completely as an insulator if the thickness of the nonsingular crystal semiconductor extends over decuple as large as that of a semiconductor film formed when a vertical channel type and laminated type complementary insulated gate type semiconductor device is shaped on an insulating substrate. CONSTITUTION:A first conductive film 2 for a lower side electrode consisting of an oxide, TiSi2, etc. is applied on an insulating substrate 1 made of glass, etc., and openings in desired number are bored through selective etching. A thick P type amorphous Si film 3 is laminated on the whole surface while burying these openings, only a section on a P channel type element forming region 10 is coated with a photo-resist film 71, and the exposed section of the film 3 is removed through etching. A thick N type amorphous Si film 3 is applied on the whole surface, the film 71 is removed together with the film 3' on the film 71, and a second semiconductor or an insulator 4 is applied on the connected and flattened films 3 and 3'. P type and N type semiconductor layers 5 and 5' each opposed to the films 3 and 3' are deposited on the insulator 4.

Description

Detailed Description of the Invention The present invention relates to a vertical channel stacked complementary insulated gate semiconductor device (hereinafter referred to as IGF) using a non-single crystal semiconductor on a substrate.
The complementary IGF is referred to as C/IGF).

The present invention provides at least two conductive electrodes laminated in five layers consisting of a first conductive electrode, a first semiconductor, a second semiconductor or insulator, a third semiconductor, and a second conductive electrode on an insulating substrate.
A fourth non-single-crystal semiconductor that forms a channel is provided around the sides of the two stacked bodies, and one of them is connected to a P-channel type IGF (
The purpose of this invention is to provide an N-channel IGF (hereinafter referred to as NIGF) (shown on the right side of the drawing) and an N-channel IGF (hereinafter referred to as NIGF) (shown on the left side of the drawing).

The present invention utilizes one laminate and makes one of the conductive electrodes common to each other, thereby connecting C/IGFs in series to form an inverter configuration.
The switch is constructed by connecting CPs in parallel and providing the electrodes of both in common, resulting in a C/IGF configuration even though it is a single laminate.

2. Description of the Related Art Complementary insulated field effect semiconductor devices (hereinafter also referred to as C/MO5) using single crystal silicon have been known.

An example of this is shown in FIG.

As is clear from the drawing, an N-type single crystal silicon substrate (
A P-well (93) is provided in 1), isolated by a buried field insulator (94), and the P-channel MO5, FET (10) and N-channel FIO5°FET (10') are connected to the source (23>), respectively. , G3)
, drain (25), <15), gate electrode (42),
(40) is shown.

Such a C7MO5 integrated circuit (IC) is of the horizontal channel type and electrically consists of three diodes (90).

(91), <92).

Providing these three diodes increases the isolation area, requiring an area 1.8 to 2.5 times the area required for two IGFs of the same channel type.

This is because this semiconductor is a single crystal, and is an unavoidable drawback. As a result, problems such as a latch-up phenomenon have occurred.

However, if a non-single-crystal semiconductor containing amorphous silicon is used instead of this single-crystal semiconductor as a semiconductor, such isolation becomes virtually unnecessary, and the launch-up phenomenon does not theoretically exist, so it is possible to change this concept. The inventor has discovered that this can be done.

The present invention relates to a non-single crystal semiconductor,
(Because it is a stacked vertical channel, it is called IGF here to distinguish it from MOS and FET devices used in conventional horizontal channel single crystal semiconductors.) 93)) It was possible to obtain a C/IGF by providing paired IGFs in two stacked bodies having different channel types, respectively.

That is, in a non-single crystal semiconductor, if the thickness is 10 times or more than the thickness of the formed semiconductor film, it can be completely treated as an insulator. That is, if the thicknesses of P, I, and N are 0.1 μ, 1 μ, and 0.1 μ, respectively, the width is 1 μ,
If the thickness is 10μ or 1μ or more, it can be substantially treated as an insulator.

Therefore, in the present invention, it was possible to provide a C/IGF with a small cell area, which is completely different from that of a C/MOS, using a conventional single crystal semiconductor.

The present invention is characterized by configuring two IGFs as a pair in the same laminate to reduce the area required for isolation and IGF wiring. That is, compared to single-crystal C/MOS, no particular area is required for isolation. Furthermore, by making it a vertical channel type,
The fourth semiconductor, which constitutes the channel formation region, is a non-single crystal semiconductor whose main component is silicon doped with hydrogen or fluorine. Furthermore, it is a non-single-crystal semiconductor and has the disadvantage of having lower carrier mobility than single-crystal semiconductors. Therefore, the present invention makes the film thickness of the second semiconductor or insulator 1μ or less, and as a result, the channel formed in the fourth semiconductor is a short channel, and the I
It has a cant-off frequency higher than that of OMIIZ.

In this way, by combining the present invention based on the 8J specifications, it was possible to create a circuit that could be applied to peripheral circuits of solid-state display devices for flat-screen TVs that replace cathode ray tubes.

FIGS. 2 and 3 show the manufacturing process of a vertical cross-sectional view of a stacked IGF for carrying out the present invention.

This drawing shows PIGF (53), (54) and NIGF.
A production example is shown in which two IGFs (51) and (52) are each made into one laminate.
This figure shows four examples of an inverter, NIGF, and PIGF in which F (53) and NIGF (52) are connected in series.It is also possible to fabricate the same process to further improve the degree of integration.

In FIG. 2(A), tin oxide + TxS is deposited on an insulating substrate (1) of quartz glass or borosilicate glass.
A first conductive film (2) such as T, J+Cr, etc. was provided as a lower electrode and lead. In this embodiment, a conductive film containing Cr as a main component is formed to a thickness of 0.2 μm. Selective etching was performed on this using the first mask (3). Furthermore, on this upper surface, a first non-single crystal semiconductor having a conductivity type of P or N type (herein referred to as P type) (3) (hereinafter referred to as Ni s1)
100 to 3000 people were formed by the known PCVCO method. Thereafter, a semiconductor (3) was selectively formed on the PIGF region (1o) using a photoresist (71 nm) and a second mask (2).

Furthermore, 200 to 10 N-type non-single crystal semiconductor (3#)
Area (10') and resist to 00 thickness (71')
In the 0 drawing produced above, the P-type semiconductor (3) is 5ixC
+-x (0<x<1, e.g. x=0.1), and an N-type semiconductor (3°> is a microcrystalline semiconductor. After this, the semiconductor (
3') was dissolved away using ultrasonic waves. Then, the N-type flat conductor on this resist was also lifted off at the same time and could be removed. Thus, Figure 2 (
As shown in C), the first semiconductors (3) and (3'), a P-type semiconductor (3) and an N-type semiconductor (3), are placed on the first electrode (2) in substantially the same plane. That is, by selectively etching one photoresist once and then using it as a lift-off resist, a P-type semiconductor region (3) was formed on the entire surface of the base (1) or the electrode thereon. Furthermore, since these respective semiconductors are not in close contact with each other, there is no mixing of N-type impurities into the P-type semiconductor layer or vice versa, and each It was possible to use P and N as semiconductors.

Furthermore, a second semiconductor or insulator (4) (hereinafter simply S
2 (Xo, 3-3μ) was laminated by the pCvo method.

Here, SI, N4-, (0≦X≦4) were set. m
''When x=Q, it becomes an insulator, and when 0<x≦4, it becomes a semiconductor or a semi-I@edge body. Further, a P-type semiconductor (5) and an N-type semiconductor (5') were formed again to a thickness of 200 to 1000 nm, and a similar lift-off process was performed using a third mask (2).

Thus, the third semiconductor having the same conductivity type as the first semiconductor (,5>,<5') (hereinafter referred to as D83)<
200 people ~ 0.2 μ) stacked (stack, called S)
Figure 2 (C) was obtained. and the third semiconductor (s3)
Also, a P-type semiconductor (5) and an N-type semiconductor (5') could be selectively formed on the same plane. In this stacked structure, region (10) has a PIF structure (in the summer, it is an insulator or an intrinsic semiconductor)
and the region (10') had a NIN junction.

In FIG. 3(A), the upper surface of the semiconductor (5), <5' is ITO (Indium tin oxide-containing MoS I, +
T r S ia + WSI, + A second conductor made of heat-resistant metal such as W, Ti, Mo, etc.
A laminate (50) of the conductors.

An unnecessary portion for providing (50') was removed using a fourth photomask (2).

In the drawing, the second conductor (6) was selectively removed in order to allow the PIGF (53), <54) to operate independently of each other in the same stacked structure.

Furthermore, the LP CVD method (low pressure vapor phase corporation PCVD
A silicon oxide film (7) with a thickness of 0.3 to 1 μm was formed by a method or a photo-CVD method. In the case of the PCVD method, the reaction between NLo and StH+ was carried out at 250°C.

The N and P layers of the first and third semiconductors are N"N or P"
It was effective to lower the contact resistance between P or N and the eleventh second electrode by using N"NINN" as P and P"PIPP+ (I is an insulator or an intrinsic semiconductor).

In this way, the first conductor, the first semiconductor, and the second
The semiconductor or insulator, the third semiconductor, and the second conductor were formed into layers.

Next, as shown in Figure 3 (B), using a mask
was removed by selective etching to form two laminates (50
), (50ゝ) were formed. That is, "laminate (56).

The respective insulators (17) and (27) in (50')
) second conductor (16), <26) 51. S2. S3 were formed to have substantially the same shape as each other. All of these were performed using an anisotropic plasma vapor phase etching method using microwaves (2.45 Gll!) using the same mask (2). The etch gas is C
A mixed gas of liver or liver + OL was used. The pressure is 0.
1-0.5 torr output 200- as edge speed 2
00 people/minute.

The laminate (50) serving as a hideout is composed of Sl (P), S2 (
]).

53 (P), and the other laminate (50') is Sl (
N), 52 (1), and S3 (N).

After this, the laminate (50') for these N-channel IGFs is
That is, the first conductors (12), (1
2'), 5l (13), <13'), S2 (14),
S3 (15), (15'), second conductor (16) and laminate (50) for P-channel IGF, ie block (
10) first conductor (22>, <22') Sl
(23), (23'), S2 (24), S3 (25
), <25'), the second conductor (26), <26), and an intrinsic or P- or N-type non-single crystal semiconductor that forms a channel formation region is stacked as a fourth semiconductor (35). I let it happen. This fourth semiconductor (35) is deposited on the substrate by silane glow discharge method (PCVD method), photo CVD method, L
Using the T CVD method (also called HOMOCVD method), the temperature range from room temperature to 500°C, for example, 25
It was provided under the conditions of 0°C, 0.1 torr, 3011, 13.56 MHz, and uses a non-single crystal silicon semiconductor with an amorphous, semi-amorphous, or polycrystalline structure. There is. The present invention focuses on amorphous or semi-amorphous silicon semiconductors doped with hydrogen or fluorine.

Furthermore, a silicon nitride film (34) is coated on the top surface in the same reactor without exposing the fourth semiconductor surface to the atmosphere.
Silane (disilane is also acceptable) and ammonia are produced by a gas phase reaction using mercury excitation using the VD method, and the thickness is 300-2.
000 people.

This insulating film may be immersed in a nitrogen or ammonia atmosphere activated by electromagnetic energy at a frequency of 13.56 MHz to 2.45 Gllz at 100 to 400° C. to form silicon nitride in a solid-vapor phase reaction.

Alternatively, silicon nitride may be formed by a PCVD method.

Then, around the 52 ('14), <24) side, it was possible to configure the channel forming region (9') (9) and the gate insulator (34) thereon. Fourth semiconductor (35
) forms a diode junction with Sl and S3.

This fourth semiconductor (35> (for example, P-type silicon) and gate insulator (34) are first provided only for the regions (52) and (53), and then a silicon oxide mask is applied to the regions (
10) Layering another fourth semiconductor (for example, N-type silicon) and an insulator to create a semiconductor doped with a trace amount of P or N-type impurity suitable for each region is a method for forming a single semiconductor layer. Although the mask increases, it is effective in controlling the threshold voltage.

In FIG. 3(B), an electrode hole is further formed using a sixth mask (3), and then a second conductive film (30) is formed covering the silicon nitride film (34) of the gate insulator on this stacked structure. 0
．． It was formed to a thickness of 3 to 1 μm.

This conductive film (30) is a transparent conductive film such as ITO (indium tin oxide), TiSi, Mo5t,
JSiL.

A heat-resistant conductive film such as W or Ti+Mo may be used. Here, a silicon semiconductor doped with a large amount of N-type impurities is
Made using the VD method. That is, 1% phosphorus in a thickness of 0.4 μ
A microcrystalline (particle size: 50 to 300 particles) non-single-crystalline semiconductor was fabricated by the PCVD method.

After that, a resist (3
8), (38'), (38 were formed.

Furthermore, as shown in FIG. 3(C), anisotropic etching in the vertical direction was performed using the seventh photolithography technique (2) in the same manner as in the fifth photolithography. That is, for example, a reactive gas such as CFLCl, CP, +OL, IIF, etc. was turned into plasma using microwaves, and this plasma was further applied from above the substrate. Then, the conductor (30) becomes
When etching a flat surface (top surface) with a thickness of 0.4μ,
This coating is removed, but on the sides it has 2-3 μ of the sum of the thickness of the laminate and the thickness of the coating in the vertical direction. Therefore, when anisotropic etching is performed in the vertical direction as shown in the drawing, these conductors are masked (3B) as shown by broken lines (39) and (39').

(It was possible to leave it in areas other than the area where 38H> is located.

As a result, as shown in Fig. 3(C), the laminate (10)
, <10') could be selectively provided with the Dito electrode residue (39), <39'). The present invention converts this residue into gay 1 to electrodes (40>, <41)
, <42), <43) and do not exist above the second semiconductor (16>, (26)), and as a result, the parasitic capacitance between the second semiconductor and the gate electrode is substantially eliminated. could be made equal.

In the drawing, among the conductors around the side of the laminate (50), <50'), the gate electrode and its lead F (40) to
The conductors on the other side except (43) were removed by horizontal vapor phase etching using an eighth photomask (2), and each dito was operated independently.

Thus, Figure 3(C) was obtained.

The plan view of FIG. 4(A), which is a longitudinal cross-sectional view centered on A-A', is shown as FIG. 3(A), and its electrical equivalent circuit is clearly shown in FIG. 4(B). etc. < (5
3), <54) is PIGF, (51), (52)! The 0 numbers of NIGF correspond to those shown in FIG. 3(C).

As is clear from FIGS. 4(A) and 3(B) and FIG. 3(C), IGFs of different conductivity types in two blocks can be connected to each other to form a C/IGF. Here, there are four IGFs (51) to (54),
Each channel has two paired channels (9), <9') and four. and I G F (52), (53)
Therefore, it was possible to configure it as an inverter. Therefore, the gate electrodes (41) and (42) are connected to each other as an input (63), and the first conductor is shared with each other as an output (63).
64).

The drain voltages v, e are connected to (62), and V, , are connected to (65). What is important here is that even if there are two IGFs in one pro-tsuku, they can be handled independently. , if they are separated by 10 μ or more, they can similarly operate independently.Furthermore, even if the gate electrode (63) crosses over the two laminates 33, the IGF will not function due to the lateral insulation characteristic of non-single crystals. (52),
<53) does not promote the generation of parasitic capacitance.

In addition, since the lower electrode is not installed in the region (72), even if the channel is turned on by the gate (63), the upper second conductor (62) (65) and the first The conductor (64) is electrically insulated. That is,
The IGF of the present invention utilizes the characteristic of non-single crystal silicon that due to the presence of the isolation region (72), isolation by a diode as shown in FIG. 1 is unnecessary.

That is, in the C/IGF of the present invention, the first conductor is covered with a semiconductor (Sl-S4) and a lateral isolation region (72) of about 10 μ or more is provided with the first conductor, thereby preventing crosstalk. , the leak can be removed. This is an important design rule when converting to an IC.

That is, in the drawing, two IGFs (51), <52) and (53), <54) can be provided as a pair. This is because the semiconductor or insulator between the two IGF channels is insulating, and the width of 10μ or more is Sl,
This is because if S2゜83 has a resistance of several tens of MΩ, it can be configured virtually independently, and by utilizing this property, it is possible to have a vertical channel type structure that is completely different from that of a crystalline semiconductor. did it.

The fourth semiconductor (30) of the present invention uses a non-single-crystal semiconductor containing amorphous silicon, uses hydrogen to neutralize dangling bonds in the semiconductor, and forms a gate without exposing its surface to the atmosphere. Making insulators. Furthermore, the photoresist is not brought into contact with the fourth semiconductor during the process, so there is no characteristic deterioration.
Alternatively, N17) Sl and S3 have another feature in that they have sufficient diode characteristics, so there are no manufacturing difficulties.

Regarding the application of the IGF of the present invention, since the electron mobility is 5 to 30 times that of holes, this C/
It is preferable to use IGF in one part and to operate the other part as an N-channel type.

For example, transistors for picture elements in a matrix configuration in flat displays (solid state display word W) are NIG
F, the peripheral part is a decoder, and the driver is C/IG
A typical application of F is to improve its operating characteristics and reduce its power consumption.

In this invention, the channel length is S2 (14), <2
It is determined by the thickness of 4), and is generally 0.1 to 3μ, and here it is set to 1.0μ. Due to such a short channel, the mobility of a non-single crystal semiconductor (25) is 115 to 1/10 that of a single crystal.
Despite the fact that it is 0L, the dual transistors have a cutoff frequency characteristic of 10M11z or more.

Thus, as a C/IGF inverter, j = 10V
It was possible to obtain V6%-10V and an operating frequency of 17.6M11z.

Also, reverse leakage is caused by Sl or 5 as shown in Figure 1.
34SixCz (0<K<1 For example x=o,
2, s2 is further changed to Si3 Na3
(0≦X≦4) or by converting it into an insulator as 5ixCpe (0x≦1), this 51.53 impurity can be
2, and the leakage of this N-1 junction or P-■ junction is 10n even if 1ov is added in the opposite direction.
It was below A/cd. This is 2 to 3 orders of magnitude lower than the reverse leakage of single crystals, which is preferable because physical properties specific to non-single crystal semiconductors are actively utilized. Furthermore, in operation at high temperatures, the metal of the electrode is non-single crystal 8
1, s3 tends to be mixed in and cause defects, so the side close to this electrode is 5ixC:1-x (0<x<1 e.g. x
= 0.2), and as a result, even after 1000 hours of operation at 150°C, no malfunction was observed after evaluating 1000 elements. Or if S3 is formed, 150℃
Considering that it can last for less than 10 hours, this is an extremely high improvement in reliability.

In the above description, the fourth semiconductor was used as the channel formation region. However, it is also possible to use non-monocrystalline silicon to which hydrogen is added as the second semiconductor, and to use the side surface portion thereof as the channel forming region. J81, the gate insulator is the first. ff12 and the third semiconductor on the side surface of the third semiconductor.
It was produced in the same manner as shown in the figure. And one area (10)
A PIF junction is configured in the region, and the other region (10') is NfN.
C/IGF was made by joining.

This structure has the advantage that the number of steps for stacking the fourth semiconductor is reduced. However, since the surface of the second semiconductor comes into contact with the atmosphere due to the etching of the fifth mask, there are many recombination centers at the interface, resulting in a frequency characteristic of 3 to 4M.
The number has dropped by 112.

As described above, since the present invention is a stacked type IGIi, multiple C/IGFs can be formed on a substrate, especially an insulating substrate, without using high-precision photolithography technology as in the past.
It became possible to create. As an application of this technology, it has become possible to use lead layers in image sensors and liquid crystal displays.

The non-single crystal semiconductor in the present invention is silicon, germanium or silicon carbide (SixC1-XO<x<1)
.

Silicon carbide or silicon nitride was used as the insulator.

[Brief explanation of drawings]

FIG. 1 shows a conventional complementary insulated gate semiconductor device. FIGS. 2 and 3 are longitudinal sectional views showing the steps of the complementary stacked insulated gate type semiconductor device of the present invention. FIG. 4 shows a plan view and an 1iiiIIU path of the stacked kf3 edge gate type semiconductor having the structure of the present invention. Patent applicant No Oゝ 10 N20 4 RiO/

Claims (1)

[Claims] 1. A P-type first semiconductor on a first electrode of a conductor on a substrate, a second semiconductor or insulator, a P-type third semiconductor, and a second electrode of a conductor. a first stacked body stacked in substantially the same shape; a fourth semiconductor is provided adjacent to the side of the stacked body to form a channel formation region; and a gate insulating film on the fourth semiconductor A first P-channel type insulated gate type semiconductor device in which a Dito electrode is disposed on a side surface of the stacked body adjacent to the gate insulating film; a second laminate in which a first semiconductor, a second semiconductor or insulator, an N-type third semiconductor, and a conductor second electrode are stacked in approximately the same shape, and adjacent to the side of the laminate. A fourth semiconductor is provided to constitute a channel forming region, and a gate insulating film on the fourth semiconductor and a gate electrode adjacent to the gate insulating film are disposed on a side surface of the stacked body. 1. An insulated gate semiconductor device comprising: two N-channel insulated gate semiconductor devices. 2. A P-type first semiconductor, a second semiconductor, a P-type third semiconductor, and a conductor second electrode on a first electrode of a conductor on a substrate are laminated in approximately the same shape. 1, a channel forming region is provided on the side surface of the second semiconductor, a gate insulating film on the second semiconductor and a gate 1 adjacent to the gate insulating film. a first P-channel type insulated gate type semiconductor device disposed on the side surface of the laminate; an N-type ff5I semiconductor on a first electrode of a conductor on the substrate; a second semiconductor; It has a second laminate in which a third semiconductor and a second electrode of a conductor are laminated in approximately the same shape, and a channel formation region is formed on a side surface portion of the second semiconductor; A second N-channel type insulated gate type semiconductor device comprising a gate insulating film on a second semiconductor and a gate electrode disposed on a side surface of the stacked body adjacent to the gate insulating film. An insulated gate type semiconductor device. 3. In claim 1 or 2,
and a second insulated gate field effect semiconductor device, wherein at least one of the first electrode and the second electrode is connected by a common conductor. 4. In claim 1, the second semiconductor or insulator is 5i7N4-i (0≦X≦4)) or 5i
An insulated gate semiconductor device characterized by having xC+-x (0≦x<1) as a main component. 5. In claim 1, the second semiconductor 1-
Marshal...Rin is Si) N4-((0<x≦4)) or 5i
An insulated gate semiconductor device characterized by having xC1z (0<x≦1) as a main component.