JPS609163A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS609163A JPS609163A JP11732183A JP11732183A JPS609163A JP S609163 A JPS609163 A JP S609163A JP 11732183 A JP11732183 A JP 11732183A JP 11732183 A JP11732183 A JP 11732183A JP S609163 A JPS609163 A JP S609163A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- collector
- windows
- emitter
- bored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- -1 arsenic ions Chemical class 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法、詳しくは従来特に１工
程を必要としたコレクタコンタクト窓開き工程を省略し
集積度の高いバイポーラトランジスタを製造子る方法に
関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a bipolar transistor with a high degree of integration by omitting the step of opening a collector contact window, which conventionally required one step. Regarding how to
（２）技術の背景
バイポーラトランジスタを厚い酸化膜に囲まれた領域に
形成する方法が開発され、かかる構造は酸化膜で囲んだ
トランジスタ（Ｏｘｉｄｅ ５ｕｒｒｏｕｎｄｅｄＴｒ
ａｎｓｉｓｔｏｒ −Ｏ５Ｔ ）構造と呼称される。(2) Background of the technology A method of forming a bipolar transistor in a region surrounded by a thick oxide film has been developed, and such a structure is called an oxide film surrounded transistor (Oxide 5urroundedTr
Ansistor-O5T) structure.
かかる構造のトランジスタは第１図に断面図で示され、
同図において、１はＰ型シリコン基板、２はＮ＋型埋没
層、３はＮ型エピタキシャル層、４は厚さ１．０μｍの
比較的に厚い酸化膜、５は化学気相成長法（ＣＶＤ法）
で形成された二酸化シリコン（５ｉ０２ ） 膜、６は
Ｎ＋型コレククコンタクト層、７はベース領域、８はエ
ミッタ領域を示す。A transistor having such a structure is shown in cross-section in FIG.
In the figure, 1 is a P-type silicon substrate, 2 is an N+ type buried layer, 3 is an N-type epitaxial layer, 4 is a relatively thick oxide film with a thickness of 1.0 μm, and 5 is a chemical vapor deposition method (CVD method). )
6 is an N+ type collector contact layer, 7 is a base region, and 8 is an emitter region.
（３）従来技術と問題点
コレクタコンタクト６は、コレクタ電極とＮ＋埋没層２
との間のエピタキシャル層３の厚さをもった部分の抵抗
値を減少する目的で高濃度のＮ型不純物をベース領域７
の形成前に拡散して形成され、かかる不純物拡散層を設
けることによってエピタキシャル層の部分の高抵抗は軽
減される。しかし、コレクタコンタクト６の形成のため
には特に１工程が必要であり、またそれば図に見て中央
の酸化膜４のベース領域７の外側の領域に形成されるの
で、バイポーラトランジスタの集積度を高めるについて
障害となっている。(3) Conventional technology and problems The collector contact 6 consists of the collector electrode and the N+ buried layer 2.
A high concentration of N-type impurity is added to the base region 7 in order to reduce the resistance value of the thick portion of the epitaxial layer 3 between the base region 7 and the base region 7.
By providing such an impurity diffusion layer, the high resistance of the epitaxial layer portion is reduced. However, one step in particular is required for the formation of the collector contact 6, and since it is formed in the area outside the base region 7 of the central oxide film 4 as seen in the figure, the integration of the bipolar transistor is This poses an obstacle to increasing the quality of life.
（４）発明の目的
本発明は上記従来の問題点に鑑み、バイポーラトランジ
スタの製造において、コレクタコンタクトの抵抗を減少
すると同時に製造される半導体装置の集積度を高める方
法を提供することを目的とする。(4) Purpose of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a method for reducing the resistance of the collector contact and simultaneously increasing the degree of integration of the manufactured semiconductor device in the manufacture of bipolar transistors. .
（５）発明の構成
そしてこの目的は本発明によれば、埋没拡散層が設けら
れた半導体基板に形成した酸化膜で囲まれる領域にバイ
ポーラトランジスタを製造する方法において、ベース領
域を形成し全面に絶縁膜を形成した後に、ベース電極と
エミッタ電極の窓開けと同時に前記酸化膜にコレクタ電
極の窓開けをナシ、エミッタ拡散と同時にコレクタコン
タクト拡散をなすことを特徴とする半導体装置の製造方
法を提供することによって達成される。(5) Structure and object of the invention According to the present invention, in a method for manufacturing a bipolar transistor in a region surrounded by an oxide film formed on a semiconductor substrate provided with a buried diffusion layer, a base region is formed and the entire surface is Provided is a method for manufacturing a semiconductor device, characterized in that after forming an insulating film, a collector electrode is not opened in the oxide film at the same time as a window is opened for a base electrode and an emitter electrode, and collector contact diffusion is performed at the same time as emitter diffusion. This is achieved by
（６）発明の実施例 以下本発明実施例を図面によって詳説する。(6) Examples of the invention Embodiments of the present invention will be explained in detail below with reference to the drawings.
本願発明者は第２図（ａｌの平面図と同図Ｂ−Ｂ線に沿
う断面図である第２図（ｂ）に示される構造のバイポー
ラトランジスタに示される如く、酸化膜４に窓開きして
、エピタキシャル層の薄い部分にコレクタコンタクト拡
散領域を形成することを考えた。なお第２図以下におい
て、既に図示した部分と同じ部分は同じ符号を付して示
す。酸化膜４の形成においては、エピタキシャル層３ば
その深さ方向にも半分程度酸化ささるので、酸化膜４の
下方ではエピタキシャル層３の厚さく深さ）はベース領
域の部分よりも小になっており、その分だけ抵抗値が小
になる。ここに高濃度の不純物拡散領域を作ると、コレ
クタとＮ＋型埋没層２との間の抵抗−ばかなり低減され
ることになる。The inventor of the present application has developed a bipolar transistor having a structure shown in FIG. 2(b), which is a plan view of FIG. Therefore, we considered forming a collector contact diffusion region in a thin part of the epitaxial layer.In Figure 2 and below, the same parts as those already shown are given the same reference numerals.In the formation of the oxide film 4, Since the epitaxial layer 3 is also oxidized by about half in the depth direction, the thickness and depth of the epitaxial layer 3 below the oxide film 4 is smaller than that of the base region, and the resistance is correspondingly smaller. value becomes small. If a high concentration impurity diffusion region is formed here, the resistance between the collector and the N+ type buried layer 2 will be considerably reduced.
他方、従来絶縁層としてのみ利用された酸化膜４に窓開
きをしてコレクタコンタクトを形成するのであるから・
第１図と第２図Ｆ１（ｌとの対比がら明らかなように、
バイポーラトランジスタの集積度が高められることにな
る。On the other hand, since the collector contact is formed by opening a window in the oxide film 4, which was conventionally used only as an insulating layer.
As is clear from the comparison between Figure 1 and Figure 2 F1(l),
The degree of integration of bipolar transistors will be increased.
以下第３図を参照して第２図のバイポーラトランジスタ
の製造工程を説明する。The manufacturing process of the bipolar transistor shown in FIG. 2 will be explained below with reference to FIG.
通常の技術を用い、Ｐ型車結晶シリコン基板の拡散によ
ってＮ゛型埋没Ｎ２を形成し、エピタキシャル成長によ
ってＮ型のエピタキシャル層を成長する。このときの状
態は第３図＋ａｌに示される。Using conventional techniques, an N-type buried N2 is formed by diffusion in a P-type wheel crystal silicon substrate, and an N-type epitaxial layer is grown by epitaxial growth. The state at this time is shown in FIG. 3+al.
次いで窒化膜（Ｓｔ３Ｎｇ膜） １０を成長し、それを
バターニングして酸“化膜を形成ずべき部分を窓開きす
る（第３図（ｂ））。この工程で、第２図に符号９で示
す部分には窒化膜を残しておく。Next, a nitride film (St3Ng film) 10 is grown, and it is buttered to open windows in the areas where the oxide film should be formed (FIG. 3(b)). The nitride film is left in the area indicated by .
続いてフィールド酸化によって窒化膜１０で窓開きした
部分のシリコンを酸化し酸化膜４を形成する。この段階
で分離（アイソレーション）拡散をなすために窓開きを
なし、例えばホウ素をイオン注入法で注入し、アニール
してアイソレーション層１１を作る。次に窒化ｎ＊ｉｏ
を除去し、ベース領域表面を酸化し、例えばホウ素のイ
オン注入法による注入とアニールとによってベース領域
７を形成する。Subsequently, the silicon in the windowed portion of the nitride film 10 is oxidized by field oxidation to form an oxide film 4. At this stage, a window is opened to perform isolation diffusion, and boron, for example, is implanted by ion implantation and annealed to form the isolation layer 11. Next, nitride n*io
is removed, the surface of the base region is oxidized, and a base region 7 is formed by, for example, boron ion implantation and annealing.
次いで全面にＣＶＤ法で５ｉ０２膜５を成長する（第３
図（Ｃ））。Next, a 5i02 film 5 is grown on the entire surface by CVD method (third
Figure (C)).
次いで異方性のドライエンチングで電極窓開きをなす、
すなわちベース電極Ｂ、エミッタ電極Ｅ、コレクタ電極
窓Ｃの窓開きをなす。このとき形成されたエミッタ電極
窓Ｅとコレクタ電極窓℃は拡散窓として用いる。従来技
術によると、コレクタコンタクト窓の窓開きのためには
１つの工程が別に必要であったが、本発明の方法による
と、ベース電極、エミッタ電極窓と同時にコレクタ電極
窓が窓開きされるのである。Next, the electrode window is opened by anisotropic dry etching.
That is, the base electrode B, the emitter electrode E, and the collector electrode window C are opened. The emitter electrode window E and the collector electrode window C formed at this time are used as a diffusion window. According to the prior art, one separate step was required to open the collector contact window, but according to the method of the present invention, the collector electrode window is opened at the same time as the base electrode and emitter electrode windows. be.
次いで、全面にレジスト膜１２を形成し、それをベース
電極窓をかくす如くにバターニングし、エミッタ電極と
コレクタ電極の窓Ｅ、Ｃを通して例えば砒素（Ａｓ”）
をイオン注入法で注入し、アニールして、エミッタ領域
８とコレクタコンタクト層６を形成する（第３図（ｄ）
）。この点も本発明の方法の特徴であって、従来コレク
タコンタクト層はベース形成前に作られ、そのための工
程が別に必要であったものである。引続き全面にアルミ
ニラムを蒸着し、電極バターニングを行う。Next, a resist film 12 is formed on the entire surface, and it is buttered so as to hide the base electrode window, and arsenic (As"), for example, is applied through the emitter electrode and collector electrode windows E and C.
is implanted by an ion implantation method and annealed to form an emitter region 8 and a collector contact layer 6 (FIG. 3(d)).
). This point is also a feature of the method of the present invention; conventionally, the collector contact layer was formed before the base was formed, and a separate process was required for this purpose. Next, aluminum laminate is deposited on the entire surface and electrode patterning is performed.
部分９（第２図（ａ））には酸化膜４の形成のための窒
化膜バターニングのときに窒化膜を残しておいた。従っ
てこの部分では酸化膜４のような厚い酸化膜は形成され
ない。その結果、ベース電極、エミッタ電極、コレクタ
電極１４Ｂ 、１４Ｅ、１４Ｇが形成されたとき、コレ
クタ電極窓Ｃは第３図＋ｄ）に示されるように深く形成
されていても、部分９で段差ができているの′で、ＡＡ
配線を第２図ｔａ＋に示す如くに引き出すと、ｉ配線の
良好な密着性（ｃｏｖｅｒａｇｅ）が得られる。A nitride film was left in the portion 9 (FIG. 2(a)) during the nitride film buttering for forming the oxide film 4. Therefore, a thick oxide film like oxide film 4 is not formed in this portion. As a result, when the base electrode, emitter electrode, and collector electrodes 14B, 14E, and 14G are formed, even if the collector electrode window C is formed deeply as shown in FIG. AA
If the wiring is pulled out as shown in FIG. 2 ta+, good coverage of the i wiring can be obtained.
（７）発明の効果
以上詳細に説明した如（、本発明によれば、バイポーラ
トランジスタの製造においてコレクタコンタクト層形成
のため特に工程を必要としないので、従来技術に比ベニ
程数を減らすことになって製造歩留りを向上し、また厚
い酸化膜４にコレクタ窓が形成されるので、半導体装置
の集積度を高めるに効果大である。(7) Effects of the Invention As explained in detail above (according to the present invention, no special process is required for forming the collector contact layer in the production of bipolar transistors, the number of bending coefficients can be reduced compared to the conventional technology). This improves the manufacturing yield, and since the collector window is formed in the thick oxide film 4, it is highly effective in increasing the degree of integration of the semiconductor device.
第１図は従来技術により作られたバイポーラトランジス
タの断面図、第２図（ａｌと（ｂ）ば本発明の方法によ
り作られるバイポーラトランジスタの平面図と断面図、
第３図は本発明の方法を実施する工程におけるバイポー
ラトランジスタの要部の断面図である。
ｉ−ｐ型シリコン基板、２−Ｎ＋型
埋没層、３工ピタキシヤル層、４．５−酸化膜、６−・
−コレクタコンタクト層、７−ベース領域、８−エミッ
タ領域、
９−酸化膜の薄い部分、１〇−窒化膜、１１− アイソ
レーション層、１２・−レジスト膜第１図
（ａ ｊ
第２図
（ａ）
第３図FIG. 1 is a cross-sectional view of a bipolar transistor made by the conventional technique, and FIG.
FIG. 3 is a cross-sectional view of a main part of a bipolar transistor in a step of carrying out the method of the present invention. ip type silicon substrate, 2-N+ type buried layer, 3-layer pitaxial layer, 4.5- oxide film, 6-.
- Collector contact layer, 7 - Base region, 8 - Emitter region, 9 - Thin part of oxide film, 10 - Nitride film, 11 - Isolation layer, 12 - Resist film Fig. 1 (a j Fig. 2 ( a) Figure 3
Claims (1)
囲まれる領域にバイポーラトランジスタを製造する方法
において、ベース領域を形成し全面に絶縁膜を形成した
後に、ベース電極とエミ・ツタ電極の窓開けと同時に前
記酸化膜にコレクタ電極の窓開けをなし、エミッタ拡散
と同時にコレクタコンタクト拡散をなすことを特徴とす
る半導体装置の製造方法。In a method for manufacturing a bipolar transistor in a region surrounded by an oxide film formed on a semiconductor substrate provided with a buried diffusion layer, after forming a base region and forming an insulating film on the entire surface, windows for the base electrode and emitter/vine electrode are formed. A method of manufacturing a semiconductor device, characterized in that a collector electrode window is opened in the oxide film at the same time as the opening, and collector contact diffusion is performed simultaneously with emitter diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11732183A JPS609163A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11732183A JPS609163A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS609163A true JPS609163A (en) | 1985-01-18 |
Family
ID=14708851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11732183A Pending JPS609163A (en) | 1983-06-29 | 1983-06-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2105298A1 (en) | 2008-03-28 | 2009-09-30 | Fujifilm Corporation | Negative-working lithographic printing plate precursor and method of lithographic printing using same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128941A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPS57162460A (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5856461A (en) * | 1981-09-30 | 1983-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1983
- 1983-06-29 JP JP11732183A patent/JPS609163A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57128941A (en) * | 1981-02-04 | 1982-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPS57162460A (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5856461A (en) * | 1981-09-30 | 1983-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2105298A1 (en) | 2008-03-28 | 2009-09-30 | Fujifilm Corporation | Negative-working lithographic printing plate precursor and method of lithographic printing using same |
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