JPS6086939A - Clock reproduction system - Google Patents

Abstract

PURPOSE:To attain reproduction of a prescribed clock despite the break of an input signal or the insertion of an excess pulse, by securing the synchronism between the differential output of a horizontal synchronizing signal and an AND circuit with the count value of reference clocks of 1-frame synchronism. CONSTITUTION:A horizontal synchronizing signal is supplied to an input terminal 8 and shaped into a differential waveform through a differentiating circuit 9. This shaped waveform is supplied to an AND gate 12. While the count value of 1-frame cycle is set to a counter 16 of a counter circuit 10 together with the count value K2 of a cycle longer than said 1-frame cycle. The reference clocks supplied through a reference clock terminal 19 are counted by the counter 16. This count value is supplied to an NAND gate 11 after the count value K1 is read out of an ROM17. In this case, the counter 16 delivers the value K2 if the gate 12 has no output and the counter 16 is not delivered. While the counter 16 counts up to the value K2 when no input exists at the terminal 8. Then the value K2 is read out of the ROM17, and the clock of the horizontal synchronizing signal is delivered through a gate.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method of regenerating a clock synchronized with an input clock, and in particular, when the input clock is cut off, a pseudo pulse is regenerated to replace a manual clock, or The present invention relates to a clock recovery method with less jitter that removes surplus clocks when they are generated.

Cb) Prior Art and Problems In conventional digital transmission, a phase synchronized oscillator is used as an example of extracting a clock from a digital signal.

An example of a configuration of a conventional clock extraction method will be described below with reference to the drawings. FIG. 1 shows a conventional phase-locked oscillator. In the figure, 1 is an input terminal into which a digital signal is input, a 2-digit phase comparison circuit, and 3 is a low-pass filter (hereinafter referred to as LPF).
, a four-digit voltage controlled oscillator, and 5 indicates an output terminal.

In FIG. 1, the clock frequency f. The phase comparison circuit 2 compares the phase of the digital signal clock I with the output clock of a voltage controlled oscillator (hereinafter referred to as vCO) 4, and the comparison component drives vC04 through an LPF, and the output clock is converted to a frequency fo. It is pulled into the digital signal clock and outputted from the output terminal 5.

Here, in order for the phase synchronized oscillator to follow clock I at high speed, the frequency bandwidth of LPF3 should be widened, and the LP
It is necessary to increase the rate of change in the oscillation frequency of vCO4 with respect to the change in the output voltage of F3.

However, if the input tarokku is interrupted in this way, the oscillation frequency of the VCO4 will run free at the upper or lower limit of the frequency band in which the VCO4 operates, and the phase synchronized oscillator will again operate at the different clock frequencies. Therefore, the clock fo' having jitter is outputted.
' has the disadvantage of erroneously determining the received data obtained from the digital signal. In addition, when extra pulses are inserted in the above method, there is a disadvantage of generating jitter in the clock.

(e) Object of the Invention In order to solve the above-mentioned drawbacks, it is an object of the present invention to provide a new lock regeneration method that regenerates a predetermined clock even when an input signal is interrupted or an excessive pulse is inserted.

(d) Structure of the Invention In order to achieve the above object, the present invention provides a clock regeneration method synchronized with an input clock, which includes means for removing surplus pulses of the input clock by a guard circuit,
The present invention is characterized in that it has means for detecting the interruption of the input clock, means for generating a pseudo pulse using the interruption detection signal, and means for replacing the pseudo pulse with the interruption of the clock.

(e) Embodiment of the Invention The outline of the clock recovery method of the present invention is shown in FIG. Reference numeral 6 indicates a clock circuit consisting of the DPL shown in FIG. 1, and reference numeral 7 indicates a pseudo pulse generation circuit according to the present invention.

In FIG. 2, when no input pulse is input to the input terminal I, the pseudo pulse generation circuit 7 generates an input clock in a pseudo manner, and when there is a surplus pulse in the input clock, it is removed. By inputting a normal human clock to the next stage clock circuit 6, a clock synchronized with the input clock is output from the output terminal 5.

Hereinafter, clock reproduction of the horizontal synchronization signal will be explained based on FIGS. 3 and 4.

FIG. 3 is a block diagram of an embodiment of a clock regeneration system using a pseudo pulse generation circuit according to the present invention. In the figure, 1.6.8 indicates the same components as in FIG. 1, 9 is a differential circuit, 10 is a counter circuit, 11 is a NAND circuit, 12.15 is an AND circuit, 13, 14° 18 is a flip-flop (hereinafter referred to as FF circuit), 16 is a counter, 17
indicates ROM.

FIG. 4 shows waveforms at points ① to ② in FIG. 3. In the figure, ■ is the horizontal synchronization number 41 of frame period IH, ■ is the differential waveform of ■,
■ is the output of the FF circuit 18, ■-1 is an extra pulse inserted outside the frame period IH, ■ is the waveform output from the other output terminal 18-1 of the FF circuit 18 when the synchronization signal is lost, (2) indicates a normal output clock, and (2) indicates an output clock based on a pseudo pulse.7 The operation of FIG. 3 will be explained using FIG. 4. In FIG. 3, the horizontal synchronizing signal input to the input terminal 8 is manually input to the FF circuits 13, 14 . The reference clock input to the input terminal 19 in FIG. The counter circuit 10 counts the reference clock in one frame period of the horizontal synchronizing signal. This count value is NAN
It is input to the D gate 11 and outputs the differential waveform (2).

The output differential waveform (2) passes through the input terminal 1, and the clock circuit 6 reproduces a clock synchronized with the horizontal synchronizing signal (2), and a portion of the output of the AND gate 12 resets the color/return signal (16).

In the above 6, the counter 16 of the counter circuit 10 is set to both 1 for the count value of one frame period and 2 for the count value of a period slightly longer than the one frame period, and is input from the reference clock terminal 17. The counter 16 counts one frame period of the horizontal synchronization signal from the reference clock, and reads 1 as the count value written in the ζ0M17, and the output is sent to the FF circuit 18 as a The latch output ki is input to the NAND gate 11. In this case, when there is no output from the AND gate 12 and the counter 16 is not reset, the counter 16 outputs a count value of 2.

When a horizontal synchronization signal is desired to be input, when no horizontal synchronization signal is input to the input terminal 8, the counter 16 starts counting the reference clock from the time of the previous horizontal synchronization signal, and the horizontal synchronization is performed. The count value of the period slightly longer than the 17th frame period of the signal is counted up to 2. The count value of 2 is read out from the count value written in the ROM 17, and the output is used as the FF circuit 18.
Latch.

This latch output is the second output terminal 18-1 of the FF circuit 18.
Therefore, the output waveform shown in Figure 4 ■ is output, and the waveform ■ is AN
The signal is input to the D gate 12, and the AND gate 12 outputs the horizontal synchronization clock (number 8) shown in FIG.

When an extra pulse is inserted within the horizontal synchronizing signal period As shown in Fig. 4 ■-1e, when an extra pulse is inserted within the horizontal synchronizing signal period, the differentiator 9 generates a differential corresponding to the waveform of ■-1. The waveform is output and input to the NAN gate 11. On the other hand, since the counter circuit 10 outputs an output corresponding to the count value of 1, the NAN gate 11 does not output the surplus pulse -1.

(f) Effects of the Invention According to the present invention, the horizontal synchronization signal is deleted or an extra clock is inserted, degrading the horizontal synchronization signal. It has the advantage that normal horizontal synchronization (g clock can be shaped) by synchronizing with the count value of the reference clock of one period using an AND circuit.

[Brief explanation of the drawing]

Figure 1 shows a conventional phase-locked oscillator, Figure 2 is a schematic diagram of the present invention, Figure 3 is a configuration diagram of an embodiment of the clock regeneration method of the present invention, and Figure 4 shows various waveforms used in Figure 3. 〜■ is shown. In the figure, 1, 8. iy, 5 is a terminal, 2 is a phase comparison circuit, 3
is LPF, 4 is VCO16 is DPLL (clock circuit)
, 7 is a pseudo pulse generation circuit, 9 is a differentiation circuit, 10 is a counter circuit, 11 is a NAND gate, 12゜15 is an AND
13, 14, 18 are FF circuits, 16 is a counter, 17 is a ROM, and 18-1 is an output terminal. Thousand 1 K Cow 2 Scream

Claims (1)

[Claims] In a clock regeneration method synchronized with an input clock, there is a means for removing surplus pulses of the input clock by a guard circuit, a means for detecting a disconnection of the input clock, and a pseudo pulse is generated by the disconnection detection signal. 1. A clock regeneration method, comprising means for replacing the pseudo pulse with the clock interruption.