JPH0583241A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To recover a clock by using a circuit extracting a preamble signal from a burst signal in an excellent way and an analog phase synchronization oscillator with low power consumption using only the preamble signal to recover an excellent clock signal phase-locked to a reception signal. CONSTITUTION:The circuit consists of a preamble extract circuit 1 extracting only a preamble signal from a reception burst signal and of a phase synchronization oscillator 2 generating a clock signal having a nominal frequency corresponding to the reception burst signal and phase-locked to the extracted preamble signal. Only the extracted preamble signal is inputted to the phase synchronization oscillator to synchronize the phase of an output clock signal with a phase of the reception burst signal to stop the input to the phase synchronization oscillator for a data signal reception period and a burst signal intermittent period thereby self-running the oscillator. The preamble extraction circuit 1 consists mainly of a monostable multivibrator 11 having a pulse width of a preamble period and of a retriggerable monostable multivibrator 12 outputting a signal to inhibit the operation of the monostable multivibrator at the reception of a data signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for producing a clock signal based on a received burst signal in an optical subscriber unit.

[0002]

2. Description of the Related Art An optical subscriber unit connects a station (OCU) and a subscriber (DSB) via a single optical transmission line, and transmits digital signals between a station and a subscriber and a subscriber and a station in a time division manner. Is a ping-pong transmission type transmission device that alternately performs a burst operation. In such a transmission system, the OCU transmits data in synchronization with the transmission clock generated from the in-station reference clock, and the DSU reproduces the transmission clock from the reception burst to create a clock signal in synchronization with the transmission clock and receives it. Used for reading data and synchronizing upstream bursts to the OCU. Also, in the OSU, each D with a different phase
In order to correctly identify the received data from the SU, it is necessary to recover the clock signal that is phase-locked with each received burst signal.

FIG. 3 is a diagram showing a burst signal targeted by the present invention. As shown in the figure, the transmission signal is a signal sent from the station side to the subscriber side (downstream frame) is a burst signal composed of a signal such as a preamble and the control information to the subscriber system unit (DSU) following it. The signal (uplink frame) to be transmitted from the subscriber side to the station is transmitted during the intermittent period of the burst cycle. The frame synchronization is generated by dividing the reference signal on the station side, and the cycle of the preamble or the like is also equal to the reference signal.

Conventionally, there is a method of using a metallic cable, which has a bit rate of several 100 Kb / s on the transmission line.
In addition, since the period of the preamble signal used for establishing synchronization at the beginning of the burst is relatively long, a clock recovery circuit using a digital PLO circuit can obtain a clock signal synchronized with the clock of the transmission side from the received burst. Was easy.

Recently, however, with the diversification of subscriber terminals, there is a strong demand for higher speed of the data rate transmitted and received on the subscriber line, and the increase of the transmission rate of the subscriber line and the ratio of the preamble period to the burst period. It has become desirable to shorten the period. Therefore, as shown in FIG. 3, the burst cycle has a bit rate of several tens Mb / s for 2.5 ms (that is, one burst is tens of thousands of bits), and the preamble signal is a burst signal of several to several tens of bits. A ping-pong transmission method via an optical transmission line is under study, and a clock recovery circuit capable of receiving this burst signal and reproducing a good clock signal is required.

As the synchronous system, a system using a phase-locked oscillator (PLO) is promising in terms of cost and size. However, in order to realize this, it is necessary for the PLO circuit provided in the device on the subscriber side to have an ultra-high-speed pull-in and also for synchronization by a burst signal rather than a normal continuous signal.

[0007]

In the conventional digital PLO used in the subscriber unit by the metallic transmission, there is a problem that the power consumption increases as the frequency increases and it is not suitable for integration into an integrated circuit. Therefore, when an analog PLO that can reduce power consumption even at high frequencies is used, there are the following problems. That is, in order to generate a clock signal that is phase-synchronized with the received burst with a preamble signal of at most several tens of bits, ultra-high-speed synchronization pull-in is required, and a VCO (voltage controlled oscillator) with a wide variable width is required. However, when a VCO having a wide variable width is used, the phase of the output signal of the VCO is shifted by the burst signal, a good clock cannot be obtained, and an error occurs in received data.

Therefore, a method of inputting only a preamble signal for establishing synchronization added to the beginning of a reception burst to a PLO (phase control oscillator) is studied, and in order to realize this, a good preamble extraction circuit and a short preamble extraction circuit are used. A phase-locked oscillator that can generate a clock signal that exactly matches the nominal frequency when the input signal is cut off is required.

The present invention has been made in view of these problems, and a circuit for satisfactorily extracting a preamble signal from a received burst signal, an excellent clock signal phase-synchronized with the received signal using only the preamble signal is provided. An object of the present invention is to provide a low power consumption analog type phase locked oscillator for reproducing and a clock reproducing circuit for reproducing a good clock from a received burst signal of high bit rate by using these.

[0010]

FIG. 1 is a block diagram of an embodiment of a clock recovery circuit of the present invention. In order to solve the above-mentioned problems, the clock recovery circuit of the present invention, as shown in FIG.
A clock recovery circuit for recovering a clock signal from a received burst signal composed of a preamble signal that repeats "1" and "0" in a transmission clock cycle and a data signal in which "1" and "0" randomly change in arbitrary bits. A preamble extraction circuit 1 for extracting only a preamble signal from the received burst signal, and a phase-locked oscillator 2 for generating a clock signal having a nominal frequency corresponding to the received burst signal in phase synchronization with the extracted preamble signal,
Only the extracted preamble signal is input to the phase-locked oscillator to synchronize the phase of the output clock signal with the received burst signal, and the input to the phase-locked oscillator is stopped during the data signal reception period and the burst signal intermittent period. The preamble extraction circuit 1 is configured to be self-propelled, and the preamble extraction circuit 1 is triggered by the first rising edge of the preamble signal and outputs a preamble detection signal having a time width substantially equal to the preamble duration 11.
And a retriggerable monostable multivibrator 12 that outputs a pulse corresponding to the burst period when the pulse width is set longer than the “0” continuous or “1” continuous period of the data signal and triggered at each falling edge of the input, Outputs of the two multivibrators 11 and 12 are input, and a first gate circuit 13 that outputs a pulse corresponding to a period from the end of the preamble to the first falling of the next preamble signal is output.
The output of the first gate circuit 13 and the output of the retriggerable monostable multivibrator 12 are input, a pulse corresponding to the data signal period is output, and the pulse is applied to the trigger inhibit input of the monostable multivibrator 11. A configuration is provided that includes second gate circuits 14 and 15 and a third gate circuit 16 that is controlled by the preamble detection detection signal and passes only the preamble signal. Further, the phase-locked oscillator 2 includes an input signal. Voltage-controlled oscillator when disconnected 24
Is configured to have an offset setting circuit 23 that gives an offset to the control voltage corresponding to the phase difference between the frequency-divided output of the voltage controlled oscillator 24 and the input signal so as to generate the output of the nominal frequency.

[0011]

The preamble extraction circuit 1 extracts only the preamble signal from the received burst signal and inputs it to the phase locked oscillator 2. The voltage-controlled oscillator 24 is controlled by the offset setting circuit 23 except when the preamble signal is input, and is controlled by the offset voltage so that the frequency pull-in that strictly corresponds to the reference clock on the station side is not necessary (the deviation is less than ppm). Is self-propelled. Then, only the phase of the oscillation output of the phase locked oscillator 24 is matched with the preamble signal by the preamble signal extracted from the reception burst. For this reason, it is possible to perform phase synchronization with the clock on the transmission side in a short preamble cycle of at most 10 bits. Therefore, even at high bit rates, analog P
The LO makes it possible to regenerate the clock, reduce power consumption, and supply a good synchronous clock to the optical subscriber unit of the high bit rate ping-pong transmission system.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of a clock recovery circuit of the present invention, and FIG. 2 is a time chart showing the operation of a preamble extraction circuit showing a transmission signal targeted by the clock recovery circuit of the present invention.

As shown in FIG. 3, the received burst signal targeted by the clock recovery circuit of the present invention has a burst period of 2.
It is repeated for 5 ms, the duration is slightly shorter than 1.25 ms, the bit rate is several tens of Mb / S, and the preamble signal in which "1" and "0" are alternately repeated in the first few bits (8 bits in the figure) of the burst. , And subsequently, the appearance of "1" and "0" consists of a data signal that randomly changes according to the data. It is assumed that the period of continuous "1" or continuous "0" of the data signal is limited to, for example, 60 bits or less.

In FIG. 1, the clock recovery circuit comprises a preamble extraction circuit 1 and a phase locked oscillator 2. As will be described later, the preamble extraction circuit 1 receives a received burst signal, passes only the preamble signal as it is and outputs it, and outputs a data signal period and a burst intermittent period (a period during which an upstream burst is transmitted from the DSU to the station side). ) Is a circuit that outputs “0”.

The phase-locked oscillator 2 comprises a phase comparator 21, a low frequency filter 22, an offset setting circuit 23, a voltage controlled crystal oscillator (VCXO) 24, and a frequency dividing circuit 25. The oscillation output of the VCXO 24 is divided by the frequency divider 6 into the phase comparator 21 by 1 / N (N
Is an integer), the preamble signal from the preamble extraction circuit 1 (alternately takes the value of "1" and "0" in the transmission clock cycle) is input during the preamble period. During this period, a pulse whose duty ratio changes according to the phase difference between both signals is output. When there is no phase difference between the two signals and they are completely in phase synchronization, or when only the comparison signal is input, the duty ratio of the pulse output by the phase comparator 21 is 50%, and the phase difference between the two signals is The duty ratio increases or decreases in proportion to the phase difference according to the positive or negative of. The output of the phase comparator 21 is integrated by the low-pass filter 22 to obtain an average voltage, which is input to the non-inverting input of the offset setting circuit 23 including an operational amplifier. An offset voltage Vo, which will be described later, is applied to the inverting input of the offset setting circuit 23, and a control voltage obtained by amplifying the difference between both inputs in a predetermined manner is applied to the VCXO 24 to control the oscillation frequency. This offset voltage Vo is preset so that the oscillation frequency of the VCXO 24 exactly matches the nominal frequency N times the input signal with an accuracy of several ppm when the output of the phase comparator 21 has a duty ratio of 50%. deep. The transmission clock is generated from the reference clock of the station, and the frequency is stable and always the same frequency. Therefore, the receiving side can use a highly stable VCXO24 with a small variable width using an ME element such as a crystal, and an offset. By adjusting the setting circuit, the oscillation frequency can be adjusted to the nominal frequency corresponding to the transmission clock with an accuracy of several PPM.

The operation of the clock recovery circuit configured as described above will be described. During the preamble period, the phase comparator 21
, The preamble signal is compared with the comparison signal, and the comparison result is converted into a control voltage by the low-pass filter and the offset setting circuit and applied to the VCXO24, and is corrected by the offset voltage until then, and the nominal value is N times the transmission clock. Change the frequency of the VCXO that was oscillating the frequency,
The phase of the oscillation output is controlled so as to match the phase of the preamble signal. Since the control sensitivity of the VCXO (the change of the oscillation frequency with respect to the change of the control voltage) is extremely high, the output signal of the VCXO24 is phase-synchronized with the received preamble signal by the change of the control voltage within the preamble period of several bits, and the original nominal frequency is restored. Return.

When the preamble period ends and the data signal period starts, the reception signal input to the phase comparator 21 does not change and "0" is continuously input. Therefore, the phase comparator 21
Output becomes duty 50%, and the offset setting circuit 23
Causes a constant control voltage offset by a predetermined value to be applied to the VCXO, and the VCXO 25 continues to generate a clock signal N times the reception bit rate in phase with the transmission clock.

Next, the configuration and operation of the preamble extraction circuit 1 will be described with reference to FIG. Note that FIG. 2 shows the circles in FIG.
The waveform at the numeral position is shown. In FIG. 3, 11 is a monostable multivibrator, 12 is a retriggerable monostable multivibrator, 13 and 14 are NAND gates, 15 is an inverter, and 16 is an AND gate. When the A input is "L", the monostable multivibrator 12 is triggered by the rising edge of the B input, the output Q becomes "H", and continuously outputs "H" with a preset time width τ _1. Then return to "L". In addition, A
When the input is "H", the above trigger is not applied and the output Q is
It remains "L". Therefore, a period corresponding to the number of bits of the preamble is set as this time width τ ₁ , and A
The received burst signal is input to the input, and the output of the inverter 15 described later is input to the B input. The retriggerable monostable multivibrator 12 is triggered by the falling edge of the A input, the Q output becomes "H", and the preset time width τ ₂ is "H".
Generate a pulse. Then, if the A input falls again during the output "H", it will be retriggered by this,
The output pulse width is redefined from the retrigger. This pulse width τ ₂ is set to be slightly longer than the time corresponding to the number of “0” consecutive bits or the number of “1” consecutive bits of the received data signal, and the received burst signal is input to the A input, whereby the first preamble signal The output becomes "H" at the falling edge, and thereafter the data signal (CR added at the end of the burst
Re-trigger at random falling edge (including C bit), continue to output "H" for a predetermined time from the last retrigger, and output a signal that becomes "L" at the burst intermittent period after the end of burst. You can Since the burst intermittent period is sufficiently longer than τ ₂ , this signal becomes "L" before the start of the next burst. The NAND gate 13 inputs the output of the monostable multivibrator 11 and the output of the retriggerable monostable multivibrator 12, so that the NAND gate 13 has a time width from the end of the preamble to the first fall of the preamble signal of the next burst. " Outputs H "pulse. The NAND gate 14 outputs the output of the retriggerable monostable multivibrator 12 and the NAND gate
Input 13 output pulses and "L" only during data signal period
Output the pulse. This output is the inverter 15
Is inverted to "H", and the monostable multivibrator 11
Is applied to the A input for performing the trigger prohibition control of. As a result, the monostable multivibrator 11 is not triggered even if the B input rises within the data signal period, and is triggered only at the first rise of the preamble signal and remains at "H" for the time width τ ₁ . Output the preamble detection signal. This preamble detection signal is the AND gate 16
, And extracts only the preamble signal from the received burst signal, which is the other input, and sends it to the subsequent phase-locked oscillator and sends "0" except during the preamble period.

[0019]

As described above, according to the present invention, the synchronization of the phase-locked oscillator can be performed at high speed, and the output of the phase-locked oscillator becomes the nominal frequency at the time of the data signal other than the preamble signal or the intermittent burst. It can be held, and the phase relationship between the transmitting side and the receiving side can be stably maintained. Also, when used on the station side, it is possible to correctly read the reception data by reproducing the clock signal which is phase-synchronized with each reception burst signal having the same frequency but different phase for each subscriber in a short preamble period.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a clock recovery circuit of the present invention.

FIG. 2 is a time chart showing the operation of the preamble extraction circuit.

FIG. 3 is a diagram showing a transmission signal targeted by the clock recovery circuit of the present invention.

[Explanation of symbols]

1 ... Preamble extraction circuit, 11 ... Monostable multivibrator, 12 ... Retriggerable monostable multivibrator, 2
... phase locked oscillator, 21 ... phase comparator, 22 ... low-pass filter, 23 ... offset setting circuit, 24 ... voltage controlled oscillator (V
CXO), 25 ... Divider

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Sumiyoshi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (3)

[Claims] 1. A clock for regenerating a clock signal from a reception burst signal composed of a preamble signal that repeats "1" and "0" in a transmission clock cycle and a data signal in which "1" and "0" randomly change in arbitrary bits. A replay circuit, a preamble extraction circuit (1) for extracting only a preamble signal from a received burst signal, and a phase for generating a clock signal of a nominal frequency corresponding to the received burst signal in phase synchronization with the extracted preamble signal Synchronous oscillator (2)
Inputting only the extracted preamble signal to the phase-locked oscillator to synchronize the phase of the output clock signal with the received burst signal, and inputting to the phase-locked oscillator during the data signal receiving period and the burst signal intermittent period. A clock recovery circuit characterized by stopping the clock and allowing it to run on its own. 2. The preamble extraction circuit (1) includes a monostable multivibrator (11) that outputs a preamble detection signal that is triggered by the first rising edge of the preamble signal and that has a time width substantially equal to the preamble duration. A retriggerable monostable multivibrator (12) that is set longer than a continuous period of “0” or “1” of a data signal, is triggered at each falling edge of the input, and outputs a pulse corresponding to a burst period; A first gate circuit (13), which receives the output of the multivibrator (11, 12) and outputs a pulse corresponding to the period from the end of the preamble to the first falling of the next preamble signal, The output of the gate circuit (13) and the output of the retriggerable monostable multivibrator (12) are input and a pulse corresponding to the data signal period is output. A second gate circuit (14, 15) applied to the trigger inhibition input of the monostable multivibrator (11), and a third gate circuit controlled by the preamble detection detection signal and passing only the preamble signal. (16) The clock recovery circuit according to claim 1, further comprising: 3. The phase-locked oscillator (2) has a frequency-divided output of the voltage-controlled oscillator (24) so that the voltage-controlled oscillator (24) generates an output of the nominal frequency when the input signal is cut off. 2. The clock recovery circuit according to claim 1, further comprising an offset setting circuit (23) for applying an offset to a control voltage corresponding to a phase difference with an input signal.