JPH0220187B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for regenerating a clock synchronized with an input clock, and more particularly to a clock regeneration method that eliminates surplus clocks with less jitter when they occur.

(b) Prior Art and Problems In conventional digital transmission, a phase-locked oscillator is used as an example of extracting a clock from a digital signal.

An example of the configuration of a conventional clock extraction method will be described below with reference to the drawings. FIG. 1 shows a conventional phase-locked oscillator. In the figure, 1 is an input terminal into which a digital signal is input, 2 is a phase comparison circuit, 3 is a low pass filter (hereinafter referred to as LPF), 4 is a voltage controlled oscillator, and 5 is an output terminal.

In FIG. 1, a digital signal clock with a clock frequency of ₀ is phase-compared with the output clock of a voltage-controlled oscillator (hereinafter referred to as VCO) 4 in a phase comparison circuit 2, and the comparison component is passed through an LPF to the VCO.
4, the output clock is inputted into a digital signal clock having a frequency of ₀ , and the output clock is outputted from the output terminal 5.

Here, in order for the phase-locked oscillator to follow the clock at high speed, the frequency bandwidth of LPF3 must be widened, and the VCO
4. It is necessary to increase the rate of change in the oscillation frequency.
However, if the input clock is interrupted in this way, the oscillation frequency of VCO4 will free-run at the upper or lower limit of the frequency band in which VCO4 operates, and as a result, the phase synchronized oscillator will become ₀ +△.
, or ₀ −△ will be output. When the next clock arrives, the phase synchronized oscillator pulls in the clock frequency ₀ again and oscillates a clock with a frequency of ₀ , but the frequency is ₀ +△ or _0.
In the process of returning from -Δ to ₀ , a clock ₀ ' having jitter with a different phase is output, and this clock ₀ ' has the disadvantage of causing errors in the judgment of received data obtained from the digital signal.

Further, in the above method, if extra pulses are inserted, there is a drawback that jitter is generated in the clock.

(c) Object of the Invention In order to solve the above-mentioned drawbacks, it is an object of the present invention to provide a new clock regeneration method that regenerates a predetermined clock even when excessive pulses are generated.

(d) Structure of the Invention In order to achieve the above object, the present invention provides a clock regeneration method in which the input clock is regenerated by inputting the input clock to a digital PLL circuit 6, in which the period of the input clock is subdivided. a differentiation circuit 9 which inputs a reference clock having a period and the input clock, differentiates the rising waveform of the input clock and outputs a positive pulse; a counter circuit 10 that outputs a positive pulse when counting up the number of pulses of the reference clock and outputting a negative pulse when counting up the number of pulses of the reference clock generated within a predetermined period longer than the one cycle; a NAND gate 11 to which the output signal of 9 and the positive pulse are input; and an AND gate 12 to which the output signal of the NAND gate 11 and the negative pulse are input;
The output signal of the AND gate 12 is converted into the digital type
By inputting the signal to the PLL circuit 6 and resetting the counter circuit 10 with the output of the AND gate 12, the NAND gate 11 and the AND
The present invention is characterized in that the gate 12 removes surplus pulses contained in the input clock.

(e) Embodiments of the Invention The outline of the clock regeneration method of the present invention is shown in FIG. Reference numeral 6 indicates a clock circuit (hereinafter abbreviated as DPLL) consisting of the digital PLL shown in FIG. 1, and 7 indicates a pseudo pulse generation circuit according to the present invention.

In FIG. 2, when no input pulse is input to the input terminal 8, the pseudo pulse generation circuit 7 generates an input clock in a pseudo manner, and when there is a surplus pulse in the input clock, it is removed. By inputting a normal input clock to the next stage clock circuit 6, a clock synchronized with the input clock is output from the output terminal 5.

Hereinafter, clock reproduction of the horizontal synchronizing signal will be explained with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram of an embodiment of a clock regeneration system using a pseudo pulse generation circuit according to the present invention. In the figure, 1, 6, and 8 indicate the same components as in Figure 1, 9 is a differential circuit, 10 is a counter circuit, and 11 is a NAND
(NAND) circuit, 12 and 15 are AND circuits, 13, 14, and 18 are flip-flops (hereinafter referred to as
(referred to as FF circuit), 16 is a counter, 17 is ROM
shows.

FIG. 4 shows waveforms at each point in FIG. 3. In the figure, the horizontal synchronization signal with a frame period of 1H, is the differential waveform of , is the output of the FF circuit 18, -1 is an extra pulse inserted at a frame period other than 1H, and is the output of the FF circuit 18 when the synchronization signal is missing. The waveform outputted from the other output terminal 18-1 shows a normal output clock, and shows an output clock caused by a pseudo pulse.

The operation shown in FIG. 3 will be explained using FIG. 4. In FIG. 3, a horizontal synchronizing signal is input to an input terminal 8, and a differential circuit 9 consisting of FF circuits 13, 14 and an AND gate 15 synchronizes with the reference clock input to the input terminal 9. The differential waveform shown in FIG. 4 is shaped, and the shaped waveform is input from the NAND gate 11 to the AND gate 12. On the other hand, the reference clock input to the clock input terminal 19 is input to the counter circuit 10. The counter circuit 10 counts the reference clock in one frame period of the horizontal synchronizing signal. This count value is input to the NAND gate 11, which outputs the differential waveform. The output differential waveform passes through the input terminal 1, and the clock circuit 6 reproduces the clock synchronized with the horizontal synchronization signal.
A portion of the output of AND gate 12 resets counter 16.

In the above, the counter 1 of the counter circuit 10
Both the count value K1 of one frame period and the count value K2 of a period slightly longer than one frame period are set in 6, and the reference clock inputted from the reference clock terminal 17 is counted by the counter 16 to match the one frame period of the horizontal synchronization signal. The count value K1 is read out from the count value K1 written in the ROM 17, and its output is latched to the FF circuit 18.
The latch output is input to NAND gate 11. In this case, when there is no output from the AND gate 12 and the counter 16 is not reset, the counter 16
outputs count value K2.

When no horizontal synchronization signal is input, when no horizontal synchronization signal is input to input terminal 8,
From the time of the previous horizontal synchronization signal, the counter 16
Counting of the reference clock is started at , and is counted up to a count value K2 with a cycle slightly longer than one frame cycle of the horizontal synchronizing signal. its count value
K2 reads the count value K2 written in the ROM 17, and latches the FF circuit 18 with its output.
This latch output is the second output terminal 1 of the FF circuit 18.
8-1 outputs the output waveform shown in FIG. is input.

When an extra pulse is inserted within the horizontal synchronizing signal period As shown in Figure 4-1, when an extra pulse is inserted within the horizontal synchronizing signal period, the differential circuit 9 generates a differential waveform corresponding to the -1 waveform. Output NAN
It is output to gate 11. On the other hand, counter circuit 1
Since the output corresponding to the count value K1 is output from 0, the surplus pulse -1 is not output from the NAN gate 11.

f. Effects of the Invention According to the present invention, the horizontal synchronization signal was conventionally deleted or an extra clock was inserted, degrading the horizontal synchronization signal, but the differential output of the horizontal synchronization signal is used as a reference for one frame period. It has the advantage that the clock of a normal horizontal synchronization signal can be shaped by synchronizing with the AND circuit using the clock count value.

[Brief explanation of drawings]

Fig. 1 shows a conventional phase synchronized oscillator, Fig. 2 shows a schematic diagram of the present invention, Fig. 3 shows a configuration diagram of an embodiment of the clock regeneration method of the present invention, and Fig. 4 shows various waveforms used in Fig. 3. shows. In the figure, 1, 8, 9, 5 are terminals, 2 is a phase comparison circuit, 3 is an LPF, 4 is a VCO, 6 is a DPLL (clock circuit), 7 is a pseudo pulse generation circuit, 9 is a differentiation circuit,
10 is a counter circuit, 11 is a NAND gate, 1
2, 15 are AND gates, 13, 14, 18 are FF
circuit, 16 is a counter, 17 is ROM, 18-1
indicates an output terminal.

Claims (1)

[Claims] 1. In a clock regeneration method in which the input clock is regenerated by inputting the input clock to a digital PLL circuit 6, a reference clock having a period obtained by subdividing the period of the input clock, and the input clock; a differentiating circuit 9 which outputs a positive pulse by differentiating the rising waveform of the input clock; A counter circuit 10 outputs a negative pulse when the number of pulses of the reference clock generated within a predetermined period longer than one cycle is counted up, and the output signal of the differentiating circuit and the positive pulse are inputted. A NAND gate 11 and an AND gate 12 are provided to input the output signal of the NAND gate and the negative pulse, and the output signal of the AND gate is converted into the digital type.
The surplus pulse contained in the input clock is removed by the NAND gate and the AND gate by inputting it to a PLL circuit and resetting the counter circuit with the output of the AND gate. Clock regeneration method.