JPH05153078A - Destuffing circuit - Google Patents

Abstract

PURPOSE:To reduce an output jitter by executing stuffing after destuffing and supplying a toothless clock signal which is generated without the continuity of stuff bits to a PLL circuit. CONSTITUTION:An input data signal 1 and the toothless clock signal 2 which is synchronized with the signal 1 are inputted to a memory circuit 5 and writing is executed. A control signal is generated so as to permit a clock signal from a master oscillator 9 to be fixed frame structure by a frame counter circuit 8 and the reading clock is generated through the use of the signal concerning reading from the memory circuit 5. As to control for inserting the stuff bit or not, the phase relation between the writing and reading clocks is monitored by a phase comparating circuit 6, period conversion is executed by a frame cycle signal from the frame counter circuit 8 by an averaging circuit 7 in order to make a stuff bit inserting interval fixed so as to stuff the input signal 1 and a data signal and the toothless clock signal are transmitted to a PLL circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system, and more particularly to a staff synchronization system using a staff technique.

[0002]

2. Description of the Related Art Generally, in this kind of staff synchronization system,
For conversion from a low-order group signal to a high-order group signal, the positions of the write clock and the read clock of the memory circuit are monitored, and when the number of bits is within k bits, one stuff bit is inserted.

When this high-order group signal is returned to the low-order group signal, P
Smoothing was performed using the LL circuit.

FIG. 3 shows an embodiment of a conventional smoothing circuit.

An input data signal 1 of low-order group information obtained by removing surplus bits such as stuff bits from a high-order group signal and a write clock signal (toothed clock signal) 2 are input to a memory circuit 10.

The signal input to the memory circuit 10 is read by the read clock signal 4 and the output data signal 3 is output.

The speeds of the read clock signal 4 are divided by the write clock signal 2 and the read clock by M by the M dividers 11 and 12, respectively, and then compared by the phase comparison circuit 13 to determine the voltage controlled oscillator 14. Feedback control is performed so that the frequency of the read clock signal 4 is controlled to become the write clock signal 2.

In this state, if the stuff bit is 1 bit, the clock signal is read out, and the clock signal hardly changes. However, when the tooth missing state due to the stuff bit as shown in FIG. The read clock signal 4 is moved by this missing clock, and the output signal moves by the number of missing bits. This will appear as jitter.

[0009]

Therefore, in the conventional circuit form, a jitter component appears when the original signal is smoothed without missing bits due to stuff bits that arrive irregularly.

Further, in order to suppress the amount of jitter, if a low-pass filter which is sufficiently low is placed in front of the voltage controlled oscillator 13,
There is a drawback that the frequency pull-in range becomes narrow.

In view of the above-mentioned drawbacks, a technical object of the present invention is to provide a destuff circuit which reduces output jitter and has a wide pull-in frequency range.

[0012]

According to the present invention, a predetermined PLL circuit is provided and N low order group signals (f _L ) are provided (N ≧ N).
In the destuffing circuit used in a digital communication system for multiplexing 1) into a higher-order group signal (f _H : f _H ≧ f _l × N) and again separating the lower-order group signal into an original signal, Only the low-order group signal is extracted from the signal, this signal is synchronized with the master clock (f _L ′) in a frame structure in which the stuff bit insertion position is a predetermined position and is not continuous, and the stuff bit insertion is averaged. A destuff circuit is obtained, which is characterized in that it is carried out periodically and then the signal is smoothed by the PLL circuit.

Further, according to the present invention, in the destuff circuit arranged before the PLL circuit, master oscillating means for generating a master clock signal having a predetermined frequency,
There is provided a destuffing circuit having stuff synchronizing means for stuff synchronizing the master clock signal so as to synchronize the input signal.

That is, the destuff circuit according to the present invention incorporates a frequency (f _L ′) slightly higher than the low-order group signal frequency (f _L ) as a master clock, and stuff synchronizes so as to synchronize with this clock signal. After that, a circuit using a conventional PLL circuit is supplied.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a destuff circuit according to an embodiment of the present invention.

The input data signal 1 and the toothless clock signal 2 synchronized with the input data signal 1 are input to the memory circuit 5 for writing.

To read from the memory circuit 5, the clock signal from the built-in master oscillator 9 is composed by the frame counter circuit 8 as shown in FIG. 2, that is, one frame is composed of N bits and the last bit of each frame. Is set to a position where the stuff bit S is inserted, and a control signal is created to have this frame structure. Using this, a read clock signal for the memory circuit 5 is created.

The control of not inserting the stuff bit is performed by monitoring the phase relationship between the write clock and the read clock by the phase comparison circuit 6, and further averaging circuit 7 in order to make the stuff bit insertion interval constant. The input signal 1 is stuffed with the frame period signal from the frame counter circuit 8 and the data signal is read from the memory circuit 5.
Send to LL circuit.

Since stuff bits are periodically inserted in this data signal, the conventional PLL circuit operates sufficiently and the output jitter component can be suppressed to a low level.

[0021]

As described above, according to the present invention, after destuffing, the stuffing is further performed to change the frame structure to eliminate the continuation of the stuffing bit, and thereby the toothless clock signal in which the surplus bits are evenly leveled is obtained. Generate,
Since this missing tooth clock signal is supplied to the PLL circuit, there is an effect that output jitter can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a destuffing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a frame structure used in the present invention.

FIG. 3 is a block diagram showing a conventional destuff circuit.

FIG. 4 is a diagram showing an input signal and a missing tooth clock signal.

[Explanation of symbols]

 1 Input Data Signal 2 Tooth Missing Clock Signal 3 Output Data Signal 4 Output Clock Signal 5 Memory Circuit 6 Phase Comparison Circuit 7 Averaging Circuit 8 Frame Counter Circuit 9 Master Oscillator 10 Memory Circuit 11, 12 M Frequency Division Circuit 13 Phase Comparison Circuit 14 Voltage controlled oscillator

Claims (2)

[Claims] 1. A predetermined PLL circuit, wherein N low order group signals (f _L ) (N ≧ 1) and high order group signals (f _H : f _H ≧) are provided.
f _l × N), and in the destuffing circuit used in the digital communication system for separating this into the low order group signal and converting it into the original signal again, only the low order group signal is extracted from the high order group signal, This signal is synchronized with a frame structure in which the stuff bit insertion position is a predetermined position and is not continuous by the master clock (f _L ′), and the stuff bit insertion is averaged and periodically performed.
A destuffing circuit characterized by smoothing a signal by an L circuit. 2. A destuffing circuit arranged in a preceding stage of a PLL circuit, wherein master oscillating means for generating a master clock signal having a predetermined frequency and stuff synchronization so as to synchronize an input signal with the master clock signal. A destuffing circuit having stuff synchronizing means.