JPS6084825A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a highly integrated CMOS.LSI by attaining the annealing technic using an electric oven which is capable of small re-distribution of implanted impurity ions, large activation and small junction leakage by performing a heat treatment with a low temperature within a specified range. CONSTITUTION:After forming gate electrodes on an Si substrate, BF2 and P are selectively implanted in P-channel regions and N-channel regions respectively by gate electrode self aligning ion implantation so as to form an amorphous layer. The shallow amorphous layer of about 0.2mum thick which is formed by implantation of BF2 or P ions is recrystallized by a heat treatment with 700 deg.C for about 30min and with 800 deg.C for about 1sec. As activation and reduction of a leakage current are carried out at the same time as the recrystallization of the amorphous layer, the heat treatment with 700-800 deg.C achieves the formation of good junctions. In addition, in case of the heat treatment with a temperature 800 deg.C or less, diffusion of P and B is small and diffusion due to re-distribution can be ignored so that a fine MOS.FET becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device. Especially, 0M
It is effective in manufacturing O8VLSI.

Conventionally, in the manufacture of semiconductor devices, annealing of an ion-implanted layer into a silicon substrate is performed at a temperature of 900° C. or higher, so that the implanted impurities are redistributed and diffused. Therefore, in the source/drain high concentration implantation layer of MO8IICT, it is difficult to miniaturize the J, MOS/FIIfT, which causes punch-through between the source and drain. In particular, in the manufacture of CMO8LSI, conventionally B was implanted into the P channel region and 88 was implanted into the N channel region to form sources and drains, so the heat treatment required to activate B required high temperatures. Since high-temperature heat treatment is required to remove defects caused by the A8 implantation of single atoms, an annealing condition of heat treatment at a temperature of about 1000° C. for about 30 minutes is used. B has a large diffusion coefficient, and in heat treatment at 100°C for 30 minutes, the diffusion due to redistribution of the implantation distribution is about 0.3 μm5, making it impossible to miniaturize p-channel MO8FBT.
This makes it difficult to achieve high integration.

The present invention eliminates such conventional drawbacks and provides an annealing technique using an electric furnace that has small redistribution of implanted impurity ions, large activation, and small junction leakage.
The purpose is to enable high integration of LSI. The present invention is characterized by heat treatment at a low temperature of 700°C to 800°C. The channel is characterized by implanting 1' into the source and drain regions to form an amorphous layer.

This will be explained below using examples. Table 1 is a 70-. chart of an example of the 0MO8LSI manufacturing process by Kinei 1iK. After forming the gate electrode on the Si substrate, B is added to the P channel region by gate electrode self-alignment ion implantation.
F2. P is selectively implanted into the N channel region to form an amorphous layer. A shallow amorphous layer of about 0.2 μm formed by BF2 or ion implantation is
It can be recrystallized by heat treatment at 700°C for about 30 minutes and at 800°C for about 1 second. Also, in the case of ``'2 and P,
Since activation and reduction of leakage current are performed simultaneously with recrystallization of the amorphous layer, a good bond can be formed by heat treatment at 700° C. to 800° C. Moreover, 800
In heat treatment at temperatures below ℃, the diffusion of P and B is small, and diffusion due to redistribution can be ignored, resulting in MOEI Fl! IT (D) miniaturization becomes possible. Figure 1 shows the wafer temperature profile of electric furnace annealing at 750°C for 2 minutes as an example of the heat treatment of the present invention. 750℃
is maintained. The wafer is 75 mm as shown in (■).
Heat treatment is performed for 2 minutes at 0°C, but (11) and (IV)
As shown in the figure, it takes 10 minutes each time to load and unload the wafers. This is because when the wafer is placed vertically and placed in and taken out of the electric furnace, if a sudden change in temperature occurs on the wafer, a slip line will be created on the wafer and the wafer will warp71). This is to make it more relaxed. There are no slip lines or warps on wafers that are taken in and out of the electric furnace at a tolerance of about 10 degrees. It is shown in Table 1.

In the manufacture of CMOB LSI, the B11'2 film and the P ion-implanted amorphous layer are annealed at t=t, and the interlayer insulating film is subjected to high-temperature, low-pressure sho and storage fjt at, for example, 775°C.
By performing this, annealing and interlayer insulating film formation can be performed simultaneously. In addition, heat treatment in an oxygen atmosphere allows formation of a thin oxide film of the gate electrode, BP, ion implantation, and ion implantation of the amorphous layer and P ion implantation. Therefore, the high temperature annealing (for example, 1000° C., 30 minutes) required for the B and H8 injection layers, which was conventionally required, can be omitted.

As explained above, by using the method for manufacturing a semiconductor device according to the present invention, diffusion of source/drain impurities in MOB'PET is small, and shallow junctions can be formed with low sheet resistance and no junction leakage. J), by applying it to the manufacturing of 0MO8LSI, it becomes possible to increase the integration of CMO8LSI.

Table 1

[Brief explanation of the drawings] Figure 1.2 Temperature profile of temperature rise and fall in heat treatment according to the present invention (1): Temperature in electric furnace (II)・(lit)・(■)
:The wafer temperature profile table shows the manufacturing process of the CMOB VLB process according to the present invention.
flowchart. Applicant: Suwa Seikosha Co., Ltd.

Claims (1)

[Claims] 111 A method for manufacturing a semiconductor device, characterized in that in iso-thermal heat treatment of a highly concentrated ion implantation layer, annealing is performed at a temperature of 700° C. to 800° C. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that an electric furnace is used to perform the annealing within an additional amount. 131 CM (In the manufacture of I B V L S process, BF is applied to the P-channel transistor source/drain region at an acceleration energy of 5 Q K, 1 x
Io”-. Inject a dose of 1 above the stomach to form an amorphous it-, then R
P is applied to the channel, transistor, source and drain regions at an acceleration energy of within 40 KgV, lX ttq.
, after forming an amorphous layer by injecting the above doping pattern, 7
A method for manufacturing a semiconductor device according to claim 1, wherein the annealing is performed at a temperature of 00°C to 800°C. (4) A method for manufacturing a semiconductor device having a thickness as set forth in claim 1, characterized in that the high concentration ion implantation layer is annealed at the same time as the interlayer insulating film is deposited under unreasonably low pressure. (5) Special I characterized by heat treatment in an oxygen atmosphere
vl' A method for manufacturing a semiconductor device according to claim 1.